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22#include "cxd2820r_priv.h"
23
24int cxd2820r_set_frontend_t2(struct dvb_frontend *fe)
25{
26 struct cxd2820r_priv *priv = fe->demodulator_priv;
27 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
28 int ret, i, bw_i;
29 u32 if_freq, if_ctl;
30 u64 num;
31 u8 buf[3], bw_param;
32 u8 bw_params1[][5] = {
33 { 0x1c, 0xb3, 0x33, 0x33, 0x33 },
34 { 0x17, 0xea, 0xaa, 0xaa, 0xaa },
35 { 0x14, 0x80, 0x00, 0x00, 0x00 },
36 { 0x11, 0xf0, 0x00, 0x00, 0x00 },
37 };
38 struct reg_val_mask tab[] = {
39 { 0x00080, 0x02, 0xff },
40 { 0x00081, 0x20, 0xff },
41 { 0x00085, 0x07, 0xff },
42 { 0x00088, 0x01, 0xff },
43 { 0x02069, 0x01, 0xff },
44
45 { 0x0207f, 0x2a, 0xff },
46 { 0x02082, 0x0a, 0xff },
47 { 0x02083, 0x0a, 0xff },
48 { 0x020cb, priv->cfg.if_agc_polarity << 6, 0x40 },
49 { 0x02070, priv->cfg.ts_mode, 0xff },
50 { 0x020b5, priv->cfg.spec_inv << 4, 0x10 },
51 { 0x02567, 0x07, 0x0f },
52 { 0x02569, 0x03, 0x03 },
53 { 0x02595, 0x1a, 0xff },
54 { 0x02596, 0x50, 0xff },
55 { 0x02a8c, 0x00, 0xff },
56 { 0x02a8d, 0x34, 0xff },
57 { 0x02a45, 0x06, 0x07 },
58 { 0x03f10, 0x0d, 0xff },
59 { 0x03f11, 0x02, 0xff },
60 { 0x03f12, 0x01, 0xff },
61 { 0x03f23, 0x2c, 0xff },
62 { 0x03f51, 0x13, 0xff },
63 { 0x03f52, 0x01, 0xff },
64 { 0x03f53, 0x00, 0xff },
65 { 0x027e6, 0x14, 0xff },
66 { 0x02786, 0x02, 0x07 },
67 { 0x02787, 0x40, 0xe0 },
68 { 0x027ef, 0x10, 0x18 },
69 };
70
71 dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz);
72
73 switch (c->bandwidth_hz) {
74 case 5000000:
75 bw_i = 0;
76 bw_param = 3;
77 break;
78 case 6000000:
79 bw_i = 1;
80 bw_param = 2;
81 break;
82 case 7000000:
83 bw_i = 2;
84 bw_param = 1;
85 break;
86 case 8000000:
87 bw_i = 3;
88 bw_param = 0;
89 break;
90 default:
91 return -EINVAL;
92 }
93
94
95 ret = cxd2820r_gpio(fe);
96 if (ret)
97 goto error;
98
99
100 if (fe->ops.tuner_ops.set_params)
101 fe->ops.tuner_ops.set_params(fe);
102
103 if (priv->delivery_system != SYS_DVBT2) {
104 for (i = 0; i < ARRAY_SIZE(tab); i++) {
105 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
106 tab[i].val, tab[i].mask);
107 if (ret)
108 goto error;
109 }
110 }
111
112 priv->delivery_system = SYS_DVBT2;
113
114
115 if (fe->ops.tuner_ops.get_if_frequency) {
116 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
117 if (ret)
118 goto error;
119 } else
120 if_freq = 0;
121
122 dbg("%s: if_freq=%d", __func__, if_freq);
123
124 num = if_freq / 1000;
125 num *= 0x1000000;
126 if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
127 buf[0] = ((if_ctl >> 16) & 0xff);
128 buf[1] = ((if_ctl >> 8) & 0xff);
129 buf[2] = ((if_ctl >> 0) & 0xff);
130
131 ret = cxd2820r_wr_regs(priv, 0x020b6, buf, 3);
132 if (ret)
133 goto error;
134
135 ret = cxd2820r_wr_regs(priv, 0x0209f, bw_params1[bw_i], 5);
136 if (ret)
137 goto error;
138
139 ret = cxd2820r_wr_reg_mask(priv, 0x020d7, bw_param << 6, 0xc0);
140 if (ret)
141 goto error;
142
143 ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
144 if (ret)
145 goto error;
146
147 ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
148 if (ret)
149 goto error;
150
151 return ret;
152error:
153 dbg("%s: failed:%d", __func__, ret);
154 return ret;
155
156}
157
158int cxd2820r_get_frontend_t2(struct dvb_frontend *fe)
159{
160 struct cxd2820r_priv *priv = fe->demodulator_priv;
161 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
162 int ret;
163 u8 buf[2];
164
165 ret = cxd2820r_rd_regs(priv, 0x0205c, buf, 2);
166 if (ret)
167 goto error;
168
169 switch ((buf[0] >> 0) & 0x07) {
170 case 0:
171 c->transmission_mode = TRANSMISSION_MODE_2K;
172 break;
173 case 1:
174 c->transmission_mode = TRANSMISSION_MODE_8K;
175 break;
176 case 2:
177 c->transmission_mode = TRANSMISSION_MODE_4K;
178 break;
179 case 3:
180 c->transmission_mode = TRANSMISSION_MODE_1K;
181 break;
182 case 4:
183 c->transmission_mode = TRANSMISSION_MODE_16K;
184 break;
185 case 5:
186 c->transmission_mode = TRANSMISSION_MODE_32K;
187 break;
188 }
189
190 switch ((buf[1] >> 4) & 0x07) {
191 case 0:
192 c->guard_interval = GUARD_INTERVAL_1_32;
193 break;
194 case 1:
195 c->guard_interval = GUARD_INTERVAL_1_16;
196 break;
197 case 2:
198 c->guard_interval = GUARD_INTERVAL_1_8;
199 break;
200 case 3:
201 c->guard_interval = GUARD_INTERVAL_1_4;
202 break;
203 case 4:
204 c->guard_interval = GUARD_INTERVAL_1_128;
205 break;
206 case 5:
207 c->guard_interval = GUARD_INTERVAL_19_128;
208 break;
209 case 6:
210 c->guard_interval = GUARD_INTERVAL_19_256;
211 break;
212 }
213
214 ret = cxd2820r_rd_regs(priv, 0x0225b, buf, 2);
215 if (ret)
216 goto error;
217
218 switch ((buf[0] >> 0) & 0x07) {
219 case 0:
220 c->fec_inner = FEC_1_2;
221 break;
222 case 1:
223 c->fec_inner = FEC_3_5;
224 break;
225 case 2:
226 c->fec_inner = FEC_2_3;
227 break;
228 case 3:
229 c->fec_inner = FEC_3_4;
230 break;
231 case 4:
232 c->fec_inner = FEC_4_5;
233 break;
234 case 5:
235 c->fec_inner = FEC_5_6;
236 break;
237 }
238
239 switch ((buf[1] >> 0) & 0x07) {
240 case 0:
241 c->modulation = QPSK;
242 break;
243 case 1:
244 c->modulation = QAM_16;
245 break;
246 case 2:
247 c->modulation = QAM_64;
248 break;
249 case 3:
250 c->modulation = QAM_256;
251 break;
252 }
253
254 ret = cxd2820r_rd_reg(priv, 0x020b5, &buf[0]);
255 if (ret)
256 goto error;
257
258 switch ((buf[0] >> 4) & 0x01) {
259 case 0:
260 c->inversion = INVERSION_OFF;
261 break;
262 case 1:
263 c->inversion = INVERSION_ON;
264 break;
265 }
266
267 return ret;
268error:
269 dbg("%s: failed:%d", __func__, ret);
270 return ret;
271}
272
273int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status)
274{
275 struct cxd2820r_priv *priv = fe->demodulator_priv;
276 int ret;
277 u8 buf[1];
278 *status = 0;
279
280 ret = cxd2820r_rd_reg(priv, 0x02010 , &buf[0]);
281 if (ret)
282 goto error;
283
284 if ((buf[0] & 0x07) == 6) {
285 if (((buf[0] >> 5) & 0x01) == 1) {
286 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
287 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
288 } else {
289 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
290 FE_HAS_VITERBI | FE_HAS_SYNC;
291 }
292 }
293
294 dbg("%s: lock=%02x", __func__, buf[0]);
295
296 return ret;
297error:
298 dbg("%s: failed:%d", __func__, ret);
299 return ret;
300}
301
302int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber)
303{
304 struct cxd2820r_priv *priv = fe->demodulator_priv;
305 int ret;
306 u8 buf[4];
307 unsigned int errbits;
308 *ber = 0;
309
310
311 ret = cxd2820r_rd_regs(priv, 0x02039, buf, sizeof(buf));
312 if (ret)
313 goto error;
314
315 if ((buf[0] >> 4) & 0x01) {
316 errbits = (buf[0] & 0x0f) << 24 | buf[1] << 16 |
317 buf[2] << 8 | buf[3];
318
319 if (errbits)
320 *ber = errbits * 64 / 16588800;
321 }
322
323 return ret;
324error:
325 dbg("%s: failed:%d", __func__, ret);
326 return ret;
327}
328
329int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe,
330 u16 *strength)
331{
332 struct cxd2820r_priv *priv = fe->demodulator_priv;
333 int ret;
334 u8 buf[2];
335 u16 tmp;
336
337 ret = cxd2820r_rd_regs(priv, 0x02026, buf, sizeof(buf));
338 if (ret)
339 goto error;
340
341 tmp = (buf[0] & 0x0f) << 8 | buf[1];
342 tmp = ~tmp & 0x0fff;
343
344
345 *strength = tmp * 0xffff / 0x0fff;
346
347 return ret;
348error:
349 dbg("%s: failed:%d", __func__, ret);
350 return ret;
351}
352
353int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr)
354{
355 struct cxd2820r_priv *priv = fe->demodulator_priv;
356 int ret;
357 u8 buf[2];
358 u16 tmp;
359
360
361 ret = cxd2820r_rd_regs(priv, 0x02028, buf, sizeof(buf));
362 if (ret)
363 goto error;
364
365 tmp = (buf[0] & 0x0f) << 8 | buf[1];
366 #define CXD2820R_LOG10_8_24 15151336
367 if (tmp)
368 *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)
369 / 100);
370 else
371 *snr = 0;
372
373 dbg("%s: dBx10=%d val=%04x", __func__, *snr, tmp);
374
375 return ret;
376error:
377 dbg("%s: failed:%d", __func__, ret);
378 return ret;
379}
380
381int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks)
382{
383 *ucblocks = 0;
384
385 return 0;
386}
387
388int cxd2820r_sleep_t2(struct dvb_frontend *fe)
389{
390 struct cxd2820r_priv *priv = fe->demodulator_priv;
391 int ret, i;
392 struct reg_val_mask tab[] = {
393 { 0x000ff, 0x1f, 0xff },
394 { 0x00085, 0x00, 0xff },
395 { 0x00088, 0x01, 0xff },
396 { 0x02069, 0x00, 0xff },
397 { 0x00081, 0x00, 0xff },
398 { 0x00080, 0x00, 0xff },
399 };
400
401 dbg("%s", __func__);
402
403 for (i = 0; i < ARRAY_SIZE(tab); i++) {
404 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
405 tab[i].mask);
406 if (ret)
407 goto error;
408 }
409
410 priv->delivery_system = SYS_UNDEFINED;
411
412 return ret;
413error:
414 dbg("%s: failed:%d", __func__, ret);
415 return ret;
416}
417
418int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe,
419 struct dvb_frontend_tune_settings *s)
420{
421 s->min_delay_ms = 1500;
422 s->step_size = fe->ops.info.frequency_stepsize * 2;
423 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
424
425 return 0;
426}
427
