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18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/i2c.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/v4l2-mediabus.h>
24#include <linux/videodev2.h>
25
26#include <media/ov772x.h>
27#include <media/soc_camera.h>
28#include <media/v4l2-ctrls.h>
29#include <media/v4l2-chip-ident.h>
30#include <media/v4l2-subdev.h>
31
32
33
34
35#define GAIN 0x00
36#define BLUE 0x01
37#define RED 0x02
38#define GREEN 0x03
39#define COM1 0x04
40#define BAVG 0x05
41#define GAVG 0x06
42#define RAVG 0x07
43#define AECH 0x08
44#define COM2 0x09
45#define PID 0x0A
46#define VER 0x0B
47#define COM3 0x0C
48#define COM4 0x0D
49#define COM5 0x0E
50#define COM6 0x0F
51#define AEC 0x10
52#define CLKRC 0x11
53#define COM7 0x12
54#define COM8 0x13
55#define COM9 0x14
56#define COM10 0x15
57#define REG16 0x16
58#define HSTART 0x17
59#define HSIZE 0x18
60#define VSTART 0x19
61#define VSIZE 0x1A
62#define PSHFT 0x1B
63#define MIDH 0x1C
64#define MIDL 0x1D
65#define LAEC 0x1F
66#define COM11 0x20
67#define BDBASE 0x22
68#define DBSTEP 0x23
69#define AEW 0x24
70#define AEB 0x25
71#define VPT 0x26
72#define REG28 0x28
73#define HOUTSIZE 0x29
74#define EXHCH 0x2A
75#define EXHCL 0x2B
76#define VOUTSIZE 0x2C
77#define ADVFL 0x2D
78#define ADVFH 0x2E
79#define YAVE 0x2F
80#define LUMHTH 0x30
81#define LUMLTH 0x31
82#define HREF 0x32
83#define DM_LNL 0x33
84#define DM_LNH 0x34
85#define ADOFF_B 0x35
86#define ADOFF_R 0x36
87#define ADOFF_GB 0x37
88#define ADOFF_GR 0x38
89#define OFF_B 0x39
90#define OFF_R 0x3A
91#define OFF_GB 0x3B
92#define OFF_GR 0x3C
93#define COM12 0x3D
94#define COM13 0x3E
95#define COM14 0x3F
96#define COM15 0x40
97#define COM16 0x41
98#define TGT_B 0x42
99#define TGT_R 0x43
100#define TGT_GB 0x44
101#define TGT_GR 0x45
102
103#define LCC0 0x46
104#define LCC1 0x47
105#define LCC2 0x48
106#define LCC3 0x49
107#define LCC4 0x4A
108#define LCC5 0x4B
109#define LCC6 0x4C
110
111#define LC_CTR 0x46
112#define LC_XC 0x47
113#define LC_YC 0x48
114#define LC_COEF 0x49
115#define LC_RADI 0x4A
116#define LC_COEFB 0x4B
117#define LC_COEFR 0x4C
118
119#define FIXGAIN 0x4D
120#define AREF0 0x4E
121#define AREF1 0x4F
122#define AREF2 0x50
123#define AREF3 0x51
124#define AREF4 0x52
125#define AREF5 0x53
126#define AREF6 0x54
127#define AREF7 0x55
128#define UFIX 0x60
129#define VFIX 0x61
130#define AWBB_BLK 0x62
131#define AWB_CTRL0 0x63
132#define DSP_CTRL1 0x64
133#define DSP_CTRL2 0x65
134#define DSP_CTRL3 0x66
135#define DSP_CTRL4 0x67
136#define AWB_BIAS 0x68
137#define AWB_CTRL1 0x69
138#define AWB_CTRL2 0x6A
139#define AWB_CTRL3 0x6B
140#define AWB_CTRL4 0x6C
141#define AWB_CTRL5 0x6D
142#define AWB_CTRL6 0x6E
143#define AWB_CTRL7 0x6F
144#define AWB_CTRL8 0x70
145#define AWB_CTRL9 0x71
146#define AWB_CTRL10 0x72
147#define AWB_CTRL11 0x73
148#define AWB_CTRL12 0x74
149#define AWB_CTRL13 0x75
150#define AWB_CTRL14 0x76
151#define AWB_CTRL15 0x77
152#define AWB_CTRL16 0x78
153#define AWB_CTRL17 0x79
154#define AWB_CTRL18 0x7A
155#define AWB_CTRL19 0x7B
156#define AWB_CTRL20 0x7C
157#define AWB_CTRL21 0x7D
158#define GAM1 0x7E
159#define GAM2 0x7F
160#define GAM3 0x80
161#define GAM4 0x81
162#define GAM5 0x82
163#define GAM6 0x83
164#define GAM7 0x84
165#define GAM8 0x85
166#define GAM9 0x86
167#define GAM10 0x87
168#define GAM11 0x88
169#define GAM12 0x89
170#define GAM13 0x8A
171#define GAM14 0x8B
172#define GAM15 0x8C
173#define SLOP 0x8D
174#define DNSTH 0x8E
175#define EDGE_STRNGT 0x8F
176#define EDGE_TRSHLD 0x90
177#define DNSOFF 0x91
178#define EDGE_UPPER 0x92
179#define EDGE_LOWER 0x93
180#define MTX1 0x94
181#define MTX2 0x95
182#define MTX3 0x96
183#define MTX4 0x97
184#define MTX5 0x98
185#define MTX6 0x99
186#define MTX_CTRL 0x9A
187#define BRIGHT 0x9B
188#define CNTRST 0x9C
189#define CNTRST_CTRL 0x9D
190#define UVAD_J0 0x9E
191#define UVAD_J1 0x9F
192#define SCAL0 0xA0
193#define SCAL1 0xA1
194#define SCAL2 0xA2
195#define FIFODLYM 0xA3
196#define FIFODLYA 0xA4
197#define SDE 0xA6
198#define USAT 0xA7
199#define VSAT 0xA8
200
201#define HUE0 0xA9
202#define HUE1 0xAA
203
204#define HUECOS 0xA9
205#define HUESIN 0xAA
206
207#define SIGN 0xAB
208#define DSPAUTO 0xAC
209
210
211
212
213
214
215#define SOFT_SLEEP_MODE 0x10
216
217#define OCAP_1x 0x00
218#define OCAP_2x 0x01
219#define OCAP_3x 0x02
220#define OCAP_4x 0x03
221
222
223#define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML)
224#define IMG_MASK (VFLIP_IMG | HFLIP_IMG)
225
226#define VFLIP_IMG 0x80
227#define HFLIP_IMG 0x40
228#define SWAP_RGB 0x20
229#define SWAP_YUV 0x10
230#define SWAP_ML 0x08
231
232#define NOTRI_CLOCK 0x04
233
234
235#define NOTRI_DATA 0x02
236
237#define SCOLOR_TEST 0x01
238
239
240
241#define PLL_BYPASS 0x00
242#define PLL_4x 0x40
243#define PLL_6x 0x80
244#define PLL_8x 0xc0
245
246#define AEC_FULL 0x00
247#define AEC_1p2 0x10
248#define AEC_1p4 0x20
249#define AEC_2p3 0x30
250
251
252#define AFR_ON_OFF 0x80
253#define AFR_SPPED 0x40
254
255#define AFR_NO_RATE 0x00
256#define AFR_1p2 0x10
257#define AFR_1p4 0x20
258#define AFR_1p8 0x30
259
260#define AF_2x 0x00
261#define AF_4x 0x04
262#define AF_8x 0x08
263#define AF_16x 0x0c
264
265#define AEC_NO_LIMIT 0x01
266
267
268
269
270#define SCCB_RESET 0x80
271
272
273#define SLCT_MASK 0x40
274#define SLCT_VGA 0x00
275#define SLCT_QVGA 0x40
276#define ITU656_ON_OFF 0x20
277
278#define FMT_MASK 0x0c
279#define FMT_GBR422 0x00
280#define FMT_RGB565 0x04
281#define FMT_RGB555 0x08
282#define FMT_RGB444 0x0c
283
284#define OFMT_MASK 0x03
285#define OFMT_YUV 0x00
286#define OFMT_P_BRAW 0x01
287#define OFMT_RGB 0x02
288#define OFMT_BRAW 0x03
289
290
291#define FAST_ALGO 0x80
292
293#define UNLMT_STEP 0x40
294
295#define BNDF_ON_OFF 0x20
296#define AEC_BND 0x10
297#define AEC_ON_OFF 0x08
298#define AGC_ON 0x04
299#define AWB_ON 0x02
300#define AEC_ON 0x01
301
302
303#define BASE_AECAGC 0x80
304
305#define GAIN_2x 0x00
306#define GAIN_4x 0x10
307#define GAIN_8x 0x20
308#define GAIN_16x 0x30
309#define GAIN_32x 0x40
310#define GAIN_64x 0x50
311#define GAIN_128x 0x60
312#define DROP_VSYNC 0x04
313#define DROP_HREF 0x02
314
315
316#define SGLF_ON_OFF 0x02
317#define SGLF_TRIG 0x01
318
319
320#define VSIZE_LSB 0x04
321
322
323#define FIFO_ON 0x80
324#define UV_ON_OFF 0x40
325#define YUV444_2_422 0x20
326#define CLR_MTRX_ON_OFF 0x10
327#define INTPLT_ON_OFF 0x08
328#define GMM_ON_OFF 0x04
329#define AUTO_BLK_ON_OFF 0x02
330#define AUTO_WHT_ON_OFF 0x01
331
332
333#define UV_MASK 0x80
334#define UV_ON 0x80
335#define UV_OFF 0x00
336#define CBAR_MASK 0x20
337#define CBAR_ON 0x20
338#define CBAR_OFF 0x00
339
340
341#define HST_VGA 0x23
342#define HST_QVGA 0x3F
343
344
345#define HSZ_VGA 0xA0
346#define HSZ_QVGA 0x50
347
348
349#define VST_VGA 0x07
350#define VST_QVGA 0x03
351
352
353#define VSZ_VGA 0xF0
354#define VSZ_QVGA 0x78
355
356
357#define HOSZ_VGA 0xA0
358#define HOSZ_QVGA 0x50
359
360
361#define VOSZ_VGA 0xF0
362#define VOSZ_QVGA 0x78
363
364
365#define AWB_ACTRL 0x80
366#define DENOISE_ACTRL 0x40
367#define EDGE_ACTRL 0x20
368#define UV_ACTRL 0x10
369#define SCAL0_ACTRL 0x08
370#define SCAL1_2_ACTRL 0x04
371
372
373
374
375#define OV7720 0x7720
376#define OV7725 0x7721
377#define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
378
379
380
381
382struct regval_list {
383 unsigned char reg_num;
384 unsigned char value;
385};
386
387struct ov772x_color_format {
388 enum v4l2_mbus_pixelcode code;
389 enum v4l2_colorspace colorspace;
390 u8 dsp3;
391 u8 com3;
392 u8 com7;
393};
394
395struct ov772x_win_size {
396 char *name;
397 __u32 width;
398 __u32 height;
399 unsigned char com7_bit;
400 const struct regval_list *regs;
401};
402
403struct ov772x_priv {
404 struct v4l2_subdev subdev;
405 struct v4l2_ctrl_handler hdl;
406 struct ov772x_camera_info *info;
407 const struct ov772x_color_format *cfmt;
408 const struct ov772x_win_size *win;
409 int model;
410 unsigned short flag_vflip:1;
411 unsigned short flag_hflip:1;
412
413 unsigned short band_filter;
414};
415
416#define ENDMARKER { 0xff, 0xff }
417
418
419
420
421static const struct regval_list ov772x_qvga_regs[] = {
422 { HSTART, HST_QVGA },
423 { HSIZE, HSZ_QVGA },
424 { VSTART, VST_QVGA },
425 { VSIZE, VSZ_QVGA },
426 { HOUTSIZE, HOSZ_QVGA },
427 { VOUTSIZE, VOSZ_QVGA },
428 ENDMARKER,
429};
430
431static const struct regval_list ov772x_vga_regs[] = {
432 { HSTART, HST_VGA },
433 { HSIZE, HSZ_VGA },
434 { VSTART, VST_VGA },
435 { VSIZE, VSZ_VGA },
436 { HOUTSIZE, HOSZ_VGA },
437 { VOUTSIZE, VOSZ_VGA },
438 ENDMARKER,
439};
440
441
442
443
444static const struct ov772x_color_format ov772x_cfmts[] = {
445 {
446 .code = V4L2_MBUS_FMT_YUYV8_2X8,
447 .colorspace = V4L2_COLORSPACE_JPEG,
448 .dsp3 = 0x0,
449 .com3 = SWAP_YUV,
450 .com7 = OFMT_YUV,
451 },
452 {
453 .code = V4L2_MBUS_FMT_YVYU8_2X8,
454 .colorspace = V4L2_COLORSPACE_JPEG,
455 .dsp3 = UV_ON,
456 .com3 = SWAP_YUV,
457 .com7 = OFMT_YUV,
458 },
459 {
460 .code = V4L2_MBUS_FMT_UYVY8_2X8,
461 .colorspace = V4L2_COLORSPACE_JPEG,
462 .dsp3 = 0x0,
463 .com3 = 0x0,
464 .com7 = OFMT_YUV,
465 },
466 {
467 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
468 .colorspace = V4L2_COLORSPACE_SRGB,
469 .dsp3 = 0x0,
470 .com3 = SWAP_RGB,
471 .com7 = FMT_RGB555 | OFMT_RGB,
472 },
473 {
474 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE,
475 .colorspace = V4L2_COLORSPACE_SRGB,
476 .dsp3 = 0x0,
477 .com3 = 0x0,
478 .com7 = FMT_RGB555 | OFMT_RGB,
479 },
480 {
481 .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
482 .colorspace = V4L2_COLORSPACE_SRGB,
483 .dsp3 = 0x0,
484 .com3 = SWAP_RGB,
485 .com7 = FMT_RGB565 | OFMT_RGB,
486 },
487 {
488 .code = V4L2_MBUS_FMT_RGB565_2X8_BE,
489 .colorspace = V4L2_COLORSPACE_SRGB,
490 .dsp3 = 0x0,
491 .com3 = 0x0,
492 .com7 = FMT_RGB565 | OFMT_RGB,
493 },
494};
495
496
497
498
499
500#define VGA_WIDTH 640
501#define VGA_HEIGHT 480
502#define QVGA_WIDTH 320
503#define QVGA_HEIGHT 240
504#define MAX_WIDTH VGA_WIDTH
505#define MAX_HEIGHT VGA_HEIGHT
506
507static const struct ov772x_win_size ov772x_win_vga = {
508 .name = "VGA",
509 .width = VGA_WIDTH,
510 .height = VGA_HEIGHT,
511 .com7_bit = SLCT_VGA,
512 .regs = ov772x_vga_regs,
513};
514
515static const struct ov772x_win_size ov772x_win_qvga = {
516 .name = "QVGA",
517 .width = QVGA_WIDTH,
518 .height = QVGA_HEIGHT,
519 .com7_bit = SLCT_QVGA,
520 .regs = ov772x_qvga_regs,
521};
522
523
524
525
526
527static struct ov772x_priv *to_ov772x(const struct i2c_client *client)
528{
529 return container_of(i2c_get_clientdata(client), struct ov772x_priv,
530 subdev);
531}
532
533static int ov772x_write_array(struct i2c_client *client,
534 const struct regval_list *vals)
535{
536 while (vals->reg_num != 0xff) {
537 int ret = i2c_smbus_write_byte_data(client,
538 vals->reg_num,
539 vals->value);
540 if (ret < 0)
541 return ret;
542 vals++;
543 }
544 return 0;
545}
546
547static int ov772x_mask_set(struct i2c_client *client,
548 u8 command,
549 u8 mask,
550 u8 set)
551{
552 s32 val = i2c_smbus_read_byte_data(client, command);
553 if (val < 0)
554 return val;
555
556 val &= ~mask;
557 val |= set & mask;
558
559 return i2c_smbus_write_byte_data(client, command, val);
560}
561
562static int ov772x_reset(struct i2c_client *client)
563{
564 int ret = i2c_smbus_write_byte_data(client, COM7, SCCB_RESET);
565 msleep(1);
566 return ret;
567}
568
569
570
571
572
573static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
574{
575 struct i2c_client *client = v4l2_get_subdevdata(sd);
576 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
577
578 if (!enable) {
579 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE);
580 return 0;
581 }
582
583 if (!priv->win || !priv->cfmt) {
584 dev_err(&client->dev, "norm or win select error\n");
585 return -EPERM;
586 }
587
588 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, 0);
589
590 dev_dbg(&client->dev, "format %d, win %s\n",
591 priv->cfmt->code, priv->win->name);
592
593 return 0;
594}
595
596static int ov772x_s_ctrl(struct v4l2_ctrl *ctrl)
597{
598 struct ov772x_priv *priv = container_of(ctrl->handler,
599 struct ov772x_priv, hdl);
600 struct v4l2_subdev *sd = &priv->subdev;
601 struct i2c_client *client = v4l2_get_subdevdata(sd);
602 int ret = 0;
603 u8 val;
604
605 switch (ctrl->id) {
606 case V4L2_CID_VFLIP:
607 val = ctrl->val ? VFLIP_IMG : 0x00;
608 priv->flag_vflip = ctrl->val;
609 if (priv->info->flags & OV772X_FLAG_VFLIP)
610 val ^= VFLIP_IMG;
611 return ov772x_mask_set(client, COM3, VFLIP_IMG, val);
612 case V4L2_CID_HFLIP:
613 val = ctrl->val ? HFLIP_IMG : 0x00;
614 priv->flag_hflip = ctrl->val;
615 if (priv->info->flags & OV772X_FLAG_HFLIP)
616 val ^= HFLIP_IMG;
617 return ov772x_mask_set(client, COM3, HFLIP_IMG, val);
618 case V4L2_CID_BAND_STOP_FILTER:
619 if (!ctrl->val) {
620
621 ret = ov772x_mask_set(client, BDBASE, 0xff, 0xff);
622 if (!ret)
623 ret = ov772x_mask_set(client, COM8,
624 BNDF_ON_OFF, 0);
625 } else {
626
627 val = 256 - ctrl->val;
628 ret = ov772x_mask_set(client, COM8,
629 BNDF_ON_OFF, BNDF_ON_OFF);
630 if (!ret)
631 ret = ov772x_mask_set(client, BDBASE,
632 0xff, val);
633 }
634 if (!ret)
635 priv->band_filter = ctrl->val;
636 return ret;
637 }
638
639 return -EINVAL;
640}
641
642static int ov772x_g_chip_ident(struct v4l2_subdev *sd,
643 struct v4l2_dbg_chip_ident *id)
644{
645 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
646
647 id->ident = priv->model;
648 id->revision = 0;
649
650 return 0;
651}
652
653#ifdef CONFIG_VIDEO_ADV_DEBUG
654static int ov772x_g_register(struct v4l2_subdev *sd,
655 struct v4l2_dbg_register *reg)
656{
657 struct i2c_client *client = v4l2_get_subdevdata(sd);
658 int ret;
659
660 reg->size = 1;
661 if (reg->reg > 0xff)
662 return -EINVAL;
663
664 ret = i2c_smbus_read_byte_data(client, reg->reg);
665 if (ret < 0)
666 return ret;
667
668 reg->val = (__u64)ret;
669
670 return 0;
671}
672
673static int ov772x_s_register(struct v4l2_subdev *sd,
674 struct v4l2_dbg_register *reg)
675{
676 struct i2c_client *client = v4l2_get_subdevdata(sd);
677
678 if (reg->reg > 0xff ||
679 reg->val > 0xff)
680 return -EINVAL;
681
682 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
683}
684#endif
685
686static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
687{
688 __u32 diff;
689 const struct ov772x_win_size *win;
690
691
692 diff = abs(width - ov772x_win_qvga.width) +
693 abs(height - ov772x_win_qvga.height);
694 win = &ov772x_win_qvga;
695
696
697 if (diff >
698 abs(width - ov772x_win_vga.width) +
699 abs(height - ov772x_win_vga.height))
700 win = &ov772x_win_vga;
701
702 return win;
703}
704
705static int ov772x_set_params(struct i2c_client *client, u32 *width, u32 *height,
706 enum v4l2_mbus_pixelcode code)
707{
708 struct ov772x_priv *priv = to_ov772x(client);
709 int ret = -EINVAL;
710 u8 val;
711 int i;
712
713
714
715
716 priv->cfmt = NULL;
717 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
718 if (code == ov772x_cfmts[i].code) {
719 priv->cfmt = ov772x_cfmts + i;
720 break;
721 }
722 }
723 if (!priv->cfmt)
724 goto ov772x_set_fmt_error;
725
726
727
728
729 priv->win = ov772x_select_win(*width, *height);
730
731
732
733
734 ov772x_reset(client);
735
736
737
738
739 if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
740
741
742
743
744
745
746
747
748 ret = ov772x_mask_set(client, DSPAUTO, EDGE_ACTRL, 0x00);
749 if (ret < 0)
750 goto ov772x_set_fmt_error;
751
752 ret = ov772x_mask_set(client,
753 EDGE_TRSHLD, OV772X_EDGE_THRESHOLD_MASK,
754 priv->info->edgectrl.threshold);
755 if (ret < 0)
756 goto ov772x_set_fmt_error;
757
758 ret = ov772x_mask_set(client,
759 EDGE_STRNGT, OV772X_EDGE_STRENGTH_MASK,
760 priv->info->edgectrl.strength);
761 if (ret < 0)
762 goto ov772x_set_fmt_error;
763
764 } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
765
766
767
768
769
770 ret = ov772x_mask_set(client,
771 EDGE_UPPER, OV772X_EDGE_UPPER_MASK,
772 priv->info->edgectrl.upper);
773 if (ret < 0)
774 goto ov772x_set_fmt_error;
775
776 ret = ov772x_mask_set(client,
777 EDGE_LOWER, OV772X_EDGE_LOWER_MASK,
778 priv->info->edgectrl.lower);
779 if (ret < 0)
780 goto ov772x_set_fmt_error;
781 }
782
783
784
785
786 ret = ov772x_write_array(client, priv->win->regs);
787 if (ret < 0)
788 goto ov772x_set_fmt_error;
789
790
791
792
793 val = priv->cfmt->dsp3;
794 if (val) {
795 ret = ov772x_mask_set(client,
796 DSP_CTRL3, UV_MASK, val);
797 if (ret < 0)
798 goto ov772x_set_fmt_error;
799 }
800
801
802
803
804 val = priv->cfmt->com3;
805 if (priv->info->flags & OV772X_FLAG_VFLIP)
806 val |= VFLIP_IMG;
807 if (priv->info->flags & OV772X_FLAG_HFLIP)
808 val |= HFLIP_IMG;
809 if (priv->flag_vflip)
810 val ^= VFLIP_IMG;
811 if (priv->flag_hflip)
812 val ^= HFLIP_IMG;
813
814 ret = ov772x_mask_set(client,
815 COM3, SWAP_MASK | IMG_MASK, val);
816 if (ret < 0)
817 goto ov772x_set_fmt_error;
818
819
820
821
822 val = priv->win->com7_bit | priv->cfmt->com7;
823 ret = ov772x_mask_set(client,
824 COM7, SLCT_MASK | FMT_MASK | OFMT_MASK,
825 val);
826 if (ret < 0)
827 goto ov772x_set_fmt_error;
828
829
830
831
832 if (priv->band_filter) {
833 ret = ov772x_mask_set(client, COM8, BNDF_ON_OFF, 1);
834 if (!ret)
835 ret = ov772x_mask_set(client, BDBASE,
836 0xff, 256 - priv->band_filter);
837 if (ret < 0)
838 goto ov772x_set_fmt_error;
839 }
840
841 *width = priv->win->width;
842 *height = priv->win->height;
843
844 return ret;
845
846ov772x_set_fmt_error:
847
848 ov772x_reset(client);
849 priv->win = NULL;
850 priv->cfmt = NULL;
851
852 return ret;
853}
854
855static int ov772x_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
856{
857 a->c.left = 0;
858 a->c.top = 0;
859 a->c.width = VGA_WIDTH;
860 a->c.height = VGA_HEIGHT;
861 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
862
863 return 0;
864}
865
866static int ov772x_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
867{
868 a->bounds.left = 0;
869 a->bounds.top = 0;
870 a->bounds.width = VGA_WIDTH;
871 a->bounds.height = VGA_HEIGHT;
872 a->defrect = a->bounds;
873 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
874 a->pixelaspect.numerator = 1;
875 a->pixelaspect.denominator = 1;
876
877 return 0;
878}
879
880static int ov772x_g_fmt(struct v4l2_subdev *sd,
881 struct v4l2_mbus_framefmt *mf)
882{
883 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
884
885 if (!priv->win || !priv->cfmt) {
886 priv->cfmt = &ov772x_cfmts[0];
887 priv->win = ov772x_select_win(VGA_WIDTH, VGA_HEIGHT);
888 }
889
890 mf->width = priv->win->width;
891 mf->height = priv->win->height;
892 mf->code = priv->cfmt->code;
893 mf->colorspace = priv->cfmt->colorspace;
894 mf->field = V4L2_FIELD_NONE;
895
896 return 0;
897}
898
899static int ov772x_s_fmt(struct v4l2_subdev *sd,
900 struct v4l2_mbus_framefmt *mf)
901{
902 struct i2c_client *client = v4l2_get_subdevdata(sd);
903 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
904 int ret = ov772x_set_params(client, &mf->width, &mf->height,
905 mf->code);
906
907 if (!ret)
908 mf->colorspace = priv->cfmt->colorspace;
909
910 return ret;
911}
912
913static int ov772x_try_fmt(struct v4l2_subdev *sd,
914 struct v4l2_mbus_framefmt *mf)
915{
916 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
917 const struct ov772x_win_size *win;
918 int i;
919
920
921
922
923 win = ov772x_select_win(mf->width, mf->height);
924
925 mf->width = win->width;
926 mf->height = win->height;
927 mf->field = V4L2_FIELD_NONE;
928
929 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++)
930 if (mf->code == ov772x_cfmts[i].code)
931 break;
932
933 if (i == ARRAY_SIZE(ov772x_cfmts)) {
934
935 if (priv->cfmt) {
936
937 mf->colorspace = priv->cfmt->colorspace;
938 mf->code = priv->cfmt->code;
939 } else {
940
941 mf->colorspace = ov772x_cfmts[0].colorspace;
942 mf->code = ov772x_cfmts[0].code;
943 }
944 } else {
945
946 mf->colorspace = ov772x_cfmts[i].colorspace;
947 }
948
949 return 0;
950}
951
952static int ov772x_video_probe(struct i2c_client *client)
953{
954 struct ov772x_priv *priv = to_ov772x(client);
955 u8 pid, ver;
956 const char *devname;
957
958
959
960
961 pid = i2c_smbus_read_byte_data(client, PID);
962 ver = i2c_smbus_read_byte_data(client, VER);
963
964 switch (VERSION(pid, ver)) {
965 case OV7720:
966 devname = "ov7720";
967 priv->model = V4L2_IDENT_OV7720;
968 break;
969 case OV7725:
970 devname = "ov7725";
971 priv->model = V4L2_IDENT_OV7725;
972 break;
973 default:
974 dev_err(&client->dev,
975 "Product ID error %x:%x\n", pid, ver);
976 return -ENODEV;
977 }
978
979 dev_info(&client->dev,
980 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
981 devname,
982 pid,
983 ver,
984 i2c_smbus_read_byte_data(client, MIDH),
985 i2c_smbus_read_byte_data(client, MIDL));
986 return v4l2_ctrl_handler_setup(&priv->hdl);
987}
988
989static const struct v4l2_ctrl_ops ov772x_ctrl_ops = {
990 .s_ctrl = ov772x_s_ctrl,
991};
992
993static struct v4l2_subdev_core_ops ov772x_subdev_core_ops = {
994 .g_chip_ident = ov772x_g_chip_ident,
995#ifdef CONFIG_VIDEO_ADV_DEBUG
996 .g_register = ov772x_g_register,
997 .s_register = ov772x_s_register,
998#endif
999};
1000
1001static int ov772x_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
1002 enum v4l2_mbus_pixelcode *code)
1003{
1004 if (index >= ARRAY_SIZE(ov772x_cfmts))
1005 return -EINVAL;
1006
1007 *code = ov772x_cfmts[index].code;
1008 return 0;
1009}
1010
1011static int ov772x_g_mbus_config(struct v4l2_subdev *sd,
1012 struct v4l2_mbus_config *cfg)
1013{
1014 struct i2c_client *client = v4l2_get_subdevdata(sd);
1015 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1016
1017 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
1018 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1019 V4L2_MBUS_DATA_ACTIVE_HIGH;
1020 cfg->type = V4L2_MBUS_PARALLEL;
1021 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
1022
1023 return 0;
1024}
1025
1026static struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {
1027 .s_stream = ov772x_s_stream,
1028 .g_mbus_fmt = ov772x_g_fmt,
1029 .s_mbus_fmt = ov772x_s_fmt,
1030 .try_mbus_fmt = ov772x_try_fmt,
1031 .cropcap = ov772x_cropcap,
1032 .g_crop = ov772x_g_crop,
1033 .enum_mbus_fmt = ov772x_enum_fmt,
1034 .g_mbus_config = ov772x_g_mbus_config,
1035};
1036
1037static struct v4l2_subdev_ops ov772x_subdev_ops = {
1038 .core = &ov772x_subdev_core_ops,
1039 .video = &ov772x_subdev_video_ops,
1040};
1041
1042
1043
1044
1045
1046static int ov772x_probe(struct i2c_client *client,
1047 const struct i2c_device_id *did)
1048{
1049 struct ov772x_priv *priv;
1050 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1051 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1052 int ret;
1053
1054 if (!icl || !icl->priv) {
1055 dev_err(&client->dev, "OV772X: missing platform data!\n");
1056 return -EINVAL;
1057 }
1058
1059 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1060 dev_err(&adapter->dev,
1061 "I2C-Adapter doesn't support "
1062 "I2C_FUNC_SMBUS_BYTE_DATA\n");
1063 return -EIO;
1064 }
1065
1066 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1067 if (!priv)
1068 return -ENOMEM;
1069
1070 priv->info = icl->priv;
1071
1072 v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops);
1073 v4l2_ctrl_handler_init(&priv->hdl, 3);
1074 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1075 V4L2_CID_VFLIP, 0, 1, 1, 0);
1076 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1077 V4L2_CID_HFLIP, 0, 1, 1, 0);
1078 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1079 V4L2_CID_BAND_STOP_FILTER, 0, 256, 1, 0);
1080 priv->subdev.ctrl_handler = &priv->hdl;
1081 if (priv->hdl.error) {
1082 int err = priv->hdl.error;
1083
1084 kfree(priv);
1085 return err;
1086 }
1087
1088 ret = ov772x_video_probe(client);
1089 if (ret) {
1090 v4l2_ctrl_handler_free(&priv->hdl);
1091 kfree(priv);
1092 }
1093
1094 return ret;
1095}
1096
1097static int ov772x_remove(struct i2c_client *client)
1098{
1099 struct ov772x_priv *priv = to_ov772x(client);
1100
1101 v4l2_device_unregister_subdev(&priv->subdev);
1102 v4l2_ctrl_handler_free(&priv->hdl);
1103 kfree(priv);
1104 return 0;
1105}
1106
1107static const struct i2c_device_id ov772x_id[] = {
1108 { "ov772x", 0 },
1109 { }
1110};
1111MODULE_DEVICE_TABLE(i2c, ov772x_id);
1112
1113static struct i2c_driver ov772x_i2c_driver = {
1114 .driver = {
1115 .name = "ov772x",
1116 },
1117 .probe = ov772x_probe,
1118 .remove = ov772x_remove,
1119 .id_table = ov772x_id,
1120};
1121
1122module_i2c_driver(ov772x_i2c_driver);
1123
1124MODULE_DESCRIPTION("SoC Camera driver for ov772x");
1125MODULE_AUTHOR("Kuninori Morimoto");
1126MODULE_LICENSE("GPL v2");
1127