LXR linux/drivers/net/can/mscan/mscan.h

   1/*
   2 * Definitions of consts/structs to drive the Freescale MSCAN.
   3 *
   4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
   5 *                         Varma Electronics Oy
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the version 2 of the GNU General Public License
   9 * as published by the Free Software Foundation
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19 */
  20
  21#ifndef __MSCAN_H__
  22#define __MSCAN_H__
  23
  24#include <linux/types.h>
  25
  26/* MSCAN control register 0 (CANCTL0) bits */
  27#define MSCAN_RXFRM             0x80
  28#define MSCAN_RXACT             0x40
  29#define MSCAN_CSWAI             0x20
  30#define MSCAN_SYNCH             0x10
  31#define MSCAN_TIME              0x08
  32#define MSCAN_WUPE              0x04
  33#define MSCAN_SLPRQ             0x02
  34#define MSCAN_INITRQ            0x01
  35
  36/* MSCAN control register 1 (CANCTL1) bits */
  37#define MSCAN_CANE              0x80
  38#define MSCAN_CLKSRC            0x40
  39#define MSCAN_LOOPB             0x20
  40#define MSCAN_LISTEN            0x10
  41#define MSCAN_BORM              0x08
  42#define MSCAN_WUPM              0x04
  43#define MSCAN_SLPAK             0x02
  44#define MSCAN_INITAK            0x01
  45
  46/* Use the MPC5XXX MSCAN variant? */
  47#ifdef CONFIG_PPC
  48#define MSCAN_FOR_MPC5XXX
  49#endif
  50
  51#ifdef MSCAN_FOR_MPC5XXX
  52#define MSCAN_CLKSRC_BUS        0
  53#define MSCAN_CLKSRC_XTAL       MSCAN_CLKSRC
  54#define MSCAN_CLKSRC_IPS        MSCAN_CLKSRC
  55#else
  56#define MSCAN_CLKSRC_BUS        MSCAN_CLKSRC
  57#define MSCAN_CLKSRC_XTAL       0
  58#endif
  59
  60/* MSCAN receiver flag register (CANRFLG) bits */
  61#define MSCAN_WUPIF             0x80
  62#define MSCAN_CSCIF             0x40
  63#define MSCAN_RSTAT1            0x20
  64#define MSCAN_RSTAT0            0x10
  65#define MSCAN_TSTAT1            0x08
  66#define MSCAN_TSTAT0            0x04
  67#define MSCAN_OVRIF             0x02
  68#define MSCAN_RXF               0x01
  69#define MSCAN_ERR_IF            (MSCAN_OVRIF | MSCAN_CSCIF)
  70#define MSCAN_RSTAT_MSK         (MSCAN_RSTAT1 | MSCAN_RSTAT0)
  71#define MSCAN_TSTAT_MSK         (MSCAN_TSTAT1 | MSCAN_TSTAT0)
  72#define MSCAN_STAT_MSK          (MSCAN_RSTAT_MSK | MSCAN_TSTAT_MSK)
  73
  74#define MSCAN_STATE_BUS_OFF     (MSCAN_RSTAT1 | MSCAN_RSTAT0 | \
  75                                 MSCAN_TSTAT1 | MSCAN_TSTAT0)
  76#define MSCAN_STATE_TX(canrflg) (((canrflg)&MSCAN_TSTAT_MSK)>>2)
  77#define MSCAN_STATE_RX(canrflg) (((canrflg)&MSCAN_RSTAT_MSK)>>4)
  78#define MSCAN_STATE_ACTIVE      0
  79#define MSCAN_STATE_WARNING     1
  80#define MSCAN_STATE_PASSIVE     2
  81#define MSCAN_STATE_BUSOFF      3
  82
  83/* MSCAN receiver interrupt enable register (CANRIER) bits */
  84#define MSCAN_WUPIE             0x80
  85#define MSCAN_CSCIE             0x40
  86#define MSCAN_RSTATE1           0x20
  87#define MSCAN_RSTATE0           0x10
  88#define MSCAN_TSTATE1           0x08
  89#define MSCAN_TSTATE0           0x04
  90#define MSCAN_OVRIE             0x02
  91#define MSCAN_RXFIE             0x01
  92
  93/* MSCAN transmitter flag register (CANTFLG) bits */
  94#define MSCAN_TXE2              0x04
  95#define MSCAN_TXE1              0x02
  96#define MSCAN_TXE0              0x01
  97#define MSCAN_TXE               (MSCAN_TXE2 | MSCAN_TXE1 | MSCAN_TXE0)
  98
  99/* MSCAN transmitter interrupt enable register (CANTIER) bits */
 100#define MSCAN_TXIE2             0x04
 101#define MSCAN_TXIE1             0x02
 102#define MSCAN_TXIE0             0x01
 103#define MSCAN_TXIE              (MSCAN_TXIE2 | MSCAN_TXIE1 | MSCAN_TXIE0)
 104
 105/* MSCAN transmitter message abort request (CANTARQ) bits */
 106#define MSCAN_ABTRQ2            0x04
 107#define MSCAN_ABTRQ1            0x02
 108#define MSCAN_ABTRQ0            0x01
 109
 110/* MSCAN transmitter message abort ack (CANTAAK) bits */
 111#define MSCAN_ABTAK2            0x04
 112#define MSCAN_ABTAK1            0x02
 113#define MSCAN_ABTAK0            0x01
 114
 115/* MSCAN transmit buffer selection (CANTBSEL) bits */
 116#define MSCAN_TX2               0x04
 117#define MSCAN_TX1               0x02
 118#define MSCAN_TX0               0x01
 119
 120/* MSCAN ID acceptance control register (CANIDAC) bits */
 121#define MSCAN_IDAM1             0x20
 122#define MSCAN_IDAM0             0x10
 123#define MSCAN_IDHIT2            0x04
 124#define MSCAN_IDHIT1            0x02
 125#define MSCAN_IDHIT0            0x01
 126
 127#define MSCAN_AF_32BIT          0x00
 128#define MSCAN_AF_16BIT          MSCAN_IDAM0
 129#define MSCAN_AF_8BIT           MSCAN_IDAM1
 130#define MSCAN_AF_CLOSED         (MSCAN_IDAM0|MSCAN_IDAM1)
 131#define MSCAN_AF_MASK           (~(MSCAN_IDAM0|MSCAN_IDAM1))
 132
 133/* MSCAN Miscellaneous Register (CANMISC) bits */
 134#define MSCAN_BOHOLD            0x01
 135
 136/* MSCAN Identifier Register (IDR) bits */
 137#define MSCAN_SFF_RTR_SHIFT     4
 138#define MSCAN_EFF_RTR_SHIFT     0
 139#define MSCAN_EFF_FLAGS         0x18    /* IDE + SRR */
 140
 141#ifdef MSCAN_FOR_MPC5XXX
 142#define _MSCAN_RESERVED_(n, num) u8 _res##n[num]
 143#define _MSCAN_RESERVED_DSR_SIZE        2
 144#else
 145#define _MSCAN_RESERVED_(n, num)
 146#define _MSCAN_RESERVED_DSR_SIZE        0
 147#endif
 148
 149/* Structure of the hardware registers */
 150struct mscan_regs {
 151        /* (see doc S12MSCANV3/D)                 MPC5200    MSCAN */
 152        u8 canctl0;                             /* + 0x00     0x00 */
 153        u8 canctl1;                             /* + 0x01     0x01 */
 154        _MSCAN_RESERVED_(1, 2);                 /* + 0x02          */
 155        u8 canbtr0;                             /* + 0x04     0x02 */
 156        u8 canbtr1;                             /* + 0x05     0x03 */
 157        _MSCAN_RESERVED_(2, 2);                 /* + 0x06          */
 158        u8 canrflg;                             /* + 0x08     0x04 */
 159        u8 canrier;                             /* + 0x09     0x05 */
 160        _MSCAN_RESERVED_(3, 2);                 /* + 0x0a          */
 161        u8 cantflg;                             /* + 0x0c     0x06 */
 162        u8 cantier;                             /* + 0x0d     0x07 */
 163        _MSCAN_RESERVED_(4, 2);                 /* + 0x0e          */
 164        u8 cantarq;                             /* + 0x10     0x08 */
 165        u8 cantaak;                             /* + 0x11     0x09 */
 166        _MSCAN_RESERVED_(5, 2);                 /* + 0x12          */
 167        u8 cantbsel;                            /* + 0x14     0x0a */
 168        u8 canidac;                             /* + 0x15     0x0b */
 169        u8 reserved;                            /* + 0x16     0x0c */
 170        _MSCAN_RESERVED_(6, 2);                 /* + 0x17          */
 171        u8 canmisc;                             /* + 0x19     0x0d */
 172        _MSCAN_RESERVED_(7, 2);                 /* + 0x1a          */
 173        u8 canrxerr;                            /* + 0x1c     0x0e */
 174        u8 cantxerr;                            /* + 0x1d     0x0f */
 175        _MSCAN_RESERVED_(8, 2);                 /* + 0x1e          */
 176        u16 canidar1_0;                         /* + 0x20     0x10 */
 177        _MSCAN_RESERVED_(9, 2);                 /* + 0x22          */
 178        u16 canidar3_2;                         /* + 0x24     0x12 */
 179        _MSCAN_RESERVED_(10, 2);                /* + 0x26          */
 180        u16 canidmr1_0;                         /* + 0x28     0x14 */
 181        _MSCAN_RESERVED_(11, 2);                /* + 0x2a          */
 182        u16 canidmr3_2;                         /* + 0x2c     0x16 */
 183        _MSCAN_RESERVED_(12, 2);                /* + 0x2e          */
 184        u16 canidar5_4;                         /* + 0x30     0x18 */
 185        _MSCAN_RESERVED_(13, 2);                /* + 0x32          */
 186        u16 canidar7_6;                         /* + 0x34     0x1a */
 187        _MSCAN_RESERVED_(14, 2);                /* + 0x36          */
 188        u16 canidmr5_4;                         /* + 0x38     0x1c */
 189        _MSCAN_RESERVED_(15, 2);                /* + 0x3a          */
 190        u16 canidmr7_6;                         /* + 0x3c     0x1e */
 191        _MSCAN_RESERVED_(16, 2);                /* + 0x3e          */
 192        struct {
 193                u16 idr1_0;                     /* + 0x40     0x20 */
 194                _MSCAN_RESERVED_(17, 2);        /* + 0x42          */
 195                u16 idr3_2;                     /* + 0x44     0x22 */
 196                _MSCAN_RESERVED_(18, 2);        /* + 0x46          */
 197                u16 dsr1_0;                     /* + 0x48     0x24 */
 198                _MSCAN_RESERVED_(19, 2);        /* + 0x4a          */
 199                u16 dsr3_2;                     /* + 0x4c     0x26 */
 200                _MSCAN_RESERVED_(20, 2);        /* + 0x4e          */
 201                u16 dsr5_4;                     /* + 0x50     0x28 */
 202                _MSCAN_RESERVED_(21, 2);        /* + 0x52          */
 203                u16 dsr7_6;                     /* + 0x54     0x2a */
 204                _MSCAN_RESERVED_(22, 2);        /* + 0x56          */
 205                u8 dlr;                         /* + 0x58     0x2c */
 206                u8 reserved;                    /* + 0x59     0x2d */
 207                _MSCAN_RESERVED_(23, 2);        /* + 0x5a          */
 208                u16 time;                       /* + 0x5c     0x2e */
 209        } rx;
 210        _MSCAN_RESERVED_(24, 2);                /* + 0x5e          */
 211        struct {
 212                u16 idr1_0;                     /* + 0x60     0x30 */
 213                _MSCAN_RESERVED_(25, 2);        /* + 0x62          */
 214                u16 idr3_2;                     /* + 0x64     0x32 */
 215                _MSCAN_RESERVED_(26, 2);        /* + 0x66          */
 216                u16 dsr1_0;                     /* + 0x68     0x34 */
 217                _MSCAN_RESERVED_(27, 2);        /* + 0x6a          */
 218                u16 dsr3_2;                     /* + 0x6c     0x36 */
 219                _MSCAN_RESERVED_(28, 2);        /* + 0x6e          */
 220                u16 dsr5_4;                     /* + 0x70     0x38 */
 221                _MSCAN_RESERVED_(29, 2);        /* + 0x72          */
 222                u16 dsr7_6;                     /* + 0x74     0x3a */
 223                _MSCAN_RESERVED_(30, 2);        /* + 0x76          */
 224                u8 dlr;                         /* + 0x78     0x3c */
 225                u8 tbpr;                        /* + 0x79     0x3d */
 226                _MSCAN_RESERVED_(31, 2);        /* + 0x7a          */
 227                u16 time;                       /* + 0x7c     0x3e */
 228        } tx;
 229        _MSCAN_RESERVED_(32, 2);                /* + 0x7e          */
 230} __packed;
 231
 232#undef _MSCAN_RESERVED_
 233#define MSCAN_REGION    sizeof(struct mscan)
 234
 235#define MSCAN_NORMAL_MODE       0
 236#define MSCAN_SLEEP_MODE        MSCAN_SLPRQ
 237#define MSCAN_INIT_MODE         (MSCAN_INITRQ | MSCAN_SLPRQ)
 238#define MSCAN_POWEROFF_MODE     (MSCAN_CSWAI | MSCAN_SLPRQ)
 239#define MSCAN_SET_MODE_RETRIES  255
 240#define MSCAN_ECHO_SKB_MAX      3
 241#define MSCAN_RX_INTS_ENABLE    (MSCAN_OVRIE | MSCAN_RXFIE | MSCAN_CSCIE | \
 242                                 MSCAN_RSTATE1 | MSCAN_RSTATE0 | \
 243                                 MSCAN_TSTATE1 | MSCAN_TSTATE0)
 244
 245/* MSCAN type variants */
 246enum {
 247        MSCAN_TYPE_MPC5200,
 248        MSCAN_TYPE_MPC5121
 249};
 250
 251#define BTR0_BRP_MASK           0x3f
 252#define BTR0_SJW_SHIFT          6
 253#define BTR0_SJW_MASK           (0x3 << BTR0_SJW_SHIFT)
 254
 255#define BTR1_TSEG1_MASK         0xf
 256#define BTR1_TSEG2_SHIFT        4
 257#define BTR1_TSEG2_MASK         (0x7 << BTR1_TSEG2_SHIFT)
 258#define BTR1_SAM_SHIFT          7
 259
 260#define BTR0_SET_BRP(brp)       (((brp) - 1) & BTR0_BRP_MASK)
 261#define BTR0_SET_SJW(sjw)       ((((sjw) - 1) << BTR0_SJW_SHIFT) & \
 262                                 BTR0_SJW_MASK)
 263
 264#define BTR1_SET_TSEG1(tseg1)   (((tseg1) - 1) &  BTR1_TSEG1_MASK)
 265#define BTR1_SET_TSEG2(tseg2)   ((((tseg2) - 1) << BTR1_TSEG2_SHIFT) & \
 266                                 BTR1_TSEG2_MASK)
 267#define BTR1_SET_SAM(sam)       ((sam) ? 1 << BTR1_SAM_SHIFT : 0)
 268
 269#define F_RX_PROGRESS   0
 270#define F_TX_PROGRESS   1
 271#define F_TX_WAIT_ALL   2
 272
 273#define TX_QUEUE_SIZE   3
 274
 275struct tx_queue_entry {
 276        struct list_head list;
 277        u8 mask;
 278        u8 id;
 279};
 280
 281struct mscan_priv {
 282        struct can_priv can;    /* must be the first member */
 283        unsigned int type;      /* MSCAN type variants */
 284        long open_time;
 285        unsigned long flags;
 286        void __iomem *reg_base; /* ioremap'ed address to registers */
 287        u8 shadow_statflg;
 288        u8 shadow_canrier;
 289        u8 cur_pri;
 290        u8 prev_buf_id;
 291        u8 tx_active;
 292
 293        struct list_head tx_head;
 294        struct tx_queue_entry tx_queue[TX_QUEUE_SIZE];
 295        struct napi_struct napi;
 296};
 297
 298extern struct net_device *alloc_mscandev(void);
 299extern int register_mscandev(struct net_device *dev, int mscan_clksrc);
 300extern void unregister_mscandev(struct net_device *dev);
 301
 302#endif /* __MSCAN_H__ */
 303