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25#ifndef _ATL2_H_
26#define _ATL2_H_
27
28#include <linux/atomic.h>
29#include <linux/netdevice.h>
30
31#ifndef _ATL2_HW_H_
32#define _ATL2_HW_H_
33
34#ifndef _ATL2_OSDEP_H_
35#define _ATL2_OSDEP_H_
36
37#include <linux/pci.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/if_ether.h>
41
42#include "atlx.h"
43
44#ifdef ETHTOOL_OPS_COMPAT
45extern int ethtool_ioctl(struct ifreq *ifr);
46#endif
47
48#define PCI_COMMAND_REGISTER PCI_COMMAND
49#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
50
51#define ATL2_WRITE_REG(a, reg, value) (iowrite32((value), \
52 ((a)->hw_addr + (reg))))
53
54#define ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr))
55
56#define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg)))
57
58#define ATL2_WRITE_REGB(a, reg, value) (iowrite8((value), \
59 ((a)->hw_addr + (reg))))
60
61#define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg)))
62
63#define ATL2_WRITE_REGW(a, reg, value) (iowrite16((value), \
64 ((a)->hw_addr + (reg))))
65
66#define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg)))
67
68#define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \
69 (iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2))))
70
71#define ATL2_READ_REG_ARRAY(a, reg, offset) \
72 (ioread32(((a)->hw_addr + (reg)) + ((offset) << 2)))
73
74#endif
75
76struct atl2_adapter;
77struct atl2_hw;
78
79
80static s32 atl2_reset_hw(struct atl2_hw *hw);
81static s32 atl2_read_mac_addr(struct atl2_hw *hw);
82static s32 atl2_init_hw(struct atl2_hw *hw);
83static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
84 u16 *duplex);
85static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr);
86static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value);
87static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data);
88static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data);
89static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value);
90static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value);
91static void atl2_set_mac_addr(struct atl2_hw *hw);
92static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue);
93static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value);
94static s32 atl2_phy_init(struct atl2_hw *hw);
95static int atl2_check_eeprom_exist(struct atl2_hw *hw);
96static void atl2_force_ps(struct atl2_hw *hw);
97
98
99
100
101#define IDLE_STATUS_RXMAC 1
102#define IDLE_STATUS_TXMAC 2
103#define IDLE_STATUS_DMAR 8
104#define IDLE_STATUS_DMAW 4
105
106
107#define MDIO_WAIT_TIMES 10
108
109
110#define MAC_CTRL_DBG_TX_BKPRESURE 0x100000
111#define MAC_CTRL_MACLP_CLK_PHY 0x8000000
112#define MAC_CTRL_HALF_LEFT_BUF_SHIFT 28
113#define MAC_CTRL_HALF_LEFT_BUF_MASK 0xF
114
115
116#define REG_SRAM_TXRAM_END 0x1500
117
118#define REG_SRAM_RXRAM_END 0x1502
119
120
121
122#define REG_TXD_BASE_ADDR_LO 0x1544
123
124#define REG_TXD_MEM_SIZE 0x1548
125
126#define REG_TXS_BASE_ADDR_LO 0x154C
127
128
129#define REG_TXS_MEM_SIZE 0x1550
130
131#define REG_RXD_BASE_ADDR_LO 0x1554
132
133
134#define REG_RXD_BUF_NUM 0x1558
135
136
137
138
139#define REG_DMAR 0x1580
140#define DMAR_EN 0x1
141
142
143#define REG_TX_CUT_THRESH 0x1590
144
145
146
147#define REG_DMAW 0x15A0
148#define DMAW_EN 0x1
149
150
151#define REG_PAUSE_ON_TH 0x15A8
152
153#define REG_PAUSE_OFF_TH 0x15AA
154
155
156
157#define REG_MB_TXD_WR_IDX 0x15f0
158#define REG_MB_RXD_RD_IDX 0x15F4
159
160
161#define ISR_TIMER 1
162#define ISR_MANUAL 2
163
164
165
166#define ISR_RXF_OV 4
167#define ISR_TXF_UR 8
168#define ISR_TXS_OV 0x10
169
170#define ISR_RXS_OV 0x20
171
172#define ISR_LINK_CHG 0x40
173#define ISR_HOST_TXD_UR 0x80
174#define ISR_HOST_RXD_OV 0x100
175#define ISR_DMAR_TO_RST 0x200
176
177#define ISR_DMAW_TO_RST 0x400
178#define ISR_PHY 0x800
179#define ISR_TS_UPDATE 0x10000
180
181#define ISR_RS_UPDATE 0x20000
182
183#define ISR_TX_EARLY 0x40000
184
185
186#define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | ISR_HOST_TXD_UR |\
187 ISR_TS_UPDATE | ISR_TX_EARLY)
188#define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | ISR_HOST_RXD_OV |\
189 ISR_RS_UPDATE)
190
191#define IMR_NORMAL_MASK (\
192 \
193 ISR_MANUAL |\
194 ISR_DMAR_TO_RST |\
195 ISR_DMAW_TO_RST |\
196 ISR_PHY |\
197 ISR_PHY_LINKDOWN |\
198 ISR_TS_UPDATE |\
199 ISR_RS_UPDATE)
200
201
202#define REG_STS_RX_PAUSE 0x1700
203#define REG_STS_RXD_OV 0x1704
204
205#define REG_STS_RXS_OV 0x1708
206
207#define REG_STS_RX_FILTER 0x170C
208
209
210
211
212
213#define MII_SMARTSPEED 0x14
214#define MII_DBG_ADDR 0x1D
215#define MII_DBG_DATA 0x1E
216
217
218#define PCI_REG_COMMAND 0x04
219#define CMD_IO_SPACE 0x0001
220#define CMD_MEMORY_SPACE 0x0002
221#define CMD_BUS_MASTER 0x0004
222
223#define MEDIA_TYPE_100M_FULL 1
224#define MEDIA_TYPE_100M_HALF 2
225#define MEDIA_TYPE_10M_FULL 3
226#define MEDIA_TYPE_10M_HALF 4
227
228#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x000F
229
230
231#define ENET_HEADER_SIZE 14
232#define MAXIMUM_ETHERNET_FRAME_SIZE 1518
233#define MINIMUM_ETHERNET_FRAME_SIZE 64
234#define ETHERNET_FCS_SIZE 4
235#define MAX_JUMBO_FRAME_SIZE 0x2000
236#define VLAN_SIZE 4
237
238struct tx_pkt_header {
239 unsigned pkt_size:11;
240 unsigned:4;
241 unsigned ins_vlan:1;
242 unsigned short vlan;
243};
244
245#define TX_PKT_HEADER_SIZE_MASK 0x7FF
246#define TX_PKT_HEADER_SIZE_SHIFT 0
247#define TX_PKT_HEADER_INS_VLAN_MASK 0x1
248#define TX_PKT_HEADER_INS_VLAN_SHIFT 15
249#define TX_PKT_HEADER_VLAN_TAG_MASK 0xFFFF
250#define TX_PKT_HEADER_VLAN_TAG_SHIFT 16
251
252struct tx_pkt_status {
253 unsigned pkt_size:11;
254 unsigned:5;
255 unsigned ok:1;
256 unsigned bcast:1;
257 unsigned mcast:1;
258 unsigned pause:1;
259 unsigned ctrl:1;
260 unsigned defer:1;
261 unsigned exc_defer:1;
262 unsigned single_col:1;
263 unsigned multi_col:1;
264 unsigned late_col:1;
265 unsigned abort_col:1;
266 unsigned underun:1;
267
268 unsigned:3;
269 unsigned update:1;
270};
271
272#define TX_PKT_STATUS_SIZE_MASK 0x7FF
273#define TX_PKT_STATUS_SIZE_SHIFT 0
274#define TX_PKT_STATUS_OK_MASK 0x1
275#define TX_PKT_STATUS_OK_SHIFT 16
276#define TX_PKT_STATUS_BCAST_MASK 0x1
277#define TX_PKT_STATUS_BCAST_SHIFT 17
278#define TX_PKT_STATUS_MCAST_MASK 0x1
279#define TX_PKT_STATUS_MCAST_SHIFT 18
280#define TX_PKT_STATUS_PAUSE_MASK 0x1
281#define TX_PKT_STATUS_PAUSE_SHIFT 19
282#define TX_PKT_STATUS_CTRL_MASK 0x1
283#define TX_PKT_STATUS_CTRL_SHIFT 20
284#define TX_PKT_STATUS_DEFER_MASK 0x1
285#define TX_PKT_STATUS_DEFER_SHIFT 21
286#define TX_PKT_STATUS_EXC_DEFER_MASK 0x1
287#define TX_PKT_STATUS_EXC_DEFER_SHIFT 22
288#define TX_PKT_STATUS_SINGLE_COL_MASK 0x1
289#define TX_PKT_STATUS_SINGLE_COL_SHIFT 23
290#define TX_PKT_STATUS_MULTI_COL_MASK 0x1
291#define TX_PKT_STATUS_MULTI_COL_SHIFT 24
292#define TX_PKT_STATUS_LATE_COL_MASK 0x1
293#define TX_PKT_STATUS_LATE_COL_SHIFT 25
294#define TX_PKT_STATUS_ABORT_COL_MASK 0x1
295#define TX_PKT_STATUS_ABORT_COL_SHIFT 26
296#define TX_PKT_STATUS_UNDERRUN_MASK 0x1
297#define TX_PKT_STATUS_UNDERRUN_SHIFT 27
298#define TX_PKT_STATUS_UPDATE_MASK 0x1
299#define TX_PKT_STATUS_UPDATE_SHIFT 31
300
301struct rx_pkt_status {
302 unsigned pkt_size:11;
303 unsigned:5;
304 unsigned ok:1;
305 unsigned bcast:1;
306 unsigned mcast:1;
307 unsigned pause:1;
308 unsigned ctrl:1;
309 unsigned crc:1;
310 unsigned code:1;
311 unsigned runt:1;
312
313 unsigned frag:1;
314
315 unsigned trunc:1;
316 unsigned align:1;
317 unsigned vlan:1;
318 unsigned:3;
319 unsigned update:1;
320 unsigned short vtag;
321 unsigned:16;
322};
323
324#define RX_PKT_STATUS_SIZE_MASK 0x7FF
325#define RX_PKT_STATUS_SIZE_SHIFT 0
326#define RX_PKT_STATUS_OK_MASK 0x1
327#define RX_PKT_STATUS_OK_SHIFT 16
328#define RX_PKT_STATUS_BCAST_MASK 0x1
329#define RX_PKT_STATUS_BCAST_SHIFT 17
330#define RX_PKT_STATUS_MCAST_MASK 0x1
331#define RX_PKT_STATUS_MCAST_SHIFT 18
332#define RX_PKT_STATUS_PAUSE_MASK 0x1
333#define RX_PKT_STATUS_PAUSE_SHIFT 19
334#define RX_PKT_STATUS_CTRL_MASK 0x1
335#define RX_PKT_STATUS_CTRL_SHIFT 20
336#define RX_PKT_STATUS_CRC_MASK 0x1
337#define RX_PKT_STATUS_CRC_SHIFT 21
338#define RX_PKT_STATUS_CODE_MASK 0x1
339#define RX_PKT_STATUS_CODE_SHIFT 22
340#define RX_PKT_STATUS_RUNT_MASK 0x1
341#define RX_PKT_STATUS_RUNT_SHIFT 23
342#define RX_PKT_STATUS_FRAG_MASK 0x1
343#define RX_PKT_STATUS_FRAG_SHIFT 24
344#define RX_PKT_STATUS_TRUNK_MASK 0x1
345#define RX_PKT_STATUS_TRUNK_SHIFT 25
346#define RX_PKT_STATUS_ALIGN_MASK 0x1
347#define RX_PKT_STATUS_ALIGN_SHIFT 26
348#define RX_PKT_STATUS_VLAN_MASK 0x1
349#define RX_PKT_STATUS_VLAN_SHIFT 27
350#define RX_PKT_STATUS_UPDATE_MASK 0x1
351#define RX_PKT_STATUS_UPDATE_SHIFT 31
352#define RX_PKT_STATUS_VLAN_TAG_MASK 0xFFFF
353#define RX_PKT_STATUS_VLAN_TAG_SHIFT 32
354
355struct rx_desc {
356 struct rx_pkt_status status;
357 unsigned char packet[1536-sizeof(struct rx_pkt_status)];
358};
359
360enum atl2_speed_duplex {
361 atl2_10_half = 0,
362 atl2_10_full = 1,
363 atl2_100_half = 2,
364 atl2_100_full = 3
365};
366
367struct atl2_spi_flash_dev {
368 const char *manu_name;
369
370 u8 cmdWRSR;
371 u8 cmdREAD;
372 u8 cmdPROGRAM;
373 u8 cmdWREN;
374 u8 cmdWRDI;
375 u8 cmdRDSR;
376 u8 cmdRDID;
377 u8 cmdSECTOR_ERASE;
378 u8 cmdCHIP_ERASE;
379};
380
381
382struct atl2_hw {
383 u8 __iomem *hw_addr;
384 void *back;
385
386 u8 preamble_len;
387 u8 max_retry;
388
389 u8 jam_ipg;
390
391
392 u8 ipgt;
393
394 u8 min_ifg;
395
396
397 u8 ipgr1;
398 u8 ipgr2;
399 u8 retry_buf;
400
401
402 u16 fc_rxd_hi;
403 u16 fc_rxd_lo;
404 u16 lcol;
405 u16 max_frame_size;
406
407 u16 MediaType;
408 u16 autoneg_advertised;
409 u16 pci_cmd_word;
410
411 u16 mii_autoneg_adv_reg;
412
413 u32 mem_rang;
414 u32 txcw;
415 u32 mc_filter_type;
416 u32 num_mc_addrs;
417 u32 collision_delta;
418 u32 tx_packet_delta;
419 u16 phy_spd_default;
420
421 u16 device_id;
422 u16 vendor_id;
423 u16 subsystem_id;
424 u16 subsystem_vendor_id;
425 u8 revision_id;
426
427
428 u8 flash_vendor;
429
430 u8 dma_fairness;
431 u8 mac_addr[ETH_ALEN];
432 u8 perm_mac_addr[ETH_ALEN];
433
434
435
436 bool phy_configured;
437};
438
439#endif
440
441struct atl2_ring_header {
442
443 void *desc;
444
445 dma_addr_t dma;
446
447 unsigned int size;
448};
449
450
451struct atl2_adapter {
452
453 struct net_device *netdev;
454 struct pci_dev *pdev;
455 u32 wol;
456 u16 link_speed;
457 u16 link_duplex;
458
459 spinlock_t stats_lock;
460
461 struct work_struct reset_task;
462 struct work_struct link_chg_task;
463 struct timer_list watchdog_timer;
464 struct timer_list phy_config_timer;
465
466 unsigned long cfg_phy;
467 bool mac_disabled;
468
469
470 dma_addr_t ring_dma;
471 void *ring_vir_addr;
472 int ring_size;
473
474 struct tx_pkt_header *txd_ring;
475 dma_addr_t txd_dma;
476
477 struct tx_pkt_status *txs_ring;
478 dma_addr_t txs_dma;
479
480 struct rx_desc *rxd_ring;
481 dma_addr_t rxd_dma;
482
483 u32 txd_ring_size;
484 u32 txs_ring_size;
485 u32 rxd_ring_size;
486
487
488
489 u32 txd_write_ptr;
490 u32 txs_next_clear;
491 u32 rxd_read_ptr;
492
493
494 atomic_t txd_read_ptr;
495 atomic_t txs_write_ptr;
496 u32 rxd_write_ptr;
497
498
499 u16 imt;
500
501 u16 ict;
502
503 unsigned long flags;
504
505 u32 bd_number;
506 bool pci_using_64;
507 bool have_msi;
508 struct atl2_hw hw;
509
510 u32 usr_cmd;
511
512
513 u32 pci_state[16];
514
515 u32 *config_space;
516};
517
518enum atl2_state_t {
519 __ATL2_TESTING,
520 __ATL2_RESETTING,
521 __ATL2_DOWN
522};
523
524#endif
525