LXR linux/drivers/net/ethernet/renesas/sh

   1/*
   2 *  SuperH Ethernet device driver
   3 *
   4 *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5 *  Copyright (C) 2008-2012 Renesas Solutions Corp.
   6 *
   7 *  This program is free software; you can redistribute it and/or modify it
   8 *  under the terms and conditions of the GNU General Public License,
   9 *  version 2, as published by the Free Software Foundation.
  10 *
  11 *  This program is distributed in the hope it will be useful, but WITHOUT
  12 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 *  more details.
  15 *  You should have received a copy of the GNU General Public License along with
  16 *  this program; if not, write to the Free Software Foundation, Inc.,
  17 *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18 *
  19 *  The full GNU General Public License is included in this distribution in
  20 *  the file called "COPYING".
  21 */
  22
  23#ifndef __SH_ETH_H__
  24#define __SH_ETH_H__
  25
  26#define CARDNAME        "sh-eth"
  27#define TX_TIMEOUT      (5*HZ)
  28#define TX_RING_SIZE    64      /* Tx ring size */
  29#define RX_RING_SIZE    64      /* Rx ring size */
  30#define TX_RING_MIN     64
  31#define RX_RING_MIN     64
  32#define TX_RING_MAX     1024
  33#define RX_RING_MAX     1024
  34#define ETHERSMALL              60
  35#define PKT_BUF_SZ              1538
  36#define SH_ETH_TSU_TIMEOUT_MS   500
  37#define SH_ETH_TSU_CAM_ENTRIES  32
  38
  39enum {
  40        /* E-DMAC registers */
  41        EDSR = 0,
  42        EDMR,
  43        EDTRR,
  44        EDRRR,
  45        EESR,
  46        EESIPR,
  47        TDLAR,
  48        TDFAR,
  49        TDFXR,
  50        TDFFR,
  51        RDLAR,
  52        RDFAR,
  53        RDFXR,
  54        RDFFR,
  55        TRSCER,
  56        RMFCR,
  57        TFTR,
  58        FDR,
  59        RMCR,
  60        EDOCR,
  61        TFUCR,
  62        RFOCR,
  63        FCFTR,
  64        RPADIR,
  65        TRIMD,
  66        RBWAR,
  67        TBRAR,
  68
  69        /* Ether registers */
  70        ECMR,
  71        ECSR,
  72        ECSIPR,
  73        PIR,
  74        PSR,
  75        RDMLR,
  76        PIPR,
  77        RFLR,
  78        IPGR,
  79        APR,
  80        MPR,
  81        PFTCR,
  82        PFRCR,
  83        RFCR,
  84        RFCF,
  85        TPAUSER,
  86        TPAUSECR,
  87        BCFR,
  88        BCFRR,
  89        GECMR,
  90        BCULR,
  91        MAHR,
  92        MALR,
  93        TROCR,
  94        CDCR,
  95        LCCR,
  96        CNDCR,
  97        CEFCR,
  98        FRECR,
  99        TSFRCR,
 100        TLFRCR,
 101        CERCR,
 102        CEECR,
 103        MAFCR,
 104        RTRATE,
 105        CSMR,
 106        RMII_MII,
 107
 108        /* TSU Absolute address */
 109        ARSTR,
 110        TSU_CTRST,
 111        TSU_FWEN0,
 112        TSU_FWEN1,
 113        TSU_FCM,
 114        TSU_BSYSL0,
 115        TSU_BSYSL1,
 116        TSU_PRISL0,
 117        TSU_PRISL1,
 118        TSU_FWSL0,
 119        TSU_FWSL1,
 120        TSU_FWSLC,
 121        TSU_QTAG0,
 122        TSU_QTAG1,
 123        TSU_QTAGM0,
 124        TSU_QTAGM1,
 125        TSU_FWSR,
 126        TSU_FWINMK,
 127        TSU_ADQT0,
 128        TSU_ADQT1,
 129        TSU_VTAG0,
 130        TSU_VTAG1,
 131        TSU_ADSBSY,
 132        TSU_TEN,
 133        TSU_POST1,
 134        TSU_POST2,
 135        TSU_POST3,
 136        TSU_POST4,
 137        TSU_ADRH0,
 138        TSU_ADRL0,
 139        TSU_ADRH31,
 140        TSU_ADRL31,
 141
 142        TXNLCR0,
 143        TXALCR0,
 144        RXNLCR0,
 145        RXALCR0,
 146        FWNLCR0,
 147        FWALCR0,
 148        TXNLCR1,
 149        TXALCR1,
 150        RXNLCR1,
 151        RXALCR1,
 152        FWNLCR1,
 153        FWALCR1,
 154
 155        /* This value must be written at last. */
 156        SH_ETH_MAX_REGISTER_OFFSET,
 157};
 158
 159static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
 160        [EDSR]  = 0x0000,
 161        [EDMR]  = 0x0400,
 162        [EDTRR] = 0x0408,
 163        [EDRRR] = 0x0410,
 164        [EESR]  = 0x0428,
 165        [EESIPR]        = 0x0430,
 166        [TDLAR] = 0x0010,
 167        [TDFAR] = 0x0014,
 168        [TDFXR] = 0x0018,
 169        [TDFFR] = 0x001c,
 170        [RDLAR] = 0x0030,
 171        [RDFAR] = 0x0034,
 172        [RDFXR] = 0x0038,
 173        [RDFFR] = 0x003c,
 174        [TRSCER]        = 0x0438,
 175        [RMFCR] = 0x0440,
 176        [TFTR]  = 0x0448,
 177        [FDR]   = 0x0450,
 178        [RMCR]  = 0x0458,
 179        [RPADIR]        = 0x0460,
 180        [FCFTR] = 0x0468,
 181        [CSMR] = 0x04E4,
 182
 183        [ECMR]  = 0x0500,
 184        [ECSR]  = 0x0510,
 185        [ECSIPR]        = 0x0518,
 186        [PIR]   = 0x0520,
 187        [PSR]   = 0x0528,
 188        [PIPR]  = 0x052c,
 189        [RFLR]  = 0x0508,
 190        [APR]   = 0x0554,
 191        [MPR]   = 0x0558,
 192        [PFTCR] = 0x055c,
 193        [PFRCR] = 0x0560,
 194        [TPAUSER]       = 0x0564,
 195        [GECMR] = 0x05b0,
 196        [BCULR] = 0x05b4,
 197        [MAHR]  = 0x05c0,
 198        [MALR]  = 0x05c8,
 199        [TROCR] = 0x0700,
 200        [CDCR]  = 0x0708,
 201        [LCCR]  = 0x0710,
 202        [CEFCR] = 0x0740,
 203        [FRECR] = 0x0748,
 204        [TSFRCR]        = 0x0750,
 205        [TLFRCR]        = 0x0758,
 206        [RFCR]  = 0x0760,
 207        [CERCR] = 0x0768,
 208        [CEECR] = 0x0770,
 209        [MAFCR] = 0x0778,
 210        [RMII_MII] =  0x0790,
 211
 212        [ARSTR] = 0x0000,
 213        [TSU_CTRST]     = 0x0004,
 214        [TSU_FWEN0]     = 0x0010,
 215        [TSU_FWEN1]     = 0x0014,
 216        [TSU_FCM]       = 0x0018,
 217        [TSU_BSYSL0]    = 0x0020,
 218        [TSU_BSYSL1]    = 0x0024,
 219        [TSU_PRISL0]    = 0x0028,
 220        [TSU_PRISL1]    = 0x002c,
 221        [TSU_FWSL0]     = 0x0030,
 222        [TSU_FWSL1]     = 0x0034,
 223        [TSU_FWSLC]     = 0x0038,
 224        [TSU_QTAG0]     = 0x0040,
 225        [TSU_QTAG1]     = 0x0044,
 226        [TSU_FWSR]      = 0x0050,
 227        [TSU_FWINMK]    = 0x0054,
 228        [TSU_ADQT0]     = 0x0048,
 229        [TSU_ADQT1]     = 0x004c,
 230        [TSU_VTAG0]     = 0x0058,
 231        [TSU_VTAG1]     = 0x005c,
 232        [TSU_ADSBSY]    = 0x0060,
 233        [TSU_TEN]       = 0x0064,
 234        [TSU_POST1]     = 0x0070,
 235        [TSU_POST2]     = 0x0074,
 236        [TSU_POST3]     = 0x0078,
 237        [TSU_POST4]     = 0x007c,
 238        [TSU_ADRH0]     = 0x0100,
 239        [TSU_ADRL0]     = 0x0104,
 240        [TSU_ADRH31]    = 0x01f8,
 241        [TSU_ADRL31]    = 0x01fc,
 242
 243        [TXNLCR0]       = 0x0080,
 244        [TXALCR0]       = 0x0084,
 245        [RXNLCR0]       = 0x0088,
 246        [RXALCR0]       = 0x008c,
 247        [FWNLCR0]       = 0x0090,
 248        [FWALCR0]       = 0x0094,
 249        [TXNLCR1]       = 0x00a0,
 250        [TXALCR1]       = 0x00a0,
 251        [RXNLCR1]       = 0x00a8,
 252        [RXALCR1]       = 0x00ac,
 253        [FWNLCR1]       = 0x00b0,
 254        [FWALCR1]       = 0x00b4,
 255};
 256
 257static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 258        [ECMR]  = 0x0100,
 259        [RFLR]  = 0x0108,
 260        [ECSR]  = 0x0110,
 261        [ECSIPR]        = 0x0118,
 262        [PIR]   = 0x0120,
 263        [PSR]   = 0x0128,
 264        [RDMLR] = 0x0140,
 265        [IPGR]  = 0x0150,
 266        [APR]   = 0x0154,
 267        [MPR]   = 0x0158,
 268        [TPAUSER]       = 0x0164,
 269        [RFCF]  = 0x0160,
 270        [TPAUSECR]      = 0x0168,
 271        [BCFRR] = 0x016c,
 272        [MAHR]  = 0x01c0,
 273        [MALR]  = 0x01c8,
 274        [TROCR] = 0x01d0,
 275        [CDCR]  = 0x01d4,
 276        [LCCR]  = 0x01d8,
 277        [CNDCR] = 0x01dc,
 278        [CEFCR] = 0x01e4,
 279        [FRECR] = 0x01e8,
 280        [TSFRCR]        = 0x01ec,
 281        [TLFRCR]        = 0x01f0,
 282        [RFCR]  = 0x01f4,
 283        [MAFCR] = 0x01f8,
 284        [RTRATE]        = 0x01fc,
 285
 286        [EDMR]  = 0x0000,
 287        [EDTRR] = 0x0008,
 288        [EDRRR] = 0x0010,
 289        [TDLAR] = 0x0018,
 290        [RDLAR] = 0x0020,
 291        [EESR]  = 0x0028,
 292        [EESIPR]        = 0x0030,
 293        [TRSCER]        = 0x0038,
 294        [RMFCR] = 0x0040,
 295        [TFTR]  = 0x0048,
 296        [FDR]   = 0x0050,
 297        [RMCR]  = 0x0058,
 298        [TFUCR] = 0x0064,
 299        [RFOCR] = 0x0068,
 300        [FCFTR] = 0x0070,
 301        [RPADIR]        = 0x0078,
 302        [TRIMD] = 0x007c,
 303        [RBWAR] = 0x00c8,
 304        [RDFAR] = 0x00cc,
 305        [TBRAR] = 0x00d4,
 306        [TDFAR] = 0x00d8,
 307};
 308
 309static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 310        [ECMR]  = 0x0160,
 311        [ECSR]  = 0x0164,
 312        [ECSIPR]        = 0x0168,
 313        [PIR]   = 0x016c,
 314        [MAHR]  = 0x0170,
 315        [MALR]  = 0x0174,
 316        [RFLR]  = 0x0178,
 317        [PSR]   = 0x017c,
 318        [TROCR] = 0x0180,
 319        [CDCR]  = 0x0184,
 320        [LCCR]  = 0x0188,
 321        [CNDCR] = 0x018c,
 322        [CEFCR] = 0x0194,
 323        [FRECR] = 0x0198,
 324        [TSFRCR]        = 0x019c,
 325        [TLFRCR]        = 0x01a0,
 326        [RFCR]  = 0x01a4,
 327        [MAFCR] = 0x01a8,
 328        [IPGR]  = 0x01b4,
 329        [APR]   = 0x01b8,
 330        [MPR]   = 0x01bc,
 331        [TPAUSER]       = 0x01c4,
 332        [BCFR]  = 0x01cc,
 333
 334        [ARSTR] = 0x0000,
 335        [TSU_CTRST]     = 0x0004,
 336        [TSU_FWEN0]     = 0x0010,
 337        [TSU_FWEN1]     = 0x0014,
 338        [TSU_FCM]       = 0x0018,
 339        [TSU_BSYSL0]    = 0x0020,
 340        [TSU_BSYSL1]    = 0x0024,
 341        [TSU_PRISL0]    = 0x0028,
 342        [TSU_PRISL1]    = 0x002c,
 343        [TSU_FWSL0]     = 0x0030,
 344        [TSU_FWSL1]     = 0x0034,
 345        [TSU_FWSLC]     = 0x0038,
 346        [TSU_QTAGM0]    = 0x0040,
 347        [TSU_QTAGM1]    = 0x0044,
 348        [TSU_ADQT0]     = 0x0048,
 349        [TSU_ADQT1]     = 0x004c,
 350        [TSU_FWSR]      = 0x0050,
 351        [TSU_FWINMK]    = 0x0054,
 352        [TSU_ADSBSY]    = 0x0060,
 353        [TSU_TEN]       = 0x0064,
 354        [TSU_POST1]     = 0x0070,
 355        [TSU_POST2]     = 0x0074,
 356        [TSU_POST3]     = 0x0078,
 357        [TSU_POST4]     = 0x007c,
 358
 359        [TXNLCR0]       = 0x0080,
 360        [TXALCR0]       = 0x0084,
 361        [RXNLCR0]       = 0x0088,
 362        [RXALCR0]       = 0x008c,
 363        [FWNLCR0]       = 0x0090,
 364        [FWALCR0]       = 0x0094,
 365        [TXNLCR1]       = 0x00a0,
 366        [TXALCR1]       = 0x00a0,
 367        [RXNLCR1]       = 0x00a8,
 368        [RXALCR1]       = 0x00ac,
 369        [FWNLCR1]       = 0x00b0,
 370        [FWALCR1]       = 0x00b4,
 371
 372        [TSU_ADRH0]     = 0x0100,
 373        [TSU_ADRL0]     = 0x0104,
 374        [TSU_ADRL31]    = 0x01fc,
 375
 376};
 377
 378/* Driver's parameters */
 379#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 380#define SH4_SKB_RX_ALIGN        32
 381#else
 382#define SH2_SH3_SKB_RX_ALIGN    2
 383#endif
 384
 385/*
 386 * Register's bits
 387 */
 388#if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) ||\
 389    defined(CONFIG_ARCH_R8A7740)
 390/* EDSR */
 391enum EDSR_BIT {
 392        EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 393};
 394#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 395
 396/* GECMR */
 397enum GECMR_BIT {
 398        GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
 399};
 400#endif
 401
 402/* EDMR */
 403enum DMAC_M_BIT {
 404        EDMR_EL = 0x40, /* Litte endian */
 405        EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 406        EDMR_SRST_GETHER = 0x03,
 407        EDMR_SRST_ETHER = 0x01,
 408};
 409
 410/* EDTRR */
 411enum DMAC_T_BIT {
 412        EDTRR_TRNS_GETHER = 0x03,
 413        EDTRR_TRNS_ETHER = 0x01,
 414};
 415
 416/* EDRRR*/
 417enum EDRRR_R_BIT {
 418        EDRRR_R = 0x01,
 419};
 420
 421/* TPAUSER */
 422enum TPAUSER_BIT {
 423        TPAUSER_TPAUSE = 0x0000ffff,
 424        TPAUSER_UNLIMITED = 0,
 425};
 426
 427/* BCFR */
 428enum BCFR_BIT {
 429        BCFR_RPAUSE = 0x0000ffff,
 430        BCFR_UNLIMITED = 0,
 431};
 432
 433/* PIR */
 434enum PIR_BIT {
 435        PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 436};
 437
 438/* PSR */
 439enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 440
 441/* EESR */
 442enum EESR_BIT {
 443        EESR_TWB1       = 0x80000000,
 444        EESR_TWB        = 0x40000000,   /* same as TWB0 */
 445        EESR_TC1        = 0x20000000,
 446        EESR_TUC        = 0x10000000,
 447        EESR_ROC        = 0x08000000,
 448        EESR_TABT       = 0x04000000,
 449        EESR_RABT       = 0x02000000,
 450        EESR_RFRMER     = 0x01000000,   /* same as RFCOF */
 451        EESR_ADE        = 0x00800000,
 452        EESR_ECI        = 0x00400000,
 453        EESR_FTC        = 0x00200000,   /* same as TC or TC0 */
 454        EESR_TDE        = 0x00100000,
 455        EESR_TFE        = 0x00080000,   /* same as TFUF */
 456        EESR_FRC        = 0x00040000,   /* same as FR */
 457        EESR_RDE        = 0x00020000,
 458        EESR_RFE        = 0x00010000,
 459        EESR_CND        = 0x00000800,
 460        EESR_DLC        = 0x00000400,
 461        EESR_CD         = 0x00000200,
 462        EESR_RTO        = 0x00000100,
 463        EESR_RMAF       = 0x00000080,
 464        EESR_CEEF       = 0x00000040,
 465        EESR_CELF       = 0x00000020,
 466        EESR_RRF        = 0x00000010,
 467        EESR_RTLF       = 0x00000008,
 468        EESR_RTSF       = 0x00000004,
 469        EESR_PRE        = 0x00000002,
 470        EESR_CERF       = 0x00000001,
 471};
 472
 473#define DEFAULT_TX_CHECK        (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
 474                                 EESR_RTO)
 475#define DEFAULT_EESR_ERR_CHECK  (EESR_TWB | EESR_TABT | EESR_RABT | \
 476                                 EESR_RDE | EESR_RFRMER | EESR_ADE | \
 477                                 EESR_TFE | EESR_TDE | EESR_ECI)
 478#define DEFAULT_TX_ERROR_CHECK  (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
 479                                 EESR_TFE)
 480
 481/* EESIPR */
 482enum DMAC_IM_BIT {
 483        DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 484        DMAC_M_RABT = 0x02000000,
 485        DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 486        DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 487        DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 488        DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 489        DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 490        DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 491        DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 492        DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 493        DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 494        DMAC_M_RINT1 = 0x00000001,
 495};
 496
 497/* Receive descriptor bit */
 498enum RD_STS_BIT {
 499        RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
 500        RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
 501        RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 502        RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 503        RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 504        RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 505        RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 506        RD_RFS1 = 0x00000001,
 507};
 508#define RDF1ST  RD_RFP1
 509#define RDFEND  RD_RFP0
 510#define RD_RFP  (RD_RFP1|RD_RFP0)
 511
 512/* FCFTR */
 513enum FCFTR_BIT {
 514        FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 515        FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 516        FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 517};
 518#define DEFAULT_FIFO_F_D_RFF    (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
 519#define DEFAULT_FIFO_F_D_RFD    (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
 520
 521/* Transfer descriptor bit */
 522enum TD_STS_BIT {
 523        TD_TACT = 0x80000000,
 524        TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
 525        TD_TFP0 = 0x10000000,
 526};
 527#define TDF1ST  TD_TFP1
 528#define TDFEND  TD_TFP0
 529#define TD_TFP  (TD_TFP1|TD_TFP0)
 530
 531/* RMCR */
 532#define DEFAULT_RMCR_VALUE      0x00000000
 533
 534/* ECMR */
 535enum FELIC_MODE_BIT {
 536        ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
 537        ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
 538        ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 539        ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 540        ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 541        ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
 542        ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
 543};
 544
 545/* ECSR */
 546enum ECSR_STATUS_BIT {
 547        ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 548        ECSR_LCHNG = 0x04,
 549        ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 550};
 551
 552#define DEFAULT_ECSR_INIT       (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
 553                                 ECSR_ICD | ECSIPR_MPDIP)
 554
 555/* ECSIPR */
 556enum ECSIPR_STATUS_MASK_BIT {
 557        ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
 558        ECSIPR_LCHNGIP = 0x04,
 559        ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
 560};
 561
 562#define DEFAULT_ECSIPR_INIT     (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
 563                                 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 564
 565/* APR */
 566enum APR_BIT {
 567        APR_AP = 0x00000001,
 568};
 569
 570/* MPR */
 571enum MPR_BIT {
 572        MPR_MP = 0x00000001,
 573};
 574
 575/* TRSCER */
 576enum DESC_I_BIT {
 577        DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 578        DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 579        DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 580        DESC_I_RINT1 = 0x0001,
 581};
 582
 583/* RPADIR */
 584enum RPADIR_BIT {
 585        RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 586        RPADIR_PADR = 0x0003f,
 587};
 588
 589/* FDR */
 590#define DEFAULT_FDR_INIT        0x00000707
 591
 592/* ARSTR */
 593enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
 594
 595/* TSU_FWEN0 */
 596enum TSU_FWEN0_BIT {
 597        TSU_FWEN0_0 = 0x00000001,
 598};
 599
 600/* TSU_ADSBSY */
 601enum TSU_ADSBSY_BIT {
 602        TSU_ADSBSY_0 = 0x00000001,
 603};
 604
 605/* TSU_TEN */
 606enum TSU_TEN_BIT {
 607        TSU_TEN_0 = 0x80000000,
 608};
 609
 610/* TSU_FWSL0 */
 611enum TSU_FWSL0_BIT {
 612        TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
 613        TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
 614        TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
 615};
 616
 617/* TSU_FWSLC */
 618enum TSU_FWSLC_BIT {
 619        TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
 620        TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
 621        TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
 622        TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
 623        TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
 624};
 625
 626/* TSU_VTAGn */
 627#define TSU_VTAG_ENABLE         0x80000000
 628#define TSU_VTAG_VID_MASK       0x00000fff
 629
 630/*
 631 * The sh ether Tx buffer descriptors.
 632 * This structure should be 20 bytes.
 633 */
 634struct sh_eth_txdesc {
 635        u32 status;             /* TD0 */
 636#if defined(__LITTLE_ENDIAN)
 637        u16 pad0;               /* TD1 */
 638        u16 buffer_length;      /* TD1 */
 639#else
 640        u16 buffer_length;      /* TD1 */
 641        u16 pad0;               /* TD1 */
 642#endif
 643        u32 addr;               /* TD2 */
 644        u32 pad1;               /* padding data */
 645} __attribute__((aligned(2), packed));
 646
 647/*
 648 * The sh ether Rx buffer descriptors.
 649 * This structure should be 20 bytes.
 650 */
 651struct sh_eth_rxdesc {
 652        u32 status;             /* RD0 */
 653#if defined(__LITTLE_ENDIAN)
 654        u16 frame_length;       /* RD1 */
 655        u16 buffer_length;      /* RD1 */
 656#else
 657        u16 buffer_length;      /* RD1 */
 658        u16 frame_length;       /* RD1 */
 659#endif
 660        u32 addr;               /* RD2 */
 661        u32 pad0;               /* padding data */
 662} __attribute__((aligned(2), packed));
 663
 664/* This structure is used by each CPU dependency handling. */
 665struct sh_eth_cpu_data {
 666        /* optional functions */
 667        void (*chip_reset)(struct net_device *ndev);
 668        void (*set_duplex)(struct net_device *ndev);
 669        void (*set_rate)(struct net_device *ndev);
 670
 671        /* mandatory initialize value */
 672        unsigned long eesipr_value;
 673
 674        /* optional initialize value */
 675        unsigned long ecsr_value;
 676        unsigned long ecsipr_value;
 677        unsigned long fdr_value;
 678        unsigned long fcftr_value;
 679        unsigned long rpadir_value;
 680        unsigned long rmcr_value;
 681
 682        /* interrupt checking mask */
 683        unsigned long tx_check;
 684        unsigned long eesr_err_check;
 685        unsigned long tx_error_check;
 686
 687        /* hardware features */
 688        unsigned no_psr:1;              /* EtherC DO NOT have PSR */
 689        unsigned apr:1;                 /* EtherC have APR */
 690        unsigned mpr:1;                 /* EtherC have MPR */
 691        unsigned tpauser:1;             /* EtherC have TPAUSER */
 692        unsigned bculr:1;               /* EtherC have BCULR */
 693        unsigned tsu:1;                 /* EtherC have TSU */
 694        unsigned hw_swap:1;             /* E-DMAC have DE bit in EDMR */
 695        unsigned rpadir:1;              /* E-DMAC have RPADIR */
 696        unsigned no_trimd:1;            /* E-DMAC DO NOT have TRIMD */
 697        unsigned no_ade:1;      /* E-DMAC DO NOT have ADE bit in EESR */
 698        unsigned hw_crc:1;      /* E-DMAC have CSMR */
 699        unsigned select_mii:1;  /* EtherC have RMII_MII (MII select register) */
 700};
 701
 702struct sh_eth_private {
 703        struct platform_device *pdev;
 704        struct sh_eth_cpu_data *cd;
 705        const u16 *reg_offset;
 706        void __iomem *addr;
 707        void __iomem *tsu_addr;
 708        u32 num_rx_ring;
 709        u32 num_tx_ring;
 710        dma_addr_t rx_desc_dma;
 711        dma_addr_t tx_desc_dma;
 712        struct sh_eth_rxdesc *rx_ring;
 713        struct sh_eth_txdesc *tx_ring;
 714        struct sk_buff **rx_skbuff;
 715        struct sk_buff **tx_skbuff;
 716        spinlock_t lock;
 717        u32 cur_rx, dirty_rx;   /* Producer/consumer ring indices */
 718        u32 cur_tx, dirty_tx;
 719        u32 rx_buf_sz;          /* Based on MTU+slack. */
 720        int edmac_endian;
 721        /* MII transceiver section. */
 722        u32 phy_id;                                     /* PHY ID */
 723        struct mii_bus *mii_bus;        /* MDIO bus control */
 724        struct phy_device *phydev;      /* PHY device control */
 725        enum phy_state link;
 726        phy_interface_t phy_interface;
 727        int msg_enable;
 728        int speed;
 729        int duplex;
 730        int port;               /* for TSU */
 731        int vlan_num_ids;       /* for VLAN tag filter */
 732
 733        unsigned no_ether_link:1;
 734        unsigned ether_link_active_low:1;
 735};
 736
 737static inline void sh_eth_soft_swap(char *src, int len)
 738{
 739#ifdef __LITTLE_ENDIAN__
 740        u32 *p = (u32 *)src;
 741        u32 *maxp;
 742        maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
 743
 744        for (; p < maxp; p++)
 745                *p = swab32(*p);
 746#endif
 747}
 748
 749static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
 750                                int enum_index)
 751{
 752        struct sh_eth_private *mdp = netdev_priv(ndev);
 753
 754        iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
 755}
 756
 757static inline unsigned long sh_eth_read(struct net_device *ndev,
 758                                        int enum_index)
 759{
 760        struct sh_eth_private *mdp = netdev_priv(ndev);
 761
 762        return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
 763}
 764
 765static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
 766                                          int enum_index)
 767{
 768        return mdp->tsu_addr + mdp->reg_offset[enum_index];
 769}
 770
 771static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
 772                                unsigned long data, int enum_index)
 773{
 774        iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
 775}
 776
 777static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
 778                                        int enum_index)
 779{
 780        return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
 781}
 782
 783#endif  /* #ifndef __SH_ETH_H__ */
 784