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17#ifndef EEPROM_H
18#define EEPROM_H
19
20#define AR_EEPROM_MODAL_SPURS 5
21
22#include "../ath.h"
23#include <net/cfg80211.h>
24#include "ar9003_eeprom.h"
25
26#ifdef __BIG_ENDIAN
27#define AR5416_EEPROM_MAGIC 0x5aa5
28#else
29#define AR5416_EEPROM_MAGIC 0xa55a
30#endif
31
32#define CTRY_DEBUG 0x1ff
33#define CTRY_DEFAULT 0
34
35#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
36#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
37#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
38#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
39#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
40#define AR_EEPROM_EEPCAP_MAXQCU_S 4
41#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
42#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
43#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
44
45#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
46#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
47#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
48#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
49#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
50#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
51
52#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
53#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
54
55#define AR5416_EEPROM_MAGIC_OFFSET 0x0
56#define AR5416_EEPROM_S 2
57#define AR5416_EEPROM_OFFSET 0x2000
58#define AR5416_EEPROM_MAX 0xae0
59
60#define AR5416_EEPROM_START_ADDR \
61 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
62
63#define SD_NO_CTL 0xE0
64#define NO_CTL 0xff
65#define CTL_MODE_M 0xf
66#define CTL_11A 0
67#define CTL_11B 1
68#define CTL_11G 2
69#define CTL_2GHT20 5
70#define CTL_5GHT20 6
71#define CTL_2GHT40 7
72#define CTL_5GHT40 8
73
74#define EXT_ADDITIVE (0x8000)
75#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
76#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
77#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
78
79#define SUB_NUM_CTL_MODES_AT_5G_40 2
80#define SUB_NUM_CTL_MODES_AT_2G_40 3
81
82#define POWER_CORRECTION_FOR_TWO_CHAIN 6
83#define POWER_CORRECTION_FOR_THREE_CHAIN 10
84
85
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87
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90
91
92
93
94
95#define AR9285_RDEXT_DEFAULT 0x1F
96
97#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
98#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
99#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
100
101#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
102#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
103 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
104#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
105 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
106
107#define EEP_RFSILENT_ENABLED 0x0001
108#define EEP_RFSILENT_ENABLED_S 0
109#define EEP_RFSILENT_POLARITY 0x0002
110#define EEP_RFSILENT_POLARITY_S 1
111#define EEP_RFSILENT_GPIO_SEL (AR_SREV_9462(ah) ? 0x00fc : 0x001c)
112#define EEP_RFSILENT_GPIO_SEL_S 2
113
114#define AR5416_OPFLAGS_11A 0x01
115#define AR5416_OPFLAGS_11G 0x02
116#define AR5416_OPFLAGS_N_5G_HT40 0x04
117#define AR5416_OPFLAGS_N_2G_HT40 0x08
118#define AR5416_OPFLAGS_N_5G_HT20 0x10
119#define AR5416_OPFLAGS_N_2G_HT20 0x20
120
121#define AR5416_EEP_NO_BACK_VER 0x1
122#define AR5416_EEP_VER 0xE
123#define AR5416_EEP_VER_MINOR_MASK 0x0FFF
124#define AR5416_EEP_MINOR_VER_2 0x2
125#define AR5416_EEP_MINOR_VER_3 0x3
126#define AR5416_EEP_MINOR_VER_7 0x7
127#define AR5416_EEP_MINOR_VER_9 0x9
128#define AR5416_EEP_MINOR_VER_16 0x10
129#define AR5416_EEP_MINOR_VER_17 0x11
130#define AR5416_EEP_MINOR_VER_19 0x13
131#define AR5416_EEP_MINOR_VER_20 0x14
132#define AR5416_EEP_MINOR_VER_21 0x15
133#define AR5416_EEP_MINOR_VER_22 0x16
134
135#define AR5416_NUM_5G_CAL_PIERS 8
136#define AR5416_NUM_2G_CAL_PIERS 4
137#define AR5416_NUM_5G_20_TARGET_POWERS 8
138#define AR5416_NUM_5G_40_TARGET_POWERS 8
139#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
140#define AR5416_NUM_2G_20_TARGET_POWERS 4
141#define AR5416_NUM_2G_40_TARGET_POWERS 4
142#define AR5416_NUM_CTLS 24
143#define AR5416_NUM_BAND_EDGES 8
144#define AR5416_NUM_PD_GAINS 4
145#define AR5416_PD_GAINS_IN_MASK 4
146#define AR5416_PD_GAIN_ICEPTS 5
147#define AR5416_NUM_PDADC_VALUES 128
148#define AR5416_BCHAN_UNUSED 0xFF
149#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
150#define AR5416_MAX_CHAINS 3
151#define AR9300_MAX_CHAINS 3
152#define AR5416_PWR_TABLE_OFFSET_DB -5
153
154
155#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
156#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
157#define AR5416_EEP_RXGAIN_ORIG 2
158
159
160#define AR5416_EEP_TXGAIN_ORIGINAL 0
161#define AR5416_EEP_TXGAIN_HIGH_POWER 1
162
163#define AR5416_EEP4K_START_LOC 64
164#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
165#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
166#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
167#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
168#define AR5416_EEP4K_NUM_CTLS 12
169#define AR5416_EEP4K_NUM_BAND_EDGES 4
170#define AR5416_EEP4K_NUM_PD_GAINS 2
171#define AR5416_EEP4K_MAX_CHAINS 1
172
173#define AR9280_TX_GAIN_TABLE_SIZE 22
174
175#define AR9287_EEP_VER 0xE
176#define AR9287_EEP_VER_MINOR_MASK 0xFFF
177#define AR9287_EEP_MINOR_VER_1 0x1
178#define AR9287_EEP_MINOR_VER_2 0x2
179#define AR9287_EEP_MINOR_VER_3 0x3
180#define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3
181#define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER
182#define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1
183
184#define AR9287_EEP_START_LOC 128
185#define AR9287_HTC_EEP_START_LOC 256
186#define AR9287_NUM_2G_CAL_PIERS 3
187#define AR9287_NUM_2G_CCK_TARGET_POWERS 3
188#define AR9287_NUM_2G_20_TARGET_POWERS 3
189#define AR9287_NUM_2G_40_TARGET_POWERS 3
190#define AR9287_NUM_CTLS 12
191#define AR9287_NUM_BAND_EDGES 4
192#define AR9287_PD_GAIN_ICEPTS 1
193#define AR9287_EEPMISC_BIG_ENDIAN 0x01
194#define AR9287_EEPMISC_WOW 0x02
195#define AR9287_MAX_CHAINS 2
196#define AR9287_ANT_16S 32
197
198#define AR9287_DATA_SZ 32
199
200#define AR9287_PWR_TABLE_OFFSET_DB -5
201
202#define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
203
204#define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
205#define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
206
207#define LNA_CTL_BUF_MODE BIT(0)
208#define LNA_CTL_ISEL_LO BIT(1)
209#define LNA_CTL_ISEL_HI BIT(2)
210#define LNA_CTL_BUF_IN BIT(3)
211#define LNA_CTL_FEM_BAND BIT(4)
212#define LNA_CTL_LOCAL_BIAS BIT(5)
213#define LNA_CTL_FORCE_XPA BIT(6)
214#define LNA_CTL_USE_ANT1 BIT(7)
215
216enum eeprom_param {
217 EEP_NFTHRESH_5,
218 EEP_NFTHRESH_2,
219 EEP_MAC_MSW,
220 EEP_MAC_MID,
221 EEP_MAC_LSW,
222 EEP_REG_0,
223 EEP_OP_CAP,
224 EEP_OP_MODE,
225 EEP_RF_SILENT,
226 EEP_OB_5,
227 EEP_DB_5,
228 EEP_OB_2,
229 EEP_DB_2,
230 EEP_MINOR_REV,
231 EEP_TX_MASK,
232 EEP_RX_MASK,
233 EEP_FSTCLK_5G,
234 EEP_RXGAIN_TYPE,
235 EEP_OL_PWRCTRL,
236 EEP_TXGAIN_TYPE,
237 EEP_RC_CHAIN_MASK,
238 EEP_DAC_HPWR_5G,
239 EEP_FRAC_N_5G,
240 EEP_DEV_TYPE,
241 EEP_TEMPSENSE_SLOPE,
242 EEP_TEMPSENSE_SLOPE_PAL_ON,
243 EEP_PWR_TABLE_OFFSET,
244 EEP_PAPRD,
245 EEP_MODAL_VER,
246 EEP_ANT_DIV_CTL1,
247 EEP_CHAIN_MASK_REDUCE,
248 EEP_ANTENNA_GAIN_2G,
249 EEP_ANTENNA_GAIN_5G,
250};
251
252enum ar5416_rates {
253 rate6mb, rate9mb, rate12mb, rate18mb,
254 rate24mb, rate36mb, rate48mb, rate54mb,
255 rate1l, rate2l, rate2s, rate5_5l,
256 rate5_5s, rate11l, rate11s, rateXr,
257 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
258 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
259 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
260 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
261 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
262 Ar5416RateSize
263};
264
265enum ath9k_hal_freq_band {
266 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
267 ATH9K_HAL_FREQ_BAND_2GHZ = 1
268};
269
270struct base_eep_header {
271 u16 length;
272 u16 checksum;
273 u16 version;
274 u8 opCapFlags;
275 u8 eepMisc;
276 u16 regDmn[2];
277 u8 macAddr[6];
278 u8 rxMask;
279 u8 txMask;
280 u16 rfSilent;
281 u16 blueToothOptions;
282 u16 deviceCap;
283 u32 binBuildNumber;
284 u8 deviceType;
285 u8 pwdclkind;
286 u8 fastClk5g;
287 u8 divChain;
288 u8 rxGainType;
289 u8 dacHiPwrMode_5G;
290 u8 openLoopPwrCntl;
291 u8 dacLpMode;
292 u8 txGainType;
293 u8 rcChainMask;
294 u8 desiredScaleCCK;
295 u8 pwr_table_offset;
296 u8 frac_n_5g;
297 u8 futureBase_3[21];
298} __packed;
299
300struct base_eep_header_4k {
301 u16 length;
302 u16 checksum;
303 u16 version;
304 u8 opCapFlags;
305 u8 eepMisc;
306 u16 regDmn[2];
307 u8 macAddr[6];
308 u8 rxMask;
309 u8 txMask;
310 u16 rfSilent;
311 u16 blueToothOptions;
312 u16 deviceCap;
313 u32 binBuildNumber;
314 u8 deviceType;
315 u8 txGainType;
316} __packed;
317
318
319struct spur_chan {
320 u16 spurChan;
321 u8 spurRangeLow;
322 u8 spurRangeHigh;
323} __packed;
324
325struct modal_eep_header {
326 u32 antCtrlChain[AR5416_MAX_CHAINS];
327 u32 antCtrlCommon;
328 u8 antennaGainCh[AR5416_MAX_CHAINS];
329 u8 switchSettling;
330 u8 txRxAttenCh[AR5416_MAX_CHAINS];
331 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
332 u8 adcDesiredSize;
333 u8 pgaDesiredSize;
334 u8 xlnaGainCh[AR5416_MAX_CHAINS];
335 u8 txEndToXpaOff;
336 u8 txEndToRxOn;
337 u8 txFrameToXpaOn;
338 u8 thresh62;
339 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
340 u8 xpdGain;
341 u8 xpd;
342 u8 iqCalICh[AR5416_MAX_CHAINS];
343 u8 iqCalQCh[AR5416_MAX_CHAINS];
344 u8 pdGainOverlap;
345 u8 ob;
346 u8 db;
347 u8 xpaBiasLvl;
348 u8 pwrDecreaseFor2Chain;
349 u8 pwrDecreaseFor3Chain;
350 u8 txFrameToDataStart;
351 u8 txFrameToPaOn;
352 u8 ht40PowerIncForPdadc;
353 u8 bswAtten[AR5416_MAX_CHAINS];
354 u8 bswMargin[AR5416_MAX_CHAINS];
355 u8 swSettleHt40;
356 u8 xatten2Db[AR5416_MAX_CHAINS];
357 u8 xatten2Margin[AR5416_MAX_CHAINS];
358 u8 ob_ch1;
359 u8 db_ch1;
360 u8 lna_ctl;
361 u8 miscBits;
362 u16 xpaBiasLvlFreq[3];
363 u8 futureModal[6];
364
365 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
366} __packed;
367
368struct calDataPerFreqOpLoop {
369 u8 pwrPdg[2][5];
370 u8 vpdPdg[2][5];
371 u8 pcdac[2][5];
372 u8 empty[2][5];
373} __packed;
374
375struct modal_eep_4k_header {
376 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
377 u32 antCtrlCommon;
378 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
379 u8 switchSettling;
380 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
381 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
382 u8 adcDesiredSize;
383 u8 pgaDesiredSize;
384 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
385 u8 txEndToXpaOff;
386 u8 txEndToRxOn;
387 u8 txFrameToXpaOn;
388 u8 thresh62;
389 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
390 u8 xpdGain;
391 u8 xpd;
392 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
393 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
394 u8 pdGainOverlap;
395#ifdef __BIG_ENDIAN_BITFIELD
396 u8 ob_1:4, ob_0:4;
397 u8 db1_1:4, db1_0:4;
398#else
399 u8 ob_0:4, ob_1:4;
400 u8 db1_0:4, db1_1:4;
401#endif
402 u8 xpaBiasLvl;
403 u8 txFrameToDataStart;
404 u8 txFrameToPaOn;
405 u8 ht40PowerIncForPdadc;
406 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
407 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
408 u8 swSettleHt40;
409 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
410 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
411#ifdef __BIG_ENDIAN_BITFIELD
412 u8 db2_1:4, db2_0:4;
413#else
414 u8 db2_0:4, db2_1:4;
415#endif
416 u8 version;
417#ifdef __BIG_ENDIAN_BITFIELD
418 u8 ob_3:4, ob_2:4;
419 u8 antdiv_ctl1:4, ob_4:4;
420 u8 db1_3:4, db1_2:4;
421 u8 antdiv_ctl2:4, db1_4:4;
422 u8 db2_2:4, db2_3:4;
423 u8 reserved:4, db2_4:4;
424#else
425 u8 ob_2:4, ob_3:4;
426 u8 ob_4:4, antdiv_ctl1:4;
427 u8 db1_2:4, db1_3:4;
428 u8 db1_4:4, antdiv_ctl2:4;
429 u8 db2_2:4, db2_3:4;
430 u8 db2_4:4, reserved:4;
431#endif
432 u8 tx_diversity;
433 u8 flc_pwr_thresh;
434 u8 bb_scale_smrt_antenna;
435#define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f
436 u8 futureModal[1];
437 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
438} __packed;
439
440struct base_eep_ar9287_header {
441 u16 length;
442 u16 checksum;
443 u16 version;
444 u8 opCapFlags;
445 u8 eepMisc;
446 u16 regDmn[2];
447 u8 macAddr[6];
448 u8 rxMask;
449 u8 txMask;
450 u16 rfSilent;
451 u16 blueToothOptions;
452 u16 deviceCap;
453 u32 binBuildNumber;
454 u8 deviceType;
455 u8 openLoopPwrCntl;
456 int8_t pwrTableOffset;
457 int8_t tempSensSlope;
458 int8_t tempSensSlopePalOn;
459 u8 futureBase[29];
460} __packed;
461
462struct modal_eep_ar9287_header {
463 u32 antCtrlChain[AR9287_MAX_CHAINS];
464 u32 antCtrlCommon;
465 int8_t antennaGainCh[AR9287_MAX_CHAINS];
466 u8 switchSettling;
467 u8 txRxAttenCh[AR9287_MAX_CHAINS];
468 u8 rxTxMarginCh[AR9287_MAX_CHAINS];
469 int8_t adcDesiredSize;
470 u8 txEndToXpaOff;
471 u8 txEndToRxOn;
472 u8 txFrameToXpaOn;
473 u8 thresh62;
474 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
475 u8 xpdGain;
476 u8 xpd;
477 int8_t iqCalICh[AR9287_MAX_CHAINS];
478 int8_t iqCalQCh[AR9287_MAX_CHAINS];
479 u8 pdGainOverlap;
480 u8 xpaBiasLvl;
481 u8 txFrameToDataStart;
482 u8 txFrameToPaOn;
483 u8 ht40PowerIncForPdadc;
484 u8 bswAtten[AR9287_MAX_CHAINS];
485 u8 bswMargin[AR9287_MAX_CHAINS];
486 u8 swSettleHt40;
487 u8 version;
488 u8 db1;
489 u8 db2;
490 u8 ob_cck;
491 u8 ob_psk;
492 u8 ob_qam;
493 u8 ob_pal_off;
494 u8 futureModal[30];
495 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
496} __packed;
497
498struct cal_data_per_freq {
499 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
500 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
501} __packed;
502
503struct cal_data_per_freq_4k {
504 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
505 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
506} __packed;
507
508struct cal_target_power_leg {
509 u8 bChannel;
510 u8 tPow2x[4];
511} __packed;
512
513struct cal_target_power_ht {
514 u8 bChannel;
515 u8 tPow2x[8];
516} __packed;
517
518struct cal_ctl_edges {
519 u8 bChannel;
520 u8 ctl;
521} __packed;
522
523struct cal_data_op_loop_ar9287 {
524 u8 pwrPdg[2][5];
525 u8 vpdPdg[2][5];
526 u8 pcdac[2][5];
527 u8 empty[2][5];
528} __packed;
529
530struct cal_data_per_freq_ar9287 {
531 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
532 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
533} __packed;
534
535union cal_data_per_freq_ar9287_u {
536 struct cal_data_op_loop_ar9287 calDataOpen;
537 struct cal_data_per_freq_ar9287 calDataClose;
538} __packed;
539
540struct cal_ctl_data_ar9287 {
541 struct cal_ctl_edges
542 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
543} __packed;
544
545struct cal_ctl_data {
546 struct cal_ctl_edges
547 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
548} __packed;
549
550struct cal_ctl_data_4k {
551 struct cal_ctl_edges
552 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
553} __packed;
554
555struct ar5416_eeprom_def {
556 struct base_eep_header baseEepHeader;
557 u8 custData[64];
558 struct modal_eep_header modalHeader[2];
559 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
560 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
561 struct cal_data_per_freq
562 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
563 struct cal_data_per_freq
564 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
565 struct cal_target_power_leg
566 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
567 struct cal_target_power_ht
568 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
569 struct cal_target_power_ht
570 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
571 struct cal_target_power_leg
572 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
573 struct cal_target_power_leg
574 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
575 struct cal_target_power_ht
576 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
577 struct cal_target_power_ht
578 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
579 u8 ctlIndex[AR5416_NUM_CTLS];
580 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
581 u8 padding;
582} __packed;
583
584struct ar5416_eeprom_4k {
585 struct base_eep_header_4k baseEepHeader;
586 u8 custData[20];
587 struct modal_eep_4k_header modalHeader;
588 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
589 struct cal_data_per_freq_4k
590 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
591 struct cal_target_power_leg
592 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
593 struct cal_target_power_leg
594 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
595 struct cal_target_power_ht
596 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
597 struct cal_target_power_ht
598 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
599 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
600 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
601 u8 padding;
602} __packed;
603
604struct ar9287_eeprom {
605 struct base_eep_ar9287_header baseEepHeader;
606 u8 custData[AR9287_DATA_SZ];
607 struct modal_eep_ar9287_header modalHeader;
608 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
609 union cal_data_per_freq_ar9287_u
610 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
611 struct cal_target_power_leg
612 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
613 struct cal_target_power_leg
614 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
615 struct cal_target_power_ht
616 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
617 struct cal_target_power_ht
618 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
619 u8 ctlIndex[AR9287_NUM_CTLS];
620 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
621 u8 padding;
622} __packed;
623
624enum reg_ext_bitmap {
625 REG_EXT_FCC_MIDBAND = 0,
626 REG_EXT_JAPAN_MIDBAND = 1,
627 REG_EXT_FCC_DFS_HT40 = 2,
628 REG_EXT_JAPAN_NONDFS_HT40 = 3,
629 REG_EXT_JAPAN_DFS_HT40 = 4
630};
631
632struct ath9k_country_entry {
633 u16 countryCode;
634 u16 regDmnEnum;
635 u16 regDmn5G;
636 u16 regDmn2G;
637 u8 isMultidomain;
638 u8 iso[3];
639};
640
641struct eeprom_ops {
642 int (*check_eeprom)(struct ath_hw *hw);
643 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
644 bool (*fill_eeprom)(struct ath_hw *hw);
645 u32 (*dump_eeprom)(struct ath_hw *hw, bool dump_base_hdr, u8 *buf,
646 u32 len, u32 size);
647 int (*get_eeprom_ver)(struct ath_hw *hw);
648 int (*get_eeprom_rev)(struct ath_hw *hw);
649 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
650 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
651 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
652 u16 cfgCtl, u8 twiceAntennaReduction,
653 u8 powerLimit, bool test);
654 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
655};
656
657void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val);
658void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
659 u32 shift, u32 val);
660int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
661 int16_t targetLeft,
662 int16_t targetRight);
663bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
664 u16 *indexL, u16 *indexR);
665bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
666void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
667 int eep_start_loc, int size);
668void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
669 u8 *pVpdList, u16 numIntercepts,
670 u8 *pRetVpdList);
671void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
672 struct ath9k_channel *chan,
673 struct cal_target_power_leg *powInfo,
674 u16 numChannels,
675 struct cal_target_power_leg *pNewPower,
676 u16 numRates, bool isExtTarget);
677void ath9k_hw_get_target_powers(struct ath_hw *ah,
678 struct ath9k_channel *chan,
679 struct cal_target_power_ht *powInfo,
680 u16 numChannels,
681 struct cal_target_power_ht *pNewPower,
682 u16 numRates, bool isHt40Target);
683u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
684 bool is2GHz, int num_band_edges);
685u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit,
686 u8 antenna_reduction);
687void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
688int ath9k_hw_eeprom_init(struct ath_hw *ah);
689
690void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
691 struct ath9k_channel *chan,
692 void *pRawDataSet,
693 u8 *bChans, u16 availPiers,
694 u16 tPdGainOverlap,
695 u16 *pPdGainBoundaries, u8 *pPDADCValues,
696 u16 numXpdGains);
697
698static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
699{
700 if (fbin == AR5416_BCHAN_UNUSED)
701 return fbin;
702
703 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
704}
705
706#define ar5416_get_ntxchains(_txchainmask) \
707 (((_txchainmask >> 2) & 1) + \
708 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
709
710extern const struct eeprom_ops eep_def_ops;
711extern const struct eeprom_ops eep_4k_ops;
712extern const struct eeprom_ops eep_ar9287_ops;
713extern const struct eeprom_ops eep_ar9287_ops;
714extern const struct eeprom_ops eep_ar9300_ops;
715
716#endif
717
