1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#include <linux/gfp.h>
25#include <linux/sched.h>
26
27#include "wlcore.h"
28#include "debug.h"
29#include "acx.h"
30#include "rx.h"
31#include "tx.h"
32#include "io.h"
33#include "hw_ops.h"
34
35
36
37
38
39#include "../wl12xx/reg.h"
40
41static u32 wlcore_rx_get_buf_size(struct wl1271 *wl,
42 u32 rx_pkt_desc)
43{
44 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN)
45 return (rx_pkt_desc & ALIGNED_RX_BUF_SIZE_MASK) >>
46 ALIGNED_RX_BUF_SIZE_SHIFT;
47
48 return (rx_pkt_desc & RX_BUF_SIZE_MASK) >> RX_BUF_SIZE_SHIFT_DIV;
49}
50
51static u32 wlcore_rx_get_align_buf_size(struct wl1271 *wl, u32 pkt_len)
52{
53 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN)
54 return ALIGN(pkt_len, WL12XX_BUS_BLOCK_SIZE);
55
56 return pkt_len;
57}
58
59static void wl1271_rx_status(struct wl1271 *wl,
60 struct wl1271_rx_descriptor *desc,
61 struct ieee80211_rx_status *status,
62 u8 beacon)
63{
64 memset(status, 0, sizeof(struct ieee80211_rx_status));
65
66 if ((desc->flags & WL1271_RX_DESC_BAND_MASK) == WL1271_RX_DESC_BAND_BG)
67 status->band = IEEE80211_BAND_2GHZ;
68 else
69 status->band = IEEE80211_BAND_5GHZ;
70
71 status->rate_idx = wlcore_rate_to_idx(wl, desc->rate, status->band);
72
73
74 if (desc->rate <= wl->hw_min_ht_rate)
75 status->flag |= RX_FLAG_HT;
76
77 status->signal = desc->rssi;
78
79
80
81
82
83
84 wl->noise = desc->rssi - (desc->snr >> 1);
85
86 status->freq = ieee80211_channel_to_frequency(desc->channel,
87 status->band);
88
89 if (desc->flags & WL1271_RX_DESC_ENCRYPT_MASK) {
90 u8 desc_err_code = desc->status & WL1271_RX_DESC_STATUS_MASK;
91
92 status->flag |= RX_FLAG_IV_STRIPPED | RX_FLAG_MMIC_STRIPPED |
93 RX_FLAG_DECRYPTED;
94
95 if (unlikely(desc_err_code == WL1271_RX_DESC_MIC_FAIL)) {
96 status->flag |= RX_FLAG_MMIC_ERROR;
97 wl1271_warning("Michael MIC error");
98 }
99 }
100}
101
102static int wl1271_rx_handle_data(struct wl1271 *wl, u8 *data, u32 length,
103 enum wl_rx_buf_align rx_align, u8 *hlid)
104{
105 struct wl1271_rx_descriptor *desc;
106 struct sk_buff *skb;
107 struct ieee80211_hdr *hdr;
108 u8 *buf;
109 u8 beacon = 0;
110 u8 is_data = 0;
111 u8 reserved = 0;
112 u16 seq_num;
113 u32 pkt_data_len;
114
115
116
117
118
119 if (unlikely(wl->plt))
120 return -EINVAL;
121
122 pkt_data_len = wlcore_hw_get_rx_packet_len(wl, data, length);
123 if (!pkt_data_len) {
124 wl1271_error("Invalid packet arrived from HW. length %d",
125 length);
126 return -EINVAL;
127 }
128
129 if (rx_align == WLCORE_RX_BUF_UNALIGNED)
130 reserved = RX_BUF_ALIGN;
131
132
133 desc = (struct wl1271_rx_descriptor *) data;
134
135 if (desc->packet_class == WL12XX_RX_CLASS_LOGGER) {
136 size_t len = length - sizeof(*desc);
137 wl12xx_copy_fwlog(wl, data + sizeof(*desc), len);
138 wake_up_interruptible(&wl->fwlog_waitq);
139 return 0;
140 }
141
142 switch (desc->status & WL1271_RX_DESC_STATUS_MASK) {
143
144 case WL1271_RX_DESC_DRIVER_RX_Q_FAIL:
145 case WL1271_RX_DESC_DECRYPT_FAIL:
146 wl1271_warning("corrupted packet in RX with status: 0x%x",
147 desc->status & WL1271_RX_DESC_STATUS_MASK);
148 return -EINVAL;
149 case WL1271_RX_DESC_SUCCESS:
150 case WL1271_RX_DESC_MIC_FAIL:
151 break;
152 default:
153 wl1271_error("invalid RX descriptor status: 0x%x",
154 desc->status & WL1271_RX_DESC_STATUS_MASK);
155 return -EINVAL;
156 }
157
158
159 skb = __dev_alloc_skb(pkt_data_len + reserved, GFP_KERNEL);
160 if (!skb) {
161 wl1271_error("Couldn't allocate RX frame");
162 return -ENOMEM;
163 }
164
165
166 skb_reserve(skb, reserved);
167
168 buf = skb_put(skb, pkt_data_len);
169
170
171
172
173
174
175
176 memcpy(buf, data + sizeof(*desc), pkt_data_len);
177 if (rx_align == WLCORE_RX_BUF_PADDED)
178 skb_pull(skb, RX_BUF_ALIGN);
179
180 *hlid = desc->hlid;
181
182 hdr = (struct ieee80211_hdr *)skb->data;
183 if (ieee80211_is_beacon(hdr->frame_control))
184 beacon = 1;
185 if (ieee80211_is_data_present(hdr->frame_control))
186 is_data = 1;
187
188 wl1271_rx_status(wl, desc, IEEE80211_SKB_RXCB(skb), beacon);
189 wlcore_hw_set_rx_csum(wl, desc, skb);
190
191 seq_num = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
192 wl1271_debug(DEBUG_RX, "rx skb 0x%p: %d B %s seq %d hlid %d", skb,
193 skb->len - desc->pad_len,
194 beacon ? "beacon" : "",
195 seq_num, *hlid);
196
197 skb_queue_tail(&wl->deferred_rx_queue, skb);
198 queue_work(wl->freezable_wq, &wl->netstack_work);
199
200 return is_data;
201}
202
203int wlcore_rx(struct wl1271 *wl, struct wl_fw_status_1 *status)
204{
205 unsigned long active_hlids[BITS_TO_LONGS(WL12XX_MAX_LINKS)] = {0};
206 u32 buf_size;
207 u32 fw_rx_counter = status->fw_rx_counter % wl->num_rx_desc;
208 u32 drv_rx_counter = wl->rx_counter % wl->num_rx_desc;
209 u32 rx_counter;
210 u32 pkt_len, align_pkt_len;
211 u32 pkt_offset, des;
212 u8 hlid;
213 enum wl_rx_buf_align rx_align;
214 int ret = 0;
215
216 while (drv_rx_counter != fw_rx_counter) {
217 buf_size = 0;
218 rx_counter = drv_rx_counter;
219 while (rx_counter != fw_rx_counter) {
220 des = le32_to_cpu(status->rx_pkt_descs[rx_counter]);
221 pkt_len = wlcore_rx_get_buf_size(wl, des);
222 align_pkt_len = wlcore_rx_get_align_buf_size(wl,
223 pkt_len);
224 if (buf_size + align_pkt_len > WL1271_AGGR_BUFFER_SIZE)
225 break;
226 buf_size += align_pkt_len;
227 rx_counter++;
228 rx_counter %= wl->num_rx_desc;
229 }
230
231 if (buf_size == 0) {
232 wl1271_warning("received empty data");
233 break;
234 }
235
236
237 des = le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]);
238 ret = wlcore_hw_prepare_read(wl, des, buf_size);
239 if (ret < 0)
240 goto out;
241
242 ret = wlcore_read_data(wl, REG_SLV_MEM_DATA, wl->aggr_buf,
243 buf_size, true);
244 if (ret < 0)
245 goto out;
246
247
248 pkt_offset = 0;
249 while (pkt_offset < buf_size) {
250 des = le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]);
251 pkt_len = wlcore_rx_get_buf_size(wl, des);
252 rx_align = wlcore_hw_get_rx_buf_align(wl, des);
253
254
255
256
257
258
259 if (wl1271_rx_handle_data(wl,
260 wl->aggr_buf + pkt_offset,
261 pkt_len, rx_align,
262 &hlid) == 1) {
263 if (hlid < WL12XX_MAX_LINKS)
264 __set_bit(hlid, active_hlids);
265 else
266 WARN(1,
267 "hlid exceeded WL12XX_MAX_LINKS "
268 "(%d)\n", hlid);
269 }
270
271 wl->rx_counter++;
272 drv_rx_counter++;
273 drv_rx_counter %= wl->num_rx_desc;
274 pkt_offset += wlcore_rx_get_align_buf_size(wl, pkt_len);
275 }
276 }
277
278
279
280
281
282 if (wl->quirks & WLCORE_QUIRK_END_OF_TRANSACTION) {
283 ret = wlcore_write32(wl, WL12XX_REG_RX_DRIVER_COUNTER,
284 wl->rx_counter);
285 if (ret < 0)
286 goto out;
287 }
288
289 wl12xx_rearm_rx_streaming(wl, active_hlids);
290
291out:
292 return ret;
293}
294
295#ifdef CONFIG_PM
296int wl1271_rx_filter_enable(struct wl1271 *wl,
297 int index, bool enable,
298 struct wl12xx_rx_filter *filter)
299{
300 int ret;
301
302 if (wl->rx_filter_enabled[index] == enable) {
303 wl1271_warning("Request to enable an already "
304 "enabled rx filter %d", index);
305 return 0;
306 }
307
308 ret = wl1271_acx_set_rx_filter(wl, index, enable, filter);
309
310 if (ret) {
311 wl1271_error("Failed to %s rx data filter %d (err=%d)",
312 enable ? "enable" : "disable", index, ret);
313 return ret;
314 }
315
316 wl->rx_filter_enabled[index] = enable;
317
318 return 0;
319}
320
321int wl1271_rx_filter_clear_all(struct wl1271 *wl)
322{
323 int i, ret = 0;
324
325 for (i = 0; i < WL1271_MAX_RX_FILTERS; i++) {
326 if (!wl->rx_filter_enabled[i])
327 continue;
328 ret = wl1271_rx_filter_enable(wl, i, 0, NULL);
329 if (ret)
330 goto out;
331 }
332
333out:
334 return ret;
335}
336#endif
337