LXR linux/drivers/scsi/be2iscsi/be

   1/**
   2 * Copyright (C) 2005 - 2011 Emulex
   3 * All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License version 2
   7 * as published by the Free Software Foundation.  The full GNU General
   8 * Public License is included in this distribution in the file called COPYING.
   9 *
  10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11 *
  12 * Contact Information:
  13 * linux-drivers@emulex.com
  14 *
  15 * Emulex
  16 * 3333 Susan Street
  17 * Costa Mesa, CA 92626
  18 */
  19
  20#ifndef _BEISCSI_MAIN_
  21#define _BEISCSI_MAIN_
  22
  23#include <linux/kernel.h>
  24#include <linux/pci.h>
  25#include <linux/if_ether.h>
  26#include <linux/in.h>
  27#include <scsi/scsi.h>
  28#include <scsi/scsi_cmnd.h>
  29#include <scsi/scsi_device.h>
  30#include <scsi/scsi_host.h>
  31#include <scsi/iscsi_proto.h>
  32#include <scsi/libiscsi.h>
  33#include <scsi/scsi_transport_iscsi.h>
  34
  35#include "be.h"
  36#define DRV_NAME                "be2iscsi"
  37#define BUILD_STR               "4.2.162.0"
  38#define BE_NAME                 "Emulex OneConnect" \
  39                                "Open-iSCSI Driver version" BUILD_STR
  40#define DRV_DESC                BE_NAME " " "Driver"
  41
  42#define BE_VENDOR_ID            0x19A2
  43/* DEVICE ID's for BE2 */
  44#define BE_DEVICE_ID1           0x212
  45#define OC_DEVICE_ID1           0x702
  46#define OC_DEVICE_ID2           0x703
  47
  48/* DEVICE ID's for BE3 */
  49#define BE_DEVICE_ID2           0x222
  50#define OC_DEVICE_ID3           0x712
  51
  52#define BE2_IO_DEPTH            1024
  53#define BE2_MAX_SESSIONS        256
  54#define BE2_CMDS_PER_CXN        128
  55#define BE2_TMFS                16
  56#define BE2_NOPOUT_REQ          16
  57#define BE2_SGE                 32
  58#define BE2_DEFPDU_HDR_SZ       64
  59#define BE2_DEFPDU_DATA_SZ      8192
  60
  61#define MAX_CPUS                31
  62#define BEISCSI_SGLIST_ELEMENTS 30
  63
  64#define BEISCSI_CMD_PER_LUN     128     /* scsi_host->cmd_per_lun */
  65#define BEISCSI_MAX_SECTORS     2048    /* scsi_host->max_sectors */
  66
  67#define BEISCSI_MAX_CMD_LEN     16      /* scsi_host->max_cmd_len */
  68#define BEISCSI_NUM_MAX_LUN     256     /* scsi_host->max_lun */
  69#define BEISCSI_NUM_DEVICES_SUPPORTED   0x01
  70#define BEISCSI_MAX_FRAGS_INIT  192
  71#define BE_NUM_MSIX_ENTRIES     1
  72
  73#define MPU_EP_CONTROL          0
  74#define MPU_EP_SEMAPHORE        0xac
  75#define BE2_SOFT_RESET          0x5c
  76#define BE2_PCI_ONLINE0         0xb0
  77#define BE2_PCI_ONLINE1         0xb4
  78#define BE2_SET_RESET           0x80
  79#define BE2_MPU_IRAM_ONLINE     0x00000080
  80
  81#define BE_SENSE_INFO_SIZE              258
  82#define BE_ISCSI_PDU_HEADER_SIZE        64
  83#define BE_MIN_MEM_SIZE                 16384
  84#define MAX_CMD_SZ                      65536
  85#define IIOC_SCSI_DATA                  0x05    /* Write Operation */
  86
  87#define DBG_LVL                         0x00000001
  88#define DBG_LVL_1                       0x00000001
  89#define DBG_LVL_2                       0x00000002
  90#define DBG_LVL_3                       0x00000004
  91#define DBG_LVL_4                       0x00000008
  92#define DBG_LVL_5                       0x00000010
  93#define DBG_LVL_6                       0x00000020
  94#define DBG_LVL_7                       0x00000040
  95#define DBG_LVL_8                       0x00000080
  96
  97#define SE_DEBUG(debug_mask, fmt, args...)              \
  98do {                                                    \
  99        if (debug_mask & DBG_LVL) {                     \
 100                printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
 101                printk(fmt, ##args);                    \
 102        }                                               \
 103} while (0);
 104
 105#define BE_ADAPTER_UP           0x00000000
 106#define BE_ADAPTER_LINK_DOWN    0x00000001
 107/**
 108 * hardware needs the async PDU buffers to be posted in multiples of 8
 109 * So have atleast 8 of them by default
 110 */
 111
 112#define HWI_GET_ASYNC_PDU_CTX(phwi)     (phwi->phwi_ctxt->pasync_ctx)
 113
 114/********* Memory BAR register ************/
 115#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET      0xfc
 116/**
 117 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
 118 * Disable" may still globally block interrupts in addition to individual
 119 * interrupt masks; a mechanism for the device driver to block all interrupts
 120 * atomically without having to arbitrate for the PCI Interrupt Disable bit
 121 * with the OS.
 122 */
 123#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK      (1 << 29)       /* bit 29 */
 124
 125/********* ISR0 Register offset **********/
 126#define CEV_ISR0_OFFSET                         0xC18
 127#define CEV_ISR_SIZE                            4
 128
 129/**
 130 * Macros for reading/writing a protection domain or CSR registers
 131 * in BladeEngine.
 132 */
 133
 134#define DB_TXULP0_OFFSET 0x40
 135#define DB_RXULP0_OFFSET 0xA0
 136/********* Event Q door bell *************/
 137#define DB_EQ_OFFSET                    DB_CQ_OFFSET
 138#define DB_EQ_RING_ID_MASK              0x1FF   /* bits 0 - 8 */
 139/* Clear the interrupt for this eq */
 140#define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
 141/* Must be 1 */
 142#define DB_EQ_EVNT_SHIFT                (10)    /* bit 10 */
 143/* Number of event entries processed */
 144#define DB_EQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 145/* Rearm bit */
 146#define DB_EQ_REARM_SHIFT               (29)    /* bit 29 */
 147
 148/********* Compl Q door bell *************/
 149#define DB_CQ_OFFSET                    0x120
 150#define DB_CQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
 151/* Number of event entries processed */
 152#define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 153/* Rearm bit */
 154#define DB_CQ_REARM_SHIFT               (29)    /* bit 29 */
 155
 156#define GET_HWI_CONTROLLER_WS(pc)       (pc->phwi_ctrlr)
 157#define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
 158                (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
 159#define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
 160                (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
 161
 162#define PAGES_REQUIRED(x) \
 163        ((x < PAGE_SIZE) ? 1 :  ((x + PAGE_SIZE - 1) / PAGE_SIZE))
 164
 165#define BEISCSI_MSI_NAME 20 /* size of msi_name string */
 166
 167enum be_mem_enum {
 168        HWI_MEM_ADDN_CONTEXT,
 169        HWI_MEM_WRB,
 170        HWI_MEM_WRBH,
 171        HWI_MEM_SGLH,
 172        HWI_MEM_SGE,
 173        HWI_MEM_ASYNC_HEADER_BUF,       /* 5 */
 174        HWI_MEM_ASYNC_DATA_BUF,
 175        HWI_MEM_ASYNC_HEADER_RING,
 176        HWI_MEM_ASYNC_DATA_RING,
 177        HWI_MEM_ASYNC_HEADER_HANDLE,
 178        HWI_MEM_ASYNC_DATA_HANDLE,      /* 10 */
 179        HWI_MEM_ASYNC_PDU_CONTEXT,
 180        ISCSI_MEM_GLOBAL_HEADER,
 181        SE_MEM_MAX
 182};
 183
 184struct be_bus_address32 {
 185        unsigned int address_lo;
 186        unsigned int address_hi;
 187};
 188
 189struct be_bus_address64 {
 190        unsigned long long address;
 191};
 192
 193struct be_bus_address {
 194        union {
 195                struct be_bus_address32 a32;
 196                struct be_bus_address64 a64;
 197        } u;
 198};
 199
 200struct mem_array {
 201        struct be_bus_address bus_address;      /* Bus address of location */
 202        void *virtual_address;          /* virtual address to the location */
 203        unsigned int size;              /* Size required by memory block */
 204};
 205
 206struct be_mem_descriptor {
 207        unsigned int index;     /* Index of this memory parameter */
 208        unsigned int category;  /* type indicates cached/non-cached */
 209        unsigned int num_elements;      /* number of elements in this
 210                                         * descriptor
 211                                         */
 212        unsigned int alignment_mask;    /* Alignment mask for this block */
 213        unsigned int size_in_bytes;     /* Size required by memory block */
 214        struct mem_array *mem_array;
 215};
 216
 217struct sgl_handle {
 218        unsigned int sgl_index;
 219        unsigned int type;
 220        unsigned int cid;
 221        struct iscsi_task *task;
 222        struct iscsi_sge *pfrag;
 223};
 224
 225struct hba_parameters {
 226        unsigned int ios_per_ctrl;
 227        unsigned int cxns_per_ctrl;
 228        unsigned int asyncpdus_per_ctrl;
 229        unsigned int icds_per_ctrl;
 230        unsigned int num_sge_per_io;
 231        unsigned int defpdu_hdr_sz;
 232        unsigned int defpdu_data_sz;
 233        unsigned int num_cq_entries;
 234        unsigned int num_eq_entries;
 235        unsigned int wrbs_per_cxn;
 236        unsigned int crashmode;
 237        unsigned int hba_num;
 238
 239        unsigned int mgmt_ws_sz;
 240        unsigned int hwi_ws_sz;
 241
 242        unsigned int eto;
 243        unsigned int ldto;
 244
 245        unsigned int dbg_flags;
 246        unsigned int num_cxn;
 247
 248        unsigned int eq_timer;
 249        /**
 250         * These are calculated from other params. They're here
 251         * for debug purposes
 252         */
 253        unsigned int num_mcc_pages;
 254        unsigned int num_mcc_cq_pages;
 255        unsigned int num_cq_pages;
 256        unsigned int num_eq_pages;
 257
 258        unsigned int num_async_pdu_buf_pages;
 259        unsigned int num_async_pdu_buf_sgl_pages;
 260        unsigned int num_async_pdu_buf_cq_pages;
 261
 262        unsigned int num_async_pdu_hdr_pages;
 263        unsigned int num_async_pdu_hdr_sgl_pages;
 264        unsigned int num_async_pdu_hdr_cq_pages;
 265
 266        unsigned int num_sge;
 267};
 268
 269struct invalidate_command_table {
 270        unsigned short icd;
 271        unsigned short cid;
 272} __packed;
 273
 274struct beiscsi_hba {
 275        struct hba_parameters params;
 276        struct hwi_controller *phwi_ctrlr;
 277        unsigned int mem_req[SE_MEM_MAX];
 278        /* PCI BAR mapped addresses */
 279        u8 __iomem *csr_va;     /* CSR */
 280        u8 __iomem *db_va;      /* Door  Bell  */
 281        u8 __iomem *pci_va;     /* PCI Config */
 282        struct be_bus_address csr_pa;   /* CSR */
 283        struct be_bus_address db_pa;    /* CSR */
 284        struct be_bus_address pci_pa;   /* CSR */
 285        /* PCI representation of our HBA */
 286        struct pci_dev *pcidev;
 287        unsigned int state;
 288        unsigned short asic_revision;
 289        unsigned int num_cpus;
 290        unsigned int nxt_cqid;
 291        struct msix_entry msix_entries[MAX_CPUS + 1];
 292        char *msi_name[MAX_CPUS + 1];
 293        bool msix_enabled;
 294        struct be_mem_descriptor *init_mem;
 295
 296        unsigned short io_sgl_alloc_index;
 297        unsigned short io_sgl_free_index;
 298        unsigned short io_sgl_hndl_avbl;
 299        struct sgl_handle **io_sgl_hndl_base;
 300        struct sgl_handle **sgl_hndl_array;
 301
 302        unsigned short eh_sgl_alloc_index;
 303        unsigned short eh_sgl_free_index;
 304        unsigned short eh_sgl_hndl_avbl;
 305        struct sgl_handle **eh_sgl_hndl_base;
 306        spinlock_t io_sgl_lock;
 307        spinlock_t mgmt_sgl_lock;
 308        spinlock_t isr_lock;
 309        unsigned int age;
 310        unsigned short avlbl_cids;
 311        unsigned short cid_alloc;
 312        unsigned short cid_free;
 313        struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
 314        struct list_head hba_queue;
 315        unsigned short *cid_array;
 316        struct iscsi_endpoint **ep_array;
 317        struct iscsi_boot_kset *boot_kset;
 318        struct Scsi_Host *shost;
 319        struct iscsi_iface *ipv4_iface;
 320        struct iscsi_iface *ipv6_iface;
 321        struct {
 322                /**
 323                 * group together since they are used most frequently
 324                 * for cid to cri conversion
 325                 */
 326                unsigned int iscsi_cid_start;
 327                unsigned int phys_port;
 328
 329                unsigned int isr_offset;
 330                unsigned int iscsi_icd_start;
 331                unsigned int iscsi_cid_count;
 332                unsigned int iscsi_icd_count;
 333                unsigned int pci_function;
 334
 335                unsigned short cid_alloc;
 336                unsigned short cid_free;
 337                unsigned short avlbl_cids;
 338                unsigned short iscsi_features;
 339                spinlock_t cid_lock;
 340        } fw_config;
 341
 342        u8 mac_address[ETH_ALEN];
 343        unsigned short todo_cq;
 344        unsigned short todo_mcc_cq;
 345        char wq_name[20];
 346        struct workqueue_struct *wq;    /* The actuak work queue */
 347        struct work_struct work_cqs;    /* The work being queued */
 348        struct be_ctrl_info ctrl;
 349        unsigned int generation;
 350        unsigned int interface_handle;
 351        struct mgmt_session_info boot_sess;
 352        struct invalidate_command_table inv_tbl[128];
 353
 354};
 355
 356struct beiscsi_session {
 357        struct pci_pool *bhs_pool;
 358};
 359
 360/**
 361 * struct beiscsi_conn - iscsi connection structure
 362 */
 363struct beiscsi_conn {
 364        struct iscsi_conn *conn;
 365        struct beiscsi_hba *phba;
 366        u32 exp_statsn;
 367        u32 beiscsi_conn_cid;
 368        struct beiscsi_endpoint *ep;
 369        unsigned short login_in_progress;
 370        struct wrb_handle *plogin_wrb_handle;
 371        struct sgl_handle *plogin_sgl_handle;
 372        struct beiscsi_session *beiscsi_sess;
 373        struct iscsi_task *task;
 374};
 375
 376/* This structure is used by the chip */
 377struct pdu_data_out {
 378        u32 dw[12];
 379};
 380/**
 381 * Pseudo amap definition in which each bit of the actual structure is defined
 382 * as a byte: used to calculate offset/shift/mask of each field
 383 */
 384struct amap_pdu_data_out {
 385        u8 opcode[6];           /* opcode */
 386        u8 rsvd0[2];            /* should be 0 */
 387        u8 rsvd1[7];
 388        u8 final_bit;           /* F bit */
 389        u8 rsvd2[16];
 390        u8 ahs_length[8];       /* no AHS */
 391        u8 data_len_hi[8];
 392        u8 data_len_lo[16];     /* DataSegmentLength */
 393        u8 lun[64];
 394        u8 itt[32];             /* ITT; initiator task tag */
 395        u8 ttt[32];             /* TTT; valid for R2T or 0xffffffff */
 396        u8 rsvd3[32];
 397        u8 exp_stat_sn[32];
 398        u8 rsvd4[32];
 399        u8 data_sn[32];
 400        u8 buffer_offset[32];
 401        u8 rsvd5[32];
 402};
 403
 404struct be_cmd_bhs {
 405        struct iscsi_scsi_req iscsi_hdr;
 406        unsigned char pad1[16];
 407        struct pdu_data_out iscsi_data_pdu;
 408        unsigned char pad2[BE_SENSE_INFO_SIZE -
 409                        sizeof(struct pdu_data_out)];
 410};
 411
 412struct beiscsi_io_task {
 413        struct wrb_handle *pwrb_handle;
 414        struct sgl_handle *psgl_handle;
 415        struct beiscsi_conn *conn;
 416        struct scsi_cmnd *scsi_cmnd;
 417        unsigned int cmd_sn;
 418        unsigned int flags;
 419        unsigned short cid;
 420        unsigned short header_len;
 421        itt_t libiscsi_itt;
 422        struct be_cmd_bhs *cmd_bhs;
 423        struct be_bus_address bhs_pa;
 424        unsigned short bhs_len;
 425};
 426
 427struct be_nonio_bhs {
 428        struct iscsi_hdr iscsi_hdr;
 429        unsigned char pad1[16];
 430        struct pdu_data_out iscsi_data_pdu;
 431        unsigned char pad2[BE_SENSE_INFO_SIZE -
 432                        sizeof(struct pdu_data_out)];
 433};
 434
 435struct be_status_bhs {
 436        struct iscsi_scsi_req iscsi_hdr;
 437        unsigned char pad1[16];
 438        /**
 439         * The plus 2 below is to hold the sense info length that gets
 440         * DMA'ed by RxULP
 441         */
 442        unsigned char sense_info[BE_SENSE_INFO_SIZE];
 443};
 444
 445struct iscsi_sge {
 446        u32 dw[4];
 447};
 448
 449/**
 450 * Pseudo amap definition in which each bit of the actual structure is defined
 451 * as a byte: used to calculate offset/shift/mask of each field
 452 */
 453struct amap_iscsi_sge {
 454        u8 addr_hi[32];
 455        u8 addr_lo[32];
 456        u8 sge_offset[22];      /* DWORD 2 */
 457        u8 rsvd0[9];            /* DWORD 2 */
 458        u8 last_sge;            /* DWORD 2 */
 459        u8 len[17];             /* DWORD 3 */
 460        u8 rsvd1[15];           /* DWORD 3 */
 461};
 462
 463struct beiscsi_offload_params {
 464        u32 dw[5];
 465};
 466
 467#define OFFLD_PARAMS_ERL        0x00000003
 468#define OFFLD_PARAMS_DDE        0x00000004
 469#define OFFLD_PARAMS_HDE        0x00000008
 470#define OFFLD_PARAMS_IR2T       0x00000010
 471#define OFFLD_PARAMS_IMD        0x00000020
 472
 473/**
 474 * Pseudo amap definition in which each bit of the actual structure is defined
 475 * as a byte: used to calculate offset/shift/mask of each field
 476 */
 477struct amap_beiscsi_offload_params {
 478        u8 max_burst_length[32];
 479        u8 max_send_data_segment_length[32];
 480        u8 first_burst_length[32];
 481        u8 erl[2];
 482        u8 dde[1];
 483        u8 hde[1];
 484        u8 ir2t[1];
 485        u8 imd[1];
 486        u8 pad[26];
 487        u8 exp_statsn[32];
 488};
 489
 490/* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
 491                struct beiscsi_hba *phba, struct sol_cqe *psol);*/
 492
 493struct async_pdu_handle {
 494        struct list_head link;
 495        struct be_bus_address pa;
 496        void *pbuffer;
 497        unsigned int consumed;
 498        unsigned char index;
 499        unsigned char is_header;
 500        unsigned short cri;
 501        unsigned long buffer_len;
 502};
 503
 504struct hwi_async_entry {
 505        struct {
 506                unsigned char hdr_received;
 507                unsigned char hdr_len;
 508                unsigned short bytes_received;
 509                unsigned int bytes_needed;
 510                struct list_head list;
 511        } wait_queue;
 512
 513        struct list_head header_busy_list;
 514        struct list_head data_busy_list;
 515};
 516
 517struct hwi_async_pdu_context {
 518        struct {
 519                struct be_bus_address pa_base;
 520                void *va_base;
 521                void *ring_base;
 522                struct async_pdu_handle *handle_base;
 523
 524                unsigned int host_write_ptr;
 525                unsigned int ep_read_ptr;
 526                unsigned int writables;
 527
 528                unsigned int free_entries;
 529                unsigned int busy_entries;
 530
 531                struct list_head free_list;
 532        } async_header;
 533
 534        struct {
 535                struct be_bus_address pa_base;
 536                void *va_base;
 537                void *ring_base;
 538                struct async_pdu_handle *handle_base;
 539
 540                unsigned int host_write_ptr;
 541                unsigned int ep_read_ptr;
 542                unsigned int writables;
 543
 544                unsigned int free_entries;
 545                unsigned int busy_entries;
 546                struct list_head free_list;
 547        } async_data;
 548
 549        unsigned int buffer_size;
 550        unsigned int num_entries;
 551
 552        /**
 553         * This is a varying size list! Do not add anything
 554         * after this entry!!
 555         */
 556        struct hwi_async_entry async_entry[BE2_MAX_SESSIONS * 2];
 557};
 558
 559#define PDUCQE_CODE_MASK        0x0000003F
 560#define PDUCQE_DPL_MASK         0xFFFF0000
 561#define PDUCQE_INDEX_MASK       0x0000FFFF
 562
 563struct i_t_dpdu_cqe {
 564        u32 dw[4];
 565} __packed;
 566
 567/**
 568 * Pseudo amap definition in which each bit of the actual structure is defined
 569 * as a byte: used to calculate offset/shift/mask of each field
 570 */
 571struct amap_i_t_dpdu_cqe {
 572        u8 db_addr_hi[32];
 573        u8 db_addr_lo[32];
 574        u8 code[6];
 575        u8 cid[10];
 576        u8 dpl[16];
 577        u8 index[16];
 578        u8 num_cons[10];
 579        u8 rsvd0[4];
 580        u8 final;
 581        u8 valid;
 582} __packed;
 583
 584#define CQE_VALID_MASK  0x80000000
 585#define CQE_CODE_MASK   0x0000003F
 586#define CQE_CID_MASK    0x0000FFC0
 587
 588#define EQE_VALID_MASK          0x00000001
 589#define EQE_MAJORCODE_MASK      0x0000000E
 590#define EQE_RESID_MASK          0xFFFF0000
 591
 592struct be_eq_entry {
 593        u32 dw[1];
 594} __packed;
 595
 596/**
 597 * Pseudo amap definition in which each bit of the actual structure is defined
 598 * as a byte: used to calculate offset/shift/mask of each field
 599 */
 600struct amap_eq_entry {
 601        u8 valid;               /* DWORD 0 */
 602        u8 major_code[3];       /* DWORD 0 */
 603        u8 minor_code[12];      /* DWORD 0 */
 604        u8 resource_id[16];     /* DWORD 0 */
 605
 606} __packed;
 607
 608struct cq_db {
 609        u32 dw[1];
 610} __packed;
 611
 612/**
 613 * Pseudo amap definition in which each bit of the actual structure is defined
 614 * as a byte: used to calculate offset/shift/mask of each field
 615 */
 616struct amap_cq_db {
 617        u8 qid[10];
 618        u8 event[1];
 619        u8 rsvd0[5];
 620        u8 num_popped[13];
 621        u8 rearm[1];
 622        u8 rsvd1[2];
 623} __packed;
 624
 625void beiscsi_process_eq(struct beiscsi_hba *phba);
 626
 627struct iscsi_wrb {
 628        u32 dw[16];
 629} __packed;
 630
 631#define WRB_TYPE_MASK 0xF0000000
 632
 633/**
 634 * Pseudo amap definition in which each bit of the actual structure is defined
 635 * as a byte: used to calculate offset/shift/mask of each field
 636 */
 637struct amap_iscsi_wrb {
 638        u8 lun[14];             /* DWORD 0 */
 639        u8 lt;                  /* DWORD 0 */
 640        u8 invld;               /* DWORD 0 */
 641        u8 wrb_idx[8];          /* DWORD 0 */
 642        u8 dsp;                 /* DWORD 0 */
 643        u8 dmsg;                /* DWORD 0 */
 644        u8 undr_run;            /* DWORD 0 */
 645        u8 over_run;            /* DWORD 0 */
 646        u8 type[4];             /* DWORD 0 */
 647        u8 ptr2nextwrb[8];      /* DWORD 1 */
 648        u8 r2t_exp_dtl[24];     /* DWORD 1 */
 649        u8 sgl_icd_idx[12];     /* DWORD 2 */
 650        u8 rsvd0[20];           /* DWORD 2 */
 651        u8 exp_data_sn[32];     /* DWORD 3 */
 652        u8 iscsi_bhs_addr_hi[32];       /* DWORD 4 */
 653        u8 iscsi_bhs_addr_lo[32];       /* DWORD 5 */
 654        u8 cmdsn_itt[32];       /* DWORD 6 */
 655        u8 dif_ref_tag[32];     /* DWORD 7 */
 656        u8 sge0_addr_hi[32];    /* DWORD 8 */
 657        u8 sge0_addr_lo[32];    /* DWORD 9  */
 658        u8 sge0_offset[22];     /* DWORD 10 */
 659        u8 pbs;                 /* DWORD 10 */
 660        u8 dif_mode[2];         /* DWORD 10 */
 661        u8 rsvd1[6];            /* DWORD 10 */
 662        u8 sge0_last;           /* DWORD 10 */
 663        u8 sge0_len[17];        /* DWORD 11 */
 664        u8 dif_meta_tag[14];    /* DWORD 11 */
 665        u8 sge0_in_ddr;         /* DWORD 11 */
 666        u8 sge1_addr_hi[32];    /* DWORD 12 */
 667        u8 sge1_addr_lo[32];    /* DWORD 13 */
 668        u8 sge1_r2t_offset[22]; /* DWORD 14 */
 669        u8 rsvd2[9];            /* DWORD 14 */
 670        u8 sge1_last;           /* DWORD 14 */
 671        u8 sge1_len[17];        /* DWORD 15 */
 672        u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
 673        u8 rsvd3[2];            /* DWORD 15 */
 674        u8 sge1_in_ddr;         /* DWORD 15 */
 675
 676} __packed;
 677
 678struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
 679void
 680free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
 681
 682void beiscsi_process_all_cqs(struct work_struct *work);
 683
 684struct pdu_nop_out {
 685        u32 dw[12];
 686};
 687
 688/**
 689 * Pseudo amap definition in which each bit of the actual structure is defined
 690 * as a byte: used to calculate offset/shift/mask of each field
 691 */
 692struct amap_pdu_nop_out {
 693        u8 opcode[6];           /* opcode 0x00 */
 694        u8 i_bit;               /* I Bit */
 695        u8 x_bit;               /* reserved; should be 0 */
 696        u8 fp_bit_filler1[7];
 697        u8 f_bit;               /* always 1 */
 698        u8 reserved1[16];
 699        u8 ahs_length[8];       /* no AHS */
 700        u8 data_len_hi[8];
 701        u8 data_len_lo[16];     /* DataSegmentLength */
 702        u8 lun[64];
 703        u8 itt[32];             /* initiator id for ping or 0xffffffff */
 704        u8 ttt[32];             /* target id for ping or 0xffffffff */
 705        u8 cmd_sn[32];
 706        u8 exp_stat_sn[32];
 707        u8 reserved5[128];
 708};
 709
 710#define PDUBASE_OPCODE_MASK     0x0000003F
 711#define PDUBASE_DATALENHI_MASK  0x0000FF00
 712#define PDUBASE_DATALENLO_MASK  0xFFFF0000
 713
 714struct pdu_base {
 715        u32 dw[16];
 716} __packed;
 717
 718/**
 719 * Pseudo amap definition in which each bit of the actual structure is defined
 720 * as a byte: used to calculate offset/shift/mask of each field
 721 */
 722struct amap_pdu_base {
 723        u8 opcode[6];
 724        u8 i_bit;               /* immediate bit */
 725        u8 x_bit;               /* reserved, always 0 */
 726        u8 reserved1[24];       /* opcode-specific fields */
 727        u8 ahs_length[8];       /* length units is 4 byte words */
 728        u8 data_len_hi[8];
 729        u8 data_len_lo[16];     /* DatasegmentLength */
 730        u8 lun[64];             /* lun or opcode-specific fields */
 731        u8 itt[32];             /* initiator task tag */
 732        u8 reserved4[224];
 733};
 734
 735struct iscsi_target_context_update_wrb {
 736        u32 dw[16];
 737} __packed;
 738
 739/**
 740 * Pseudo amap definition in which each bit of the actual structure is defined
 741 * as a byte: used to calculate offset/shift/mask of each field
 742 */
 743struct amap_iscsi_target_context_update_wrb {
 744        u8 lun[14];             /* DWORD 0 */
 745        u8 lt;                  /* DWORD 0 */
 746        u8 invld;               /* DWORD 0 */
 747        u8 wrb_idx[8];          /* DWORD 0 */
 748        u8 dsp;                 /* DWORD 0 */
 749        u8 dmsg;                /* DWORD 0 */
 750        u8 undr_run;            /* DWORD 0 */
 751        u8 over_run;            /* DWORD 0 */
 752        u8 type[4];             /* DWORD 0 */
 753        u8 ptr2nextwrb[8];      /* DWORD 1 */
 754        u8 max_burst_length[19];        /* DWORD 1 */
 755        u8 rsvd0[5];            /* DWORD 1 */
 756        u8 rsvd1[15];           /* DWORD 2 */
 757        u8 max_send_data_segment_length[17];    /* DWORD 2 */
 758        u8 first_burst_length[14];      /* DWORD 3 */
 759        u8 rsvd2[2];            /* DWORD 3 */
 760        u8 tx_wrbindex_drv_msg[8];      /* DWORD 3 */
 761        u8 rsvd3[5];            /* DWORD 3 */
 762        u8 session_state[3];    /* DWORD 3 */
 763        u8 rsvd4[16];           /* DWORD 4 */
 764        u8 tx_jumbo;            /* DWORD 4 */
 765        u8 hde;                 /* DWORD 4 */
 766        u8 dde;                 /* DWORD 4 */
 767        u8 erl[2];              /* DWORD 4 */
 768        u8 domain_id[5];                /* DWORD 4 */
 769        u8 mode;                /* DWORD 4 */
 770        u8 imd;                 /* DWORD 4 */
 771        u8 ir2t;                /* DWORD 4 */
 772        u8 notpredblq[2];       /* DWORD 4 */
 773        u8 compltonack;         /* DWORD 4 */
 774        u8 stat_sn[32];         /* DWORD 5 */
 775        u8 pad_buffer_addr_hi[32];      /* DWORD 6 */
 776        u8 pad_buffer_addr_lo[32];      /* DWORD 7 */
 777        u8 pad_addr_hi[32];     /* DWORD 8 */
 778        u8 pad_addr_lo[32];     /* DWORD 9 */
 779        u8 rsvd5[32];           /* DWORD 10 */
 780        u8 rsvd6[32];           /* DWORD 11 */
 781        u8 rsvd7[32];           /* DWORD 12 */
 782        u8 rsvd8[32];           /* DWORD 13 */
 783        u8 rsvd9[32];           /* DWORD 14 */
 784        u8 rsvd10[32];          /* DWORD 15 */
 785
 786} __packed;
 787
 788struct be_ring {
 789        u32 pages;              /* queue size in pages */
 790        u32 id;                 /* queue id assigned by beklib */
 791        u32 num;                /* number of elements in queue */
 792        u32 cidx;               /* consumer index */
 793        u32 pidx;               /* producer index -- not used by most rings */
 794        u32 item_size;          /* size in bytes of one object */
 795
 796        void *va;               /* The virtual address of the ring.  This
 797                                 * should be last to allow 32 & 64 bit debugger
 798                                 * extensions to work.
 799                                 */
 800};
 801
 802struct hwi_wrb_context {
 803        struct list_head wrb_handle_list;
 804        struct list_head wrb_handle_drvr_list;
 805        struct wrb_handle **pwrb_handle_base;
 806        struct wrb_handle **pwrb_handle_basestd;
 807        struct iscsi_wrb *plast_wrb;
 808        unsigned short alloc_index;
 809        unsigned short free_index;
 810        unsigned short wrb_handles_available;
 811        unsigned short cid;
 812};
 813
 814struct hwi_controller {
 815        struct list_head io_sgl_list;
 816        struct list_head eh_sgl_list;
 817        struct sgl_handle *psgl_handle_base;
 818        unsigned int wrb_mem_index;
 819
 820        struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
 821        struct mcc_wrb *pmcc_wrb_base;
 822        struct be_ring default_pdu_hdr;
 823        struct be_ring default_pdu_data;
 824        struct hwi_context_memory *phwi_ctxt;
 825};
 826
 827enum hwh_type_enum {
 828        HWH_TYPE_IO = 1,
 829        HWH_TYPE_LOGOUT = 2,
 830        HWH_TYPE_TMF = 3,
 831        HWH_TYPE_NOP = 4,
 832        HWH_TYPE_IO_RD = 5,
 833        HWH_TYPE_LOGIN = 11,
 834        HWH_TYPE_INVALID = 0xFFFFFFFF
 835};
 836
 837struct wrb_handle {
 838        enum hwh_type_enum type;
 839        unsigned short wrb_index;
 840        unsigned short nxt_wrb_index;
 841
 842        struct iscsi_task *pio_handle;
 843        struct iscsi_wrb *pwrb;
 844};
 845
 846struct hwi_context_memory {
 847        /* Adaptive interrupt coalescing (AIC) info */
 848        u16 min_eqd;            /* in usecs */
 849        u16 max_eqd;            /* in usecs */
 850        u16 cur_eqd;            /* in usecs */
 851        struct be_eq_obj be_eq[MAX_CPUS];
 852        struct be_queue_info be_cq[MAX_CPUS];
 853
 854        struct be_queue_info be_def_hdrq;
 855        struct be_queue_info be_def_dataq;
 856
 857        struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
 858        struct be_mcc_wrb_context *pbe_mcc_context;
 859
 860        struct hwi_async_pdu_context *pasync_ctx;
 861};
 862
 863#endif
 864