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18#ifndef __BFA_DEFS_H__
19#define __BFA_DEFS_H__
20
21#include "bfa_fc.h"
22#include "bfad_drv.h"
23
24#define BFA_MFG_SERIALNUM_SIZE 11
25#define STRSZ(_n) (((_n) + 4) & ~3)
26
27
28
29
30enum {
31 BFA_MFG_TYPE_CB_MAX = 825,
32 BFA_MFG_TYPE_FC8P2 = 825,
33 BFA_MFG_TYPE_FC8P1 = 815,
34 BFA_MFG_TYPE_FC4P2 = 425,
35 BFA_MFG_TYPE_FC4P1 = 415,
36 BFA_MFG_TYPE_CNA10P2 = 1020,
37 BFA_MFG_TYPE_CNA10P1 = 1010,
38 BFA_MFG_TYPE_JAYHAWK = 804,
39 BFA_MFG_TYPE_WANCHESE = 1007,
40 BFA_MFG_TYPE_ASTRA = 807,
41 BFA_MFG_TYPE_LIGHTNING_P0 = 902,
42 BFA_MFG_TYPE_LIGHTNING = 1741,
43 BFA_MFG_TYPE_PROWLER_F = 1560,
44 BFA_MFG_TYPE_PROWLER_N = 1410,
45 BFA_MFG_TYPE_PROWLER_C = 1710,
46 BFA_MFG_TYPE_PROWLER_D = 1860,
47 BFA_MFG_TYPE_CHINOOK = 1867,
48 BFA_MFG_TYPE_INVALID = 0,
49};
50
51#pragma pack(1)
52
53
54
55
56#define bfa_mfg_is_mezz(type) (( \
57 (type) == BFA_MFG_TYPE_JAYHAWK || \
58 (type) == BFA_MFG_TYPE_WANCHESE || \
59 (type) == BFA_MFG_TYPE_ASTRA || \
60 (type) == BFA_MFG_TYPE_LIGHTNING_P0 || \
61 (type) == BFA_MFG_TYPE_LIGHTNING || \
62 (type) == BFA_MFG_TYPE_CHINOOK))
63
64
65
66
67#define bfa_mfg_is_old_wwn_mac_model(type) (( \
68 (type) == BFA_MFG_TYPE_FC8P2 || \
69 (type) == BFA_MFG_TYPE_FC8P1 || \
70 (type) == BFA_MFG_TYPE_FC4P2 || \
71 (type) == BFA_MFG_TYPE_FC4P1 || \
72 (type) == BFA_MFG_TYPE_CNA10P2 || \
73 (type) == BFA_MFG_TYPE_CNA10P1 || \
74 (type) == BFA_MFG_TYPE_JAYHAWK || \
75 (type) == BFA_MFG_TYPE_WANCHESE))
76
77#define bfa_mfg_increment_wwn_mac(m, i) \
78do { \
79 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \
80 (u32)(m)[2]; \
81 t += (i); \
82 (m)[0] = (t >> 16) & 0xFF; \
83 (m)[1] = (t >> 8) & 0xFF; \
84 (m)[2] = t & 0xFF; \
85} while (0)
86
87
88
89
90#define BFA_MFG_VPD_LEN 512
91
92
93
94
95enum {
96 BFA_MFG_VPD_UNKNOWN = 0,
97 BFA_MFG_VPD_IBM = 1,
98 BFA_MFG_VPD_HP = 2,
99 BFA_MFG_VPD_DELL = 3,
100 BFA_MFG_VPD_PCI_IBM = 0x08,
101 BFA_MFG_VPD_PCI_HP = 0x10,
102 BFA_MFG_VPD_PCI_DELL = 0x20,
103 BFA_MFG_VPD_PCI_BRCD = 0xf8,
104};
105
106
107
108
109struct bfa_mfg_vpd_s {
110 u8 version;
111 u8 vpd_sig[3];
112 u8 chksum;
113 u8 vendor;
114 u8 len;
115 u8 rsv;
116 u8 data[BFA_MFG_VPD_LEN];
117};
118
119#pragma pack()
120
121
122
123
124enum bfa_status {
125 BFA_STATUS_OK = 0,
126 BFA_STATUS_FAILED = 1,
127 BFA_STATUS_EINVAL = 2,
128
129 BFA_STATUS_ENOMEM = 3,
130 BFA_STATUS_ETIMER = 5,
131
132 BFA_STATUS_EPROTOCOL = 6,
133 BFA_STATUS_SFP_UNSUPP = 10,
134 BFA_STATUS_UNKNOWN_VFID = 11,
135 BFA_STATUS_DATACORRUPTED = 12,
136 BFA_STATUS_DEVBUSY = 13,
137 BFA_STATUS_HDMA_FAILED = 16,
138 BFA_STATUS_FLASH_BAD_LEN = 17,
139 BFA_STATUS_UNKNOWN_LWWN = 18,
140 BFA_STATUS_UNKNOWN_RWWN = 19,
141 BFA_STATUS_VPORT_EXISTS = 21,
142 BFA_STATUS_VPORT_MAX = 22,
143 BFA_STATUS_UNSUPP_SPEED = 23,
144 BFA_STATUS_INVLD_DFSZ = 24,
145 BFA_STATUS_CMD_NOTSUPP = 26,
146 BFA_STATUS_FABRIC_RJT = 29,
147 BFA_STATUS_UNKNOWN_VWWN = 30,
148 BFA_STATUS_PORT_OFFLINE = 34,
149 BFA_STATUS_VPORT_WWN_BP = 46,
150 BFA_STATUS_PORT_NOT_DISABLED = 47,
151 BFA_STATUS_NO_FCPIM_NEXUS = 52,
152 BFA_STATUS_IOC_FAILURE = 56,
153
154 BFA_STATUS_INVALID_WWN = 57,
155 BFA_STATUS_ADAPTER_ENABLED = 60,
156 BFA_STATUS_IOC_NON_OP = 61,
157 BFA_STATUS_VERSION_FAIL = 70,
158 BFA_STATUS_DIAG_BUSY = 71,
159 BFA_STATUS_BEACON_ON = 72,
160 BFA_STATUS_ENOFSAVE = 78,
161 BFA_STATUS_IOC_DISABLED = 82,
162 BFA_STATUS_NO_SFP_DEV = 89,
163 BFA_STATUS_MEMTEST_FAILED = 90,
164 BFA_STATUS_LEDTEST_OP = 109,
165 BFA_STATUS_INVALID_MAC = 134,
166 BFA_STATUS_PBC = 154,
167
168 BFA_STATUS_BAD_FWCFG = 156,
169 BFA_STATUS_INVALID_VENDOR = 158,
170 BFA_STATUS_SFP_NOT_READY = 159,
171 BFA_STATUS_TRUNK_ENABLED = 164,
172
173 BFA_STATUS_TRUNK_DISABLED = 165,
174
175 BFA_STATUS_IOPROFILE_OFF = 175,
176 BFA_STATUS_PHY_NOT_PRESENT = 183,
177 BFA_STATUS_FEATURE_NOT_SUPPORTED = 192,
178 BFA_STATUS_ENTRY_EXISTS = 193,
179 BFA_STATUS_ENTRY_NOT_EXISTS = 194,
180 BFA_STATUS_NO_CHANGE = 195,
181 BFA_STATUS_FAA_ENABLED = 197,
182 BFA_STATUS_FAA_DISABLED = 198,
183 BFA_STATUS_FAA_ACQUIRED = 199,
184 BFA_STATUS_FAA_ACQ_ADDR = 200,
185 BFA_STATUS_ERROR_TRUNK_ENABLED = 203,
186 BFA_STATUS_MAX_ENTRY_REACHED = 212,
187 BFA_STATUS_MAX_VAL
188};
189#define bfa_status_t enum bfa_status
190
191enum bfa_eproto_status {
192 BFA_EPROTO_BAD_ACCEPT = 0,
193 BFA_EPROTO_UNKNOWN_RSP = 1
194};
195#define bfa_eproto_status_t enum bfa_eproto_status
196
197enum bfa_boolean {
198 BFA_FALSE = 0,
199 BFA_TRUE = 1
200};
201#define bfa_boolean_t enum bfa_boolean
202
203#define BFA_STRING_32 32
204#define BFA_VERSION_LEN 64
205
206
207
208
209
210
211
212
213enum {
214 BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE),
215
216
217
218 BFA_ADAPTER_MODEL_NAME_LEN = 16,
219 BFA_ADAPTER_MODEL_DESCR_LEN = 128,
220 BFA_ADAPTER_MFG_NAME_LEN = 8,
221 BFA_ADAPTER_SYM_NAME_LEN = 64,
222 BFA_ADAPTER_OS_TYPE_LEN = 64,
223};
224
225struct bfa_adapter_attr_s {
226 char manufacturer[BFA_ADAPTER_MFG_NAME_LEN];
227 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
228 u32 card_type;
229 char model[BFA_ADAPTER_MODEL_NAME_LEN];
230 char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN];
231 wwn_t pwwn;
232 char node_symname[FC_SYMNAME_MAX];
233 char hw_ver[BFA_VERSION_LEN];
234 char fw_ver[BFA_VERSION_LEN];
235 char optrom_ver[BFA_VERSION_LEN];
236 char os_type[BFA_ADAPTER_OS_TYPE_LEN];
237 struct bfa_mfg_vpd_s vpd;
238 struct mac_s mac;
239
240 u8 nports;
241 u8 max_speed;
242 u8 prototype;
243 char asic_rev;
244
245 u8 pcie_gen;
246 u8 pcie_lanes_orig;
247 u8 pcie_lanes;
248 u8 cna_capable;
249
250 u8 is_mezz;
251 u8 trunk_capable;
252};
253
254
255
256
257
258enum {
259 BFA_IOC_DRIVER_LEN = 16,
260 BFA_IOC_CHIP_REV_LEN = 8,
261};
262
263
264
265
266struct bfa_ioc_driver_attr_s {
267 char driver[BFA_IOC_DRIVER_LEN];
268 char driver_ver[BFA_VERSION_LEN];
269 char fw_ver[BFA_VERSION_LEN];
270 char bios_ver[BFA_VERSION_LEN];
271 char efi_ver[BFA_VERSION_LEN];
272 char ob_ver[BFA_VERSION_LEN];
273};
274
275
276
277
278struct bfa_ioc_pci_attr_s {
279 u16 vendor_id;
280 u16 device_id;
281 u16 ssid;
282 u16 ssvid;
283 u32 pcifn;
284 u32 rsvd;
285 char chip_rev[BFA_IOC_CHIP_REV_LEN];
286};
287
288
289
290
291enum bfa_ioc_state {
292 BFA_IOC_UNINIT = 1,
293 BFA_IOC_RESET = 2,
294 BFA_IOC_SEMWAIT = 3,
295 BFA_IOC_HWINIT = 4,
296 BFA_IOC_GETATTR = 5,
297 BFA_IOC_OPERATIONAL = 6,
298 BFA_IOC_INITFAIL = 7,
299 BFA_IOC_FAIL = 8,
300 BFA_IOC_DISABLING = 9,
301 BFA_IOC_DISABLED = 10,
302 BFA_IOC_FWMISMATCH = 11,
303 BFA_IOC_ENABLING = 12,
304 BFA_IOC_HWFAIL = 13,
305 BFA_IOC_ACQ_ADDR = 14,
306};
307
308
309
310
311struct bfa_fw_ioc_stats_s {
312 u32 enable_reqs;
313 u32 disable_reqs;
314 u32 get_attr_reqs;
315 u32 dbg_sync;
316 u32 dbg_dump;
317 u32 unknown_reqs;
318};
319
320
321
322
323struct bfa_ioc_drv_stats_s {
324 u32 ioc_isrs;
325 u32 ioc_enables;
326 u32 ioc_disables;
327 u32 ioc_hbfails;
328 u32 ioc_boots;
329 u32 stats_tmos;
330 u32 hb_count;
331 u32 disable_reqs;
332 u32 enable_reqs;
333 u32 disable_replies;
334 u32 enable_replies;
335 u32 rsvd;
336};
337
338
339
340
341struct bfa_ioc_stats_s {
342 struct bfa_ioc_drv_stats_s drv_stats;
343 struct bfa_fw_ioc_stats_s fw_stats;
344};
345
346enum bfa_ioc_type_e {
347 BFA_IOC_TYPE_FC = 1,
348 BFA_IOC_TYPE_FCoE = 2,
349 BFA_IOC_TYPE_LL = 3,
350};
351
352
353
354
355struct bfa_ioc_attr_s {
356 enum bfa_ioc_type_e ioc_type;
357 enum bfa_ioc_state state;
358 struct bfa_adapter_attr_s adapter_attr;
359 struct bfa_ioc_driver_attr_s driver_attr;
360 struct bfa_ioc_pci_attr_s pci_attr;
361 u8 port_id;
362 u8 port_mode;
363 u8 cap_bm;
364 u8 port_mode_cfg;
365 u8 rsvd[4];
366};
367
368
369
370
371enum bfa_aen_category {
372 BFA_AEN_CAT_ADAPTER = 1,
373 BFA_AEN_CAT_PORT = 2,
374 BFA_AEN_CAT_LPORT = 3,
375 BFA_AEN_CAT_RPORT = 4,
376 BFA_AEN_CAT_ITNIM = 5,
377 BFA_AEN_CAT_AUDIT = 8,
378 BFA_AEN_CAT_IOC = 9,
379};
380
381
382enum bfa_adapter_aen_event {
383 BFA_ADAPTER_AEN_ADD = 1,
384 BFA_ADAPTER_AEN_REMOVE = 2,
385};
386
387struct bfa_adapter_aen_data_s {
388 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
389 u32 nports;
390 wwn_t pwwn;
391};
392
393
394enum bfa_port_aen_event {
395 BFA_PORT_AEN_ONLINE = 1,
396 BFA_PORT_AEN_OFFLINE = 2,
397 BFA_PORT_AEN_RLIR = 3,
398 BFA_PORT_AEN_SFP_INSERT = 4,
399 BFA_PORT_AEN_SFP_REMOVE = 5,
400 BFA_PORT_AEN_SFP_POM = 6,
401 BFA_PORT_AEN_ENABLE = 7,
402 BFA_PORT_AEN_DISABLE = 8,
403 BFA_PORT_AEN_AUTH_ON = 9,
404 BFA_PORT_AEN_AUTH_OFF = 10,
405 BFA_PORT_AEN_DISCONNECT = 11,
406 BFA_PORT_AEN_QOS_NEG = 12,
407 BFA_PORT_AEN_FABRIC_NAME_CHANGE = 13,
408 BFA_PORT_AEN_SFP_ACCESS_ERROR = 14,
409 BFA_PORT_AEN_SFP_UNSUPPORT = 15,
410};
411
412enum bfa_port_aen_sfp_pom {
413 BFA_PORT_AEN_SFP_POM_GREEN = 1,
414 BFA_PORT_AEN_SFP_POM_AMBER = 2,
415 BFA_PORT_AEN_SFP_POM_RED = 3,
416 BFA_PORT_AEN_SFP_POM_MAX = BFA_PORT_AEN_SFP_POM_RED
417};
418
419struct bfa_port_aen_data_s {
420 wwn_t pwwn;
421 wwn_t fwwn;
422 u32 phy_port_num;
423 u16 ioc_type;
424 u16 level;
425 mac_t mac;
426 u16 rsvd;
427};
428
429
430enum bfa_lport_aen_event {
431 BFA_LPORT_AEN_NEW = 1,
432 BFA_LPORT_AEN_DELETE = 2,
433 BFA_LPORT_AEN_ONLINE = 3,
434 BFA_LPORT_AEN_OFFLINE = 4,
435 BFA_LPORT_AEN_DISCONNECT = 5,
436 BFA_LPORT_AEN_NEW_PROP = 6,
437 BFA_LPORT_AEN_DELETE_PROP = 7,
438 BFA_LPORT_AEN_NEW_STANDARD = 8,
439 BFA_LPORT_AEN_DELETE_STANDARD = 9,
440 BFA_LPORT_AEN_NPIV_DUP_WWN = 10,
441 BFA_LPORT_AEN_NPIV_FABRIC_MAX = 11,
442 BFA_LPORT_AEN_NPIV_UNKNOWN = 12,
443};
444
445struct bfa_lport_aen_data_s {
446 u16 vf_id;
447 u16 roles;
448 u32 rsvd;
449 wwn_t ppwwn;
450 wwn_t lpwwn;
451};
452
453
454enum bfa_itnim_aen_event {
455 BFA_ITNIM_AEN_ONLINE = 1,
456 BFA_ITNIM_AEN_OFFLINE = 2,
457 BFA_ITNIM_AEN_DISCONNECT = 3,
458};
459
460struct bfa_itnim_aen_data_s {
461 u16 vf_id;
462 u16 rsvd[3];
463 wwn_t ppwwn;
464 wwn_t lpwwn;
465 wwn_t rpwwn;
466};
467
468
469enum bfa_audit_aen_event {
470 BFA_AUDIT_AEN_AUTH_ENABLE = 1,
471 BFA_AUDIT_AEN_AUTH_DISABLE = 2,
472 BFA_AUDIT_AEN_FLASH_ERASE = 3,
473 BFA_AUDIT_AEN_FLASH_UPDATE = 4,
474};
475
476struct bfa_audit_aen_data_s {
477 wwn_t pwwn;
478 int partition_inst;
479 int partition_type;
480};
481
482
483enum bfa_ioc_aen_event {
484 BFA_IOC_AEN_HBGOOD = 1,
485 BFA_IOC_AEN_HBFAIL = 2,
486 BFA_IOC_AEN_ENABLE = 3,
487 BFA_IOC_AEN_DISABLE = 4,
488 BFA_IOC_AEN_FWMISMATCH = 5,
489 BFA_IOC_AEN_FWCFG_ERROR = 6,
490 BFA_IOC_AEN_INVALID_VENDOR = 7,
491 BFA_IOC_AEN_INVALID_NWWN = 8,
492 BFA_IOC_AEN_INVALID_PWWN = 9
493};
494
495struct bfa_ioc_aen_data_s {
496 wwn_t pwwn;
497 u16 ioc_type;
498 mac_t mac;
499};
500
501
502
503
504
505
506
507
508#define BFA_MFG_CHKSUM_SIZE 16
509
510#define BFA_MFG_PARTNUM_SIZE 14
511#define BFA_MFG_SUPPLIER_ID_SIZE 10
512#define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20
513#define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20
514#define BFA_MFG_SUPPLIER_REVISION_SIZE 4
515
516
517
518#define BFA_MFG_IC_FC 0x01
519#define BFA_MFG_IC_ETH 0x02
520
521
522
523
524#define BFA_CM_HBA 0x01
525#define BFA_CM_CNA 0x02
526#define BFA_CM_NIC 0x04
527#define BFA_CM_FC16G 0x08
528#define BFA_CM_SRIOV 0x10
529#define BFA_CM_MEZZ 0x20
530
531#pragma pack(1)
532
533
534
535
536struct bfa_mfg_block_s {
537 u8 version;
538 u8 mfg_sig[3];
539 u16 mfgsize;
540 u16 u16_chksum;
541 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
542 char brcd_partnum[STRSZ(BFA_MFG_PARTNUM_SIZE)];
543 u8 mfg_day;
544 u8 mfg_month;
545 u16 mfg_year;
546 wwn_t mfg_wwn;
547 u8 num_wwn;
548 u8 mfg_speeds;
549 u8 rsv[2];
550 char supplier_id[STRSZ(BFA_MFG_SUPPLIER_ID_SIZE)];
551 char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)];
552 char supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)];
553 char supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)];
554 mac_t mfg_mac;
555 u8 num_mac;
556 u8 rsv2;
557 u32 card_type;
558 char cap_nic;
559 char cap_cna;
560 char cap_hba;
561 char cap_fc16g;
562 char cap_sriov;
563 char cap_mezz;
564 u8 rsv3;
565 u8 mfg_nports;
566 char media[8];
567 char initial_mode[8];
568 u8 rsv4[84];
569 u8 md5_chksum[BFA_MFG_CHKSUM_SIZE];
570};
571
572#pragma pack()
573
574
575
576
577
578
579
580
581enum {
582 BFA_PCI_VENDOR_ID_BROCADE = 0x1657,
583 BFA_PCI_DEVICE_ID_FC_8G2P = 0x13,
584 BFA_PCI_DEVICE_ID_FC_8G1P = 0x17,
585 BFA_PCI_DEVICE_ID_CT = 0x14,
586 BFA_PCI_DEVICE_ID_CT_FC = 0x21,
587 BFA_PCI_DEVICE_ID_CT2 = 0x22,
588};
589
590#define bfa_asic_id_cb(__d) \
591 ((__d) == BFA_PCI_DEVICE_ID_FC_8G2P || \
592 (__d) == BFA_PCI_DEVICE_ID_FC_8G1P)
593#define bfa_asic_id_ct(__d) \
594 ((__d) == BFA_PCI_DEVICE_ID_CT || \
595 (__d) == BFA_PCI_DEVICE_ID_CT_FC)
596#define bfa_asic_id_ct2(__d) ((__d) == BFA_PCI_DEVICE_ID_CT2)
597#define bfa_asic_id_ctc(__d) \
598 (bfa_asic_id_ct(__d) || bfa_asic_id_ct2(__d))
599
600
601
602
603enum {
604 BFA_PCI_FCOE_SSDEVICE_ID = 0x14,
605 BFA_PCI_CT2_SSID_FCoE = 0x22,
606 BFA_PCI_CT2_SSID_ETH = 0x23,
607 BFA_PCI_CT2_SSID_FC = 0x24,
608};
609
610
611
612
613#define BFA_PCI_ACCESS_RANGES 1
614
615
616
617
618
619enum bfa_port_speed {
620 BFA_PORT_SPEED_UNKNOWN = 0,
621 BFA_PORT_SPEED_1GBPS = 1,
622 BFA_PORT_SPEED_2GBPS = 2,
623 BFA_PORT_SPEED_4GBPS = 4,
624 BFA_PORT_SPEED_8GBPS = 8,
625 BFA_PORT_SPEED_10GBPS = 10,
626 BFA_PORT_SPEED_16GBPS = 16,
627 BFA_PORT_SPEED_AUTO = 0xf,
628};
629#define bfa_port_speed_t enum bfa_port_speed
630
631enum {
632 BFA_BOOT_BOOTLUN_MAX = 4,
633 BFA_PREBOOT_BOOTLUN_MAX = 8,
634};
635
636#define BOOT_CFG_REV1 1
637#define BOOT_CFG_VLAN 1
638
639
640
641
642
643enum bfa_boot_bootopt {
644 BFA_BOOT_AUTO_DISCOVER = 0,
645 BFA_BOOT_STORED_BLUN = 1,
646 BFA_BOOT_FIRST_LUN = 2,
647 BFA_BOOT_PBC = 3,
648};
649
650#pragma pack(1)
651
652
653
654struct bfa_boot_bootlun_s {
655 wwn_t pwwn;
656 struct scsi_lun lun;
657};
658#pragma pack()
659
660
661
662
663struct bfa_boot_cfg_s {
664 u8 version;
665 u8 rsvd1;
666 u16 chksum;
667 u8 enable;
668 u8 speed;
669 u8 topology;
670 u8 bootopt;
671 u32 nbluns;
672 u32 rsvd2;
673 struct bfa_boot_bootlun_s blun[BFA_BOOT_BOOTLUN_MAX];
674 struct bfa_boot_bootlun_s blun_disc[BFA_BOOT_BOOTLUN_MAX];
675};
676
677struct bfa_boot_pbc_s {
678 u8 enable;
679 u8 speed;
680 u8 topology;
681 u8 rsvd1;
682 u32 nbluns;
683 struct bfa_boot_bootlun_s pblun[BFA_PREBOOT_BOOTLUN_MAX];
684};
685
686struct bfa_ethboot_cfg_s {
687 u8 version;
688 u8 rsvd1;
689 u16 chksum;
690 u8 enable;
691 u8 rsvd2;
692 u16 vlan;
693};
694
695
696
697
698#define BFA_ABLK_MAX_PORTS 2
699#define BFA_ABLK_MAX_PFS 16
700#define BFA_ABLK_MAX 2
701
702#pragma pack(1)
703enum bfa_mode_s {
704 BFA_MODE_HBA = 1,
705 BFA_MODE_CNA = 2,
706 BFA_MODE_NIC = 3
707};
708
709struct bfa_adapter_cfg_mode_s {
710 u16 max_pf;
711 u16 max_vf;
712 enum bfa_mode_s mode;
713};
714
715struct bfa_ablk_cfg_pf_s {
716 u16 pers;
717 u8 port_id;
718 u8 optrom;
719 u8 valid;
720 u8 sriov;
721 u8 max_vfs;
722 u8 rsvd[1];
723 u16 num_qpairs;
724 u16 num_vectors;
725 u32 bw;
726};
727
728struct bfa_ablk_cfg_port_s {
729 u8 mode;
730 u8 type;
731 u8 max_pfs;
732 u8 rsvd[5];
733};
734
735struct bfa_ablk_cfg_inst_s {
736 u8 nports;
737 u8 max_pfs;
738 u8 rsvd[6];
739 struct bfa_ablk_cfg_pf_s pf_cfg[BFA_ABLK_MAX_PFS];
740 struct bfa_ablk_cfg_port_s port_cfg[BFA_ABLK_MAX_PORTS];
741};
742
743struct bfa_ablk_cfg_s {
744 struct bfa_ablk_cfg_inst_s inst[BFA_ABLK_MAX];
745};
746
747
748
749
750
751#define SFP_DIAGMON_SIZE 10
752
753
754#define BFA_SFP_SCN_REMOVED 0
755#define BFA_SFP_SCN_INSERTED 1
756#define BFA_SFP_SCN_POM 2
757#define BFA_SFP_SCN_FAILED 3
758#define BFA_SFP_SCN_UNSUPPORT 4
759#define BFA_SFP_SCN_VALID 5
760
761enum bfa_defs_sfp_media_e {
762 BFA_SFP_MEDIA_UNKNOWN = 0x00,
763 BFA_SFP_MEDIA_CU = 0x01,
764 BFA_SFP_MEDIA_LW = 0x02,
765 BFA_SFP_MEDIA_SW = 0x03,
766 BFA_SFP_MEDIA_EL = 0x04,
767 BFA_SFP_MEDIA_UNSUPPORT = 0x05,
768};
769
770
771
772
773enum {
774 SFP_XMTR_TECH_CU = (1 << 0),
775 SFP_XMTR_TECH_CP = (1 << 1),
776 SFP_XMTR_TECH_CA = (1 << 2),
777 SFP_XMTR_TECH_LL = (1 << 3),
778 SFP_XMTR_TECH_SL = (1 << 4),
779 SFP_XMTR_TECH_SN = (1 << 5),
780 SFP_XMTR_TECH_EL_INTRA = (1 << 6),
781 SFP_XMTR_TECH_EL_INTER = (1 << 7),
782 SFP_XMTR_TECH_LC = (1 << 8),
783 SFP_XMTR_TECH_SA = (1 << 9)
784};
785
786
787
788
789
790struct sfp_srlid_base_s {
791 u8 id;
792 u8 extid;
793 u8 connector;
794 u8 xcvr[8];
795 u8 encoding;
796 u8 br_norm;
797 u8 rate_id;
798 u8 len_km;
799 u8 len_100m;
800 u8 len_om2;
801 u8 len_om1;
802 u8 len_cu;
803 u8 len_om3;
804 u8 vendor_name[16];
805 u8 unalloc1;
806 u8 vendor_oui[3];
807 u8 vendor_pn[16];
808 u8 vendor_rev[4];
809 u8 wavelen[2];
810 u8 unalloc2;
811 u8 cc_base;
812};
813
814
815
816
817
818struct sfp_srlid_ext_s {
819 u8 options[2];
820 u8 br_max;
821 u8 br_min;
822 u8 vendor_sn[16];
823 u8 date_code[8];
824 u8 diag_mon_type;
825 u8 en_options;
826 u8 sff_8472;
827 u8 cc_ext;
828};
829
830
831
832
833
834struct sfp_diag_base_s {
835
836
837
838 u8 temp_high_alarm[2];
839 u8 temp_low_alarm[2];
840 u8 temp_high_warning[2];
841 u8 temp_low_warning[2];
842
843 u8 volt_high_alarm[2];
844 u8 volt_low_alarm[2];
845 u8 volt_high_warning[2];
846 u8 volt_low_warning[2];
847
848 u8 bias_high_alarm[2];
849 u8 bias_low_alarm[2];
850 u8 bias_high_warning[2];
851 u8 bias_low_warning[2];
852
853 u8 tx_pwr_high_alarm[2];
854 u8 tx_pwr_low_alarm[2];
855 u8 tx_pwr_high_warning[2];
856 u8 tx_pwr_low_warning[2];
857
858 u8 rx_pwr_high_alarm[2];
859 u8 rx_pwr_low_alarm[2];
860 u8 rx_pwr_high_warning[2];
861 u8 rx_pwr_low_warning[2];
862
863 u8 unallocate_1[16];
864
865
866
867
868 u8 rx_pwr[20];
869 u8 tx_i[4];
870 u8 tx_pwr[4];
871 u8 temp[4];
872 u8 volt[4];
873 u8 unallocate_2[3];
874 u8 cc_dmi;
875};
876
877
878
879
880
881struct sfp_diag_ext_s {
882 u8 diag[SFP_DIAGMON_SIZE];
883 u8 unalloc1[4];
884 u8 status_ctl;
885 u8 rsvd;
886 u8 alarm_flags[2];
887 u8 unalloc2[2];
888 u8 warning_flags[2];
889 u8 ext_status_ctl[2];
890};
891
892struct sfp_mem_s {
893 struct sfp_srlid_base_s srlid_base;
894 struct sfp_srlid_ext_s srlid_ext;
895 struct sfp_diag_base_s diag_base;
896 struct sfp_diag_ext_s diag_ext;
897};
898
899
900
901
902union sfp_xcvr_e10g_code_u {
903 u8 b;
904 struct {
905#ifdef __BIG_ENDIAN
906 u8 e10g_unall:1;
907 u8 e10g_lrm:1;
908 u8 e10g_lr:1;
909 u8 e10g_sr:1;
910 u8 ib_sx:1;
911 u8 ib_lx:1;
912 u8 ib_cu_a:1;
913 u8 ib_cu_p:1;
914#else
915 u8 ib_cu_p:1;
916 u8 ib_cu_a:1;
917 u8 ib_lx:1;
918 u8 ib_sx:1;
919 u8 e10g_sr:1;
920 u8 e10g_lr:1;
921 u8 e10g_lrm:1;
922 u8 e10g_unall:1;
923#endif
924 } r;
925};
926
927union sfp_xcvr_so1_code_u {
928 u8 b;
929 struct {
930 u8 escon:2;
931 u8 oc192_reach:1;
932 u8 so_reach:2;
933 u8 oc48_reach:3;
934 } r;
935};
936
937union sfp_xcvr_so2_code_u {
938 u8 b;
939 struct {
940 u8 reserved:1;
941 u8 oc12_reach:3;
942 u8 reserved1:1;
943 u8 oc3_reach:3;
944 } r;
945};
946
947union sfp_xcvr_eth_code_u {
948 u8 b;
949 struct {
950 u8 base_px:1;
951 u8 base_bx10:1;
952 u8 e100base_fx:1;
953 u8 e100base_lx:1;
954 u8 e1000base_t:1;
955 u8 e1000base_cx:1;
956 u8 e1000base_lx:1;
957 u8 e1000base_sx:1;
958 } r;
959};
960
961struct sfp_xcvr_fc1_code_s {
962 u8 link_len:5;
963 u8 xmtr_tech2:3;
964 u8 xmtr_tech1:7;
965 u8 reserved1:1;
966};
967
968union sfp_xcvr_fc2_code_u {
969 u8 b;
970 struct {
971 u8 tw_media:1;
972 u8 tp_media:1;
973 u8 mi_media:1;
974 u8 tv_media:1;
975 u8 m6_media:1;
976 u8 m5_media:1;
977 u8 reserved:1;
978 u8 sm_media:1;
979 } r;
980};
981
982union sfp_xcvr_fc3_code_u {
983 u8 b;
984 struct {
985#ifdef __BIG_ENDIAN
986 u8 rsv4:1;
987 u8 mb800:1;
988 u8 mb1600:1;
989 u8 mb400:1;
990 u8 rsv2:1;
991 u8 mb200:1;
992 u8 rsv1:1;
993 u8 mb100:1;
994#else
995 u8 mb100:1;
996 u8 rsv1:1;
997 u8 mb200:1;
998 u8 rsv2:1;
999 u8 mb400:1;
1000 u8 mb1600:1;
1001 u8 mb800:1;
1002 u8 rsv4:1;
1003#endif
1004 } r;
1005};
1006
1007struct sfp_xcvr_s {
1008 union sfp_xcvr_e10g_code_u e10g;
1009 union sfp_xcvr_so1_code_u so1;
1010 union sfp_xcvr_so2_code_u so2;
1011 union sfp_xcvr_eth_code_u eth;
1012 struct sfp_xcvr_fc1_code_s fc1;
1013 union sfp_xcvr_fc2_code_u fc2;
1014 union sfp_xcvr_fc3_code_u fc3;
1015};
1016
1017
1018
1019
1020#define BFA_FLASH_PART_ENTRY_SIZE 32
1021#define BFA_FLASH_PART_MAX 32
1022
1023enum bfa_flash_part_type {
1024 BFA_FLASH_PART_OPTROM = 1,
1025 BFA_FLASH_PART_FWIMG = 2,
1026 BFA_FLASH_PART_FWCFG = 3,
1027 BFA_FLASH_PART_DRV = 4,
1028 BFA_FLASH_PART_BOOT = 5,
1029 BFA_FLASH_PART_ASIC = 6,
1030 BFA_FLASH_PART_MFG = 7,
1031 BFA_FLASH_PART_OPTROM2 = 8,
1032 BFA_FLASH_PART_VPD = 9,
1033 BFA_FLASH_PART_PBC = 10,
1034 BFA_FLASH_PART_BOOTOVL = 11,
1035 BFA_FLASH_PART_LOG = 12,
1036 BFA_FLASH_PART_PXECFG = 13,
1037 BFA_FLASH_PART_PXEOVL = 14,
1038 BFA_FLASH_PART_PORTCFG = 15,
1039 BFA_FLASH_PART_ASICBK = 16,
1040};
1041
1042
1043
1044
1045struct bfa_flash_part_attr_s {
1046 u32 part_type;
1047 u32 part_instance;
1048 u32 part_off;
1049 u32 part_size;
1050 u32 part_len;
1051 u32 part_status;
1052 char rsv[BFA_FLASH_PART_ENTRY_SIZE - 24];
1053};
1054
1055
1056
1057
1058struct bfa_flash_attr_s {
1059 u32 status;
1060 u32 npart;
1061 struct bfa_flash_part_attr_s part[BFA_FLASH_PART_MAX];
1062};
1063
1064
1065
1066
1067#define LB_PATTERN_DEFAULT 0xB5B5B5B5
1068#define QTEST_CNT_DEFAULT 10
1069#define QTEST_PAT_DEFAULT LB_PATTERN_DEFAULT
1070
1071struct bfa_diag_memtest_s {
1072 u8 algo;
1073 u8 rsvd[7];
1074};
1075
1076struct bfa_diag_memtest_result {
1077 u32 status;
1078 u32 addr;
1079 u32 exp;
1080 u32 act;
1081 u32 err_status;
1082 u32 err_status1;
1083 u32 err_addr;
1084 u8 algo;
1085 u8 rsv[3];
1086};
1087
1088struct bfa_diag_loopback_result_s {
1089 u32 numtxmfrm;
1090 u32 numosffrm;
1091 u32 numrcvfrm;
1092 u32 badfrminf;
1093 u32 badfrmnum;
1094 u8 status;
1095 u8 rsvd[3];
1096};
1097
1098struct bfa_diag_ledtest_s {
1099 u32 cmd;
1100 u32 color;
1101 u16 freq;
1102 u8 led;
1103 u8 rsvd[5];
1104};
1105
1106struct bfa_diag_loopback_s {
1107 u32 loopcnt;
1108 u32 pattern;
1109 u8 lb_mode;
1110 u8 speed;
1111 u8 rsvd[2];
1112};
1113
1114
1115
1116
1117enum bfa_phy_status_e {
1118 BFA_PHY_STATUS_GOOD = 0,
1119 BFA_PHY_STATUS_NOT_PRESENT = 1,
1120 BFA_PHY_STATUS_BAD = 2,
1121};
1122
1123
1124
1125
1126struct bfa_phy_attr_s {
1127 u32 status;
1128 u32 length;
1129 u32 fw_ver;
1130 u32 an_status;
1131 u32 pma_pmd_status;
1132 u32 pma_pmd_signal;
1133 u32 pcs_status;
1134};
1135
1136
1137
1138
1139struct bfa_phy_stats_s {
1140 u32 status;
1141 u32 link_breaks;
1142 u32 pma_pmd_fault;
1143 u32 pcs_fault;
1144 u32 speed_neg;
1145 u32 tx_eq_training;
1146 u32 tx_eq_timeout;
1147 u32 crc_error;
1148};
1149
1150#pragma pack()
1151
1152#endif
1153