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26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/string.h>
30#include <linux/timer.h>
31#include <linux/ioport.h>
32#include <linux/major.h>
33#include <linux/blkdev.h>
34#include <linux/interrupt.h>
35#include <linux/pci.h>
36#include <linux/delay.h>
37#include <linux/ctype.h>
38#include <linux/dma-mapping.h>
39
40#include <asm/dma.h>
41#include <asm/io.h>
42
43#include <scsi/scsi.h>
44#include <scsi/scsi_cmnd.h>
45#include <scsi/scsi_device.h>
46#include <scsi/scsi_host.h>
47#include <scsi/scsi_ioctl.h>
48
49#include "nsp32.h"
50
51
52
53
54
55static int trans_mode = 0;
56module_param (trans_mode, int, 0);
57MODULE_PARM_DESC(trans_mode, "transfer mode (0: BIOS(default) 1: Async 2: Ultra20M");
58#define ASYNC_MODE 1
59#define ULTRA20M_MODE 2
60
61static bool auto_param = 0;
62module_param (auto_param, bool, 0);
63MODULE_PARM_DESC(auto_param, "AutoParameter mode (0: ON(default) 1: OFF)");
64
65static bool disc_priv = 1;
66module_param (disc_priv, bool, 0);
67MODULE_PARM_DESC(disc_priv, "disconnection privilege mode (0: ON 1: OFF(default))");
68
69MODULE_AUTHOR("YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>, GOTO Masanori <gotom@debian.or.jp>");
70MODULE_DESCRIPTION("Workbit NinjaSCSI-32Bi/UDE CardBus/PCI SCSI host bus adapter module");
71MODULE_LICENSE("GPL");
72
73static const char *nsp32_release_version = "1.2";
74
75
76
77
78
79static struct pci_device_id nsp32_pci_table[] __devinitdata = {
80 {
81 .vendor = PCI_VENDOR_ID_IODATA,
82 .device = PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II,
83 .subvendor = PCI_ANY_ID,
84 .subdevice = PCI_ANY_ID,
85 .driver_data = MODEL_IODATA,
86 },
87 {
88 .vendor = PCI_VENDOR_ID_WORKBIT,
89 .device = PCI_DEVICE_ID_NINJASCSI_32BI_KME,
90 .subvendor = PCI_ANY_ID,
91 .subdevice = PCI_ANY_ID,
92 .driver_data = MODEL_KME,
93 },
94 {
95 .vendor = PCI_VENDOR_ID_WORKBIT,
96 .device = PCI_DEVICE_ID_NINJASCSI_32BI_WBT,
97 .subvendor = PCI_ANY_ID,
98 .subdevice = PCI_ANY_ID,
99 .driver_data = MODEL_WORKBIT,
100 },
101 {
102 .vendor = PCI_VENDOR_ID_WORKBIT,
103 .device = PCI_DEVICE_ID_WORKBIT_STANDARD,
104 .subvendor = PCI_ANY_ID,
105 .subdevice = PCI_ANY_ID,
106 .driver_data = MODEL_PCI_WORKBIT,
107 },
108 {
109 .vendor = PCI_VENDOR_ID_WORKBIT,
110 .device = PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC,
111 .subvendor = PCI_ANY_ID,
112 .subdevice = PCI_ANY_ID,
113 .driver_data = MODEL_LOGITEC,
114 },
115 {
116 .vendor = PCI_VENDOR_ID_WORKBIT,
117 .device = PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC,
118 .subvendor = PCI_ANY_ID,
119 .subdevice = PCI_ANY_ID,
120 .driver_data = MODEL_PCI_LOGITEC,
121 },
122 {
123 .vendor = PCI_VENDOR_ID_WORKBIT,
124 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO,
125 .subvendor = PCI_ANY_ID,
126 .subdevice = PCI_ANY_ID,
127 .driver_data = MODEL_PCI_MELCO,
128 },
129 {
130 .vendor = PCI_VENDOR_ID_WORKBIT,
131 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II,
132 .subvendor = PCI_ANY_ID,
133 .subdevice = PCI_ANY_ID,
134 .driver_data = MODEL_PCI_MELCO,
135 },
136 {0,0,},
137};
138MODULE_DEVICE_TABLE(pci, nsp32_pci_table);
139
140static nsp32_hw_data nsp32_data_base;
141
142
143
144
145
146
147
148static nsp32_sync_table nsp32_sync_table_40M[] = {
149
150 {0x1, 0, 0x0c, 0x0c, SMPL_40M},
151 {0x2, 0, 0x0d, 0x18, SMPL_40M},
152 {0x3, 1, 0x19, 0x19, SMPL_40M},
153 {0x4, 1, 0x1a, 0x1f, SMPL_20M},
154 {0x5, 2, 0x20, 0x25, SMPL_20M},
155 {0x6, 2, 0x26, 0x31, SMPL_20M},
156 {0x7, 3, 0x32, 0x32, SMPL_20M},
157 {0x8, 3, 0x33, 0x38, SMPL_10M},
158 {0x9, 3, 0x39, 0x3e, SMPL_10M},
159};
160
161static nsp32_sync_table nsp32_sync_table_20M[] = {
162 {0x1, 0, 0x19, 0x19, SMPL_40M},
163 {0x2, 0, 0x1a, 0x25, SMPL_20M},
164 {0x3, 1, 0x26, 0x32, SMPL_20M},
165 {0x4, 1, 0x33, 0x3e, SMPL_10M},
166 {0x5, 2, 0x3f, 0x4b, SMPL_10M},
167 {0x6, 2, 0x4c, 0x57, SMPL_10M},
168 {0x7, 3, 0x58, 0x64, SMPL_10M},
169 {0x8, 3, 0x65, 0x70, SMPL_10M},
170 {0x9, 3, 0x71, 0x7d, SMPL_10M},
171};
172
173static nsp32_sync_table nsp32_sync_table_pci[] = {
174 {0x1, 0, 0x0c, 0x0f, SMPL_40M},
175 {0x2, 0, 0x10, 0x16, SMPL_40M},
176 {0x3, 1, 0x17, 0x1e, SMPL_20M},
177 {0x4, 1, 0x1f, 0x25, SMPL_20M},
178 {0x5, 2, 0x26, 0x2d, SMPL_20M},
179 {0x6, 2, 0x2e, 0x34, SMPL_10M},
180 {0x7, 3, 0x35, 0x3c, SMPL_10M},
181 {0x8, 3, 0x3d, 0x43, SMPL_10M},
182 {0x9, 3, 0x44, 0x4b, SMPL_10M},
183};
184
185
186
187
188
189static int __devinit nsp32_probe (struct pci_dev *, const struct pci_device_id *);
190static void __devexit nsp32_remove(struct pci_dev *);
191static int __init init_nsp32 (void);
192static void __exit exit_nsp32 (void);
193
194
195static int nsp32_proc_info (struct Scsi_Host *, char *, char **, off_t, int, int);
196
197static int nsp32_detect (struct pci_dev *pdev);
198static int nsp32_queuecommand(struct Scsi_Host *, struct scsi_cmnd *);
199static const char *nsp32_info (struct Scsi_Host *);
200static int nsp32_release (struct Scsi_Host *);
201
202
203static int nsp32_eh_abort (struct scsi_cmnd *);
204static int nsp32_eh_bus_reset (struct scsi_cmnd *);
205static int nsp32_eh_host_reset(struct scsi_cmnd *);
206
207
208static void nsp32_build_identify(struct scsi_cmnd *);
209static void nsp32_build_nop (struct scsi_cmnd *);
210static void nsp32_build_reject (struct scsi_cmnd *);
211static void nsp32_build_sdtr (struct scsi_cmnd *, unsigned char, unsigned char);
212
213
214static int nsp32_busfree_occur(struct scsi_cmnd *, unsigned short);
215static void nsp32_msgout_occur (struct scsi_cmnd *);
216static void nsp32_msgin_occur (struct scsi_cmnd *, unsigned long, unsigned short);
217
218static int nsp32_setup_sg_table (struct scsi_cmnd *);
219static int nsp32_selection_autopara(struct scsi_cmnd *);
220static int nsp32_selection_autoscsi(struct scsi_cmnd *);
221static void nsp32_scsi_done (struct scsi_cmnd *);
222static int nsp32_arbitration (struct scsi_cmnd *, unsigned int);
223static int nsp32_reselection (struct scsi_cmnd *, unsigned char);
224static void nsp32_adjust_busfree (struct scsi_cmnd *, unsigned int);
225static void nsp32_restart_autoscsi (struct scsi_cmnd *, unsigned short);
226
227
228static void nsp32_analyze_sdtr (struct scsi_cmnd *);
229static int nsp32_search_period_entry(nsp32_hw_data *, nsp32_target *, unsigned char);
230static void nsp32_set_async (nsp32_hw_data *, nsp32_target *);
231static void nsp32_set_max_sync (nsp32_hw_data *, nsp32_target *, unsigned char *, unsigned char *);
232static void nsp32_set_sync_entry (nsp32_hw_data *, nsp32_target *, int, unsigned char);
233
234
235static void nsp32_wait_req (nsp32_hw_data *, int);
236static void nsp32_wait_sack (nsp32_hw_data *, int);
237static void nsp32_sack_assert (nsp32_hw_data *);
238static void nsp32_sack_negate (nsp32_hw_data *);
239static void nsp32_do_bus_reset(nsp32_hw_data *);
240
241
242static irqreturn_t do_nsp32_isr(int, void *);
243
244
245static int nsp32hw_init(nsp32_hw_data *);
246
247
248static int nsp32_getprom_param (nsp32_hw_data *);
249static int nsp32_getprom_at24 (nsp32_hw_data *);
250static int nsp32_getprom_c16 (nsp32_hw_data *);
251static void nsp32_prom_start (nsp32_hw_data *);
252static void nsp32_prom_stop (nsp32_hw_data *);
253static int nsp32_prom_read (nsp32_hw_data *, int);
254static int nsp32_prom_read_bit (nsp32_hw_data *);
255static void nsp32_prom_write_bit(nsp32_hw_data *, int);
256static void nsp32_prom_set (nsp32_hw_data *, int, int);
257static int nsp32_prom_get (nsp32_hw_data *, int);
258
259
260static void nsp32_message (const char *, int, char *, char *, ...);
261#ifdef NSP32_DEBUG
262static void nsp32_dmessage(const char *, int, int, char *, ...);
263#endif
264
265
266
267
268static struct scsi_host_template nsp32_template = {
269 .proc_name = "nsp32",
270 .name = "Workbit NinjaSCSI-32Bi/UDE",
271 .proc_info = nsp32_proc_info,
272 .info = nsp32_info,
273 .queuecommand = nsp32_queuecommand,
274 .can_queue = 1,
275 .sg_tablesize = NSP32_SG_SIZE,
276 .max_sectors = 128,
277 .cmd_per_lun = 1,
278 .this_id = NSP32_HOST_SCSIID,
279 .use_clustering = DISABLE_CLUSTERING,
280 .eh_abort_handler = nsp32_eh_abort,
281 .eh_bus_reset_handler = nsp32_eh_bus_reset,
282 .eh_host_reset_handler = nsp32_eh_host_reset,
283
284};
285
286#include "nsp32_io.h"
287
288
289
290
291#ifndef NSP32_DEBUG
292# define NSP32_DEBUG_MASK 0x000000
293# define nsp32_msg(type, args...) nsp32_message ("", 0, (type), args)
294# define nsp32_dbg(mask, args...)
295#else
296# define NSP32_DEBUG_MASK 0xffffff
297# define nsp32_msg(type, args...) \
298 nsp32_message (__func__, __LINE__, (type), args)
299# define nsp32_dbg(mask, args...) \
300 nsp32_dmessage(__func__, __LINE__, (mask), args)
301#endif
302
303#define NSP32_DEBUG_QUEUECOMMAND BIT(0)
304#define NSP32_DEBUG_REGISTER BIT(1)
305#define NSP32_DEBUG_AUTOSCSI BIT(2)
306#define NSP32_DEBUG_INTR BIT(3)
307#define NSP32_DEBUG_SGLIST BIT(4)
308#define NSP32_DEBUG_BUSFREE BIT(5)
309#define NSP32_DEBUG_CDB_CONTENTS BIT(6)
310#define NSP32_DEBUG_RESELECTION BIT(7)
311#define NSP32_DEBUG_MSGINOCCUR BIT(8)
312#define NSP32_DEBUG_EEPROM BIT(9)
313#define NSP32_DEBUG_MSGOUTOCCUR BIT(10)
314#define NSP32_DEBUG_BUSRESET BIT(11)
315#define NSP32_DEBUG_RESTART BIT(12)
316#define NSP32_DEBUG_SYNC BIT(13)
317#define NSP32_DEBUG_WAIT BIT(14)
318#define NSP32_DEBUG_TARGETFLAG BIT(15)
319#define NSP32_DEBUG_PROC BIT(16)
320#define NSP32_DEBUG_INIT BIT(17)
321#define NSP32_SPECIAL_PRINT_REGISTER BIT(20)
322
323#define NSP32_DEBUG_BUF_LEN 100
324
325static void nsp32_message(const char *func, int line, char *type, char *fmt, ...)
326{
327 va_list args;
328 char buf[NSP32_DEBUG_BUF_LEN];
329
330 va_start(args, fmt);
331 vsnprintf(buf, sizeof(buf), fmt, args);
332 va_end(args);
333
334#ifndef NSP32_DEBUG
335 printk("%snsp32: %s\n", type, buf);
336#else
337 printk("%snsp32: %s (%d): %s\n", type, func, line, buf);
338#endif
339}
340
341#ifdef NSP32_DEBUG
342static void nsp32_dmessage(const char *func, int line, int mask, char *fmt, ...)
343{
344 va_list args;
345 char buf[NSP32_DEBUG_BUF_LEN];
346
347 va_start(args, fmt);
348 vsnprintf(buf, sizeof(buf), fmt, args);
349 va_end(args);
350
351 if (mask & NSP32_DEBUG_MASK) {
352 printk("nsp32-debug: 0x%x %s (%d): %s\n", mask, func, line, buf);
353 }
354}
355#endif
356
357#ifdef NSP32_DEBUG
358# include "nsp32_debug.c"
359#else
360# define show_command(arg)
361# define show_busphase(arg)
362# define show_autophase(arg)
363#endif
364
365
366
367
368static void nsp32_build_identify(struct scsi_cmnd *SCpnt)
369{
370 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
371 int pos = data->msgout_len;
372 int mode = FALSE;
373
374
375 if (disc_priv == 0) {
376
377 }
378
379 data->msgoutbuf[pos] = IDENTIFY(mode, SCpnt->device->lun); pos++;
380
381 data->msgout_len = pos;
382}
383
384
385
386
387static void nsp32_build_sdtr(struct scsi_cmnd *SCpnt,
388 unsigned char period,
389 unsigned char offset)
390{
391 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
392 int pos = data->msgout_len;
393
394 data->msgoutbuf[pos] = EXTENDED_MESSAGE; pos++;
395 data->msgoutbuf[pos] = EXTENDED_SDTR_LEN; pos++;
396 data->msgoutbuf[pos] = EXTENDED_SDTR; pos++;
397 data->msgoutbuf[pos] = period; pos++;
398 data->msgoutbuf[pos] = offset; pos++;
399
400 data->msgout_len = pos;
401}
402
403
404
405
406static void nsp32_build_nop(struct scsi_cmnd *SCpnt)
407{
408 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
409 int pos = data->msgout_len;
410
411 if (pos != 0) {
412 nsp32_msg(KERN_WARNING,
413 "Some messages are already contained!");
414 return;
415 }
416
417 data->msgoutbuf[pos] = NOP; pos++;
418 data->msgout_len = pos;
419}
420
421
422
423
424static void nsp32_build_reject(struct scsi_cmnd *SCpnt)
425{
426 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
427 int pos = data->msgout_len;
428
429 data->msgoutbuf[pos] = MESSAGE_REJECT; pos++;
430 data->msgout_len = pos;
431}
432
433
434
435
436#if 0
437static void nsp32_start_timer(struct scsi_cmnd *SCpnt, int time)
438{
439 unsigned int base = SCpnt->host->io_port;
440
441 nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
442
443 if (time & (~TIMER_CNT_MASK)) {
444 nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
445 }
446
447 nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK);
448}
449#endif
450
451
452
453
454
455static int nsp32_selection_autopara(struct scsi_cmnd *SCpnt)
456{
457 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
458 unsigned int base = SCpnt->device->host->io_port;
459 unsigned int host_id = SCpnt->device->host->this_id;
460 unsigned char target = scmd_id(SCpnt);
461 nsp32_autoparam *param = data->autoparam;
462 unsigned char phase;
463 int i, ret;
464 unsigned int msgout;
465 u16_le s;
466
467 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
468
469
470
471
472 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
473 if (phase != BUSMON_BUS_FREE) {
474 nsp32_msg(KERN_WARNING, "bus busy");
475 show_busphase(phase & BUSMON_PHASE_MASK);
476 SCpnt->result = DID_BUS_BUSY << 16;
477 return FALSE;
478 }
479
480
481
482
483
484
485
486 if (data->msgout_len == 0) {
487 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
488 SCpnt->result = DID_ERROR << 16;
489 return FALSE;
490 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
491 msgout = 0;
492 for (i = 0; i < data->msgout_len; i++) {
493
494
495
496
497
498
499 msgout >>= 8;
500 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
501 }
502 msgout |= MV_VALID;
503 msgout |= (unsigned int)data->msgout_len;
504 } else {
505
506 msgout = 0;
507 }
508
509
510
511
512
513
514
515 memset(param, 0, sizeof(nsp32_autoparam));
516
517
518 for (i = 0; i < SCpnt->cmd_len; i++) {
519 param->cdb[4 * i] = SCpnt->cmnd[i];
520 }
521
522
523 param->msgout = cpu_to_le32(msgout);
524
525
526 param->syncreg = data->cur_target->syncreg;
527 param->ackwidth = data->cur_target->ackwidth;
528 param->target_id = BIT(host_id) | BIT(target);
529 param->sample_reg = data->cur_target->sample_reg;
530
531
532
533
534 param->command_control = cpu_to_le16(CLEAR_CDB_FIFO_POINTER |
535 AUTOSCSI_START |
536 AUTO_MSGIN_00_OR_04 |
537 AUTO_MSGIN_02 |
538 AUTO_ATN );
539
540
541
542 s = 0;
543 switch (data->trans_method) {
544 case NSP32_TRANSFER_BUSMASTER:
545 s |= BM_START;
546 break;
547 case NSP32_TRANSFER_MMIO:
548 s |= CB_MMIO_MODE;
549 break;
550 case NSP32_TRANSFER_PIO:
551 s |= CB_IO_MODE;
552 break;
553 default:
554 nsp32_msg(KERN_ERR, "unknown trans_method");
555 break;
556 }
557
558
559
560
561 s |= (TRANSFER_GO | ALL_COUNTER_CLR);
562 param->transfer_control = cpu_to_le16(s);
563
564
565 param->sgt_pointer = cpu_to_le32(data->cur_lunt->sglun_paddr);
566
567
568
569
570 nsp32_write4(base, SGT_ADR, data->auto_paddr);
571 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER |
572 AUTO_PARAMETER );
573
574
575
576
577 ret = nsp32_arbitration(SCpnt, base);
578
579 return ret;
580}
581
582
583
584
585
586static int nsp32_selection_autoscsi(struct scsi_cmnd *SCpnt)
587{
588 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
589 unsigned int base = SCpnt->device->host->io_port;
590 unsigned int host_id = SCpnt->device->host->this_id;
591 unsigned char target = scmd_id(SCpnt);
592 unsigned char phase;
593 int status;
594 unsigned short command = 0;
595 unsigned int msgout = 0;
596 unsigned short execph;
597 int i;
598
599 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
600
601
602
603
604 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
605
606
607
608
609 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
610 if(((phase & BUSMON_BSY) == 1) || (phase & BUSMON_SEL) == 1) {
611 nsp32_msg(KERN_WARNING, "bus busy");
612 SCpnt->result = DID_BUS_BUSY << 16;
613 status = 1;
614 goto out;
615 }
616
617
618
619
620 execph = nsp32_read2(base, SCSI_EXECUTE_PHASE);
621
622
623
624
625 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER);
626
627
628
629
630 for (i = 0; i < SCpnt->cmd_len; i++) {
631 nsp32_write1(base, COMMAND_DATA, SCpnt->cmnd[i]);
632 }
633 nsp32_dbg(NSP32_DEBUG_CDB_CONTENTS, "CDB[0]=[0x%x]", SCpnt->cmnd[0]);
634
635
636
637
638 nsp32_write1(base, SCSI_OUT_LATCH_TARGET_ID, BIT(host_id) | BIT(target));
639
640
641
642
643
644
645
646 if (data->msgout_len == 0) {
647 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
648 SCpnt->result = DID_ERROR << 16;
649 status = 1;
650 goto out;
651 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
652 msgout = 0;
653 for (i = 0; i < data->msgout_len; i++) {
654
655
656
657
658
659
660 msgout >>= 8;
661 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
662 }
663 msgout |= MV_VALID;
664 msgout |= (unsigned int)data->msgout_len;
665 nsp32_write4(base, SCSI_MSG_OUT, msgout);
666 } else {
667
668 nsp32_write4(base, SCSI_MSG_OUT, 0);
669 }
670
671
672
673
674 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
675
676
677
678
679
680
681
682 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
683
684
685
686
687 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
688
689
690
691
692
693 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
694
695
696
697
698 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
699
700 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
701 "syncreg=0x%x, ackwidth=0x%x, sgtpaddr=0x%x, id=0x%x",
702 nsp32_read1(base, SYNC_REG), nsp32_read1(base, ACK_WIDTH),
703 nsp32_read4(base, SGT_ADR), nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID));
704 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "msgout_len=%d, msgout=0x%x",
705 data->msgout_len, msgout);
706
707
708
709
710 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
711
712
713
714
715 command = 0;
716 command |= (TRANSFER_GO | ALL_COUNTER_CLR);
717 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
718 if (scsi_bufflen(SCpnt) > 0) {
719 command |= BM_START;
720 }
721 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
722 command |= CB_MMIO_MODE;
723 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
724 command |= CB_IO_MODE;
725 }
726 nsp32_write2(base, TRANSFER_CONTROL, command);
727
728
729
730
731 command = (CLEAR_CDB_FIFO_POINTER |
732 AUTOSCSI_START |
733 AUTO_MSGIN_00_OR_04 |
734 AUTO_MSGIN_02 |
735 AUTO_ATN );
736 nsp32_write2(base, COMMAND_CONTROL, command);
737
738
739
740
741 status = nsp32_arbitration(SCpnt, base);
742
743 out:
744
745
746
747 nsp32_write2(base, IRQ_CONTROL, 0);
748
749 return status;
750}
751
752
753
754
755
756
757
758
759
760
761static int nsp32_arbitration(struct scsi_cmnd *SCpnt, unsigned int base)
762{
763 unsigned char arbit;
764 int status = TRUE;
765 int time = 0;
766
767 do {
768 arbit = nsp32_read1(base, ARBIT_STATUS);
769 time++;
770 } while ((arbit & (ARBIT_WIN | ARBIT_FAIL)) == 0 &&
771 (time <= ARBIT_TIMEOUT_TIME));
772
773 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
774 "arbit: 0x%x, delay time: %d", arbit, time);
775
776 if (arbit & ARBIT_WIN) {
777
778 SCpnt->result = DID_OK << 16;
779 nsp32_index_write1(base, EXT_PORT, LED_ON);
780 } else if (arbit & ARBIT_FAIL) {
781
782 SCpnt->result = DID_BUS_BUSY << 16;
783 status = FALSE;
784 } else {
785
786
787
788
789 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "arbit timeout");
790 SCpnt->result = DID_NO_CONNECT << 16;
791 status = FALSE;
792 }
793
794
795
796
797 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
798
799 return status;
800}
801
802
803
804
805
806
807
808
809
810static int nsp32_reselection(struct scsi_cmnd *SCpnt, unsigned char newlun)
811{
812 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
813 unsigned int host_id = SCpnt->device->host->this_id;
814 unsigned int base = SCpnt->device->host->io_port;
815 unsigned char tmpid, newid;
816
817 nsp32_dbg(NSP32_DEBUG_RESELECTION, "enter");
818
819
820
821
822 tmpid = nsp32_read1(base, RESELECT_ID);
823 tmpid &= (~BIT(host_id));
824 newid = 0;
825 while (tmpid) {
826 if (tmpid & 1) {
827 break;
828 }
829 tmpid >>= 1;
830 newid++;
831 }
832
833
834
835
836
837
838 if (newid >= ARRAY_SIZE(data->lunt) || newlun >= ARRAY_SIZE(data->lunt[0])) {
839 nsp32_msg(KERN_WARNING, "unknown id/lun");
840 return FALSE;
841 } else if(data->lunt[newid][newlun].SCpnt == NULL) {
842 nsp32_msg(KERN_WARNING, "no SCSI command is processing");
843 return FALSE;
844 }
845
846 data->cur_id = newid;
847 data->cur_lun = newlun;
848 data->cur_target = &(data->target[newid]);
849 data->cur_lunt = &(data->lunt[newid][newlun]);
850
851
852 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
853
854 return TRUE;
855}
856
857
858
859
860
861
862
863
864static int nsp32_setup_sg_table(struct scsi_cmnd *SCpnt)
865{
866 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
867 struct scatterlist *sg;
868 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
869 int num, i;
870 u32_le l;
871
872 if (sgt == NULL) {
873 nsp32_dbg(NSP32_DEBUG_SGLIST, "SGT == null");
874 return FALSE;
875 }
876
877 num = scsi_dma_map(SCpnt);
878 if (!num)
879 return TRUE;
880 else if (num < 0)
881 return FALSE;
882 else {
883 scsi_for_each_sg(SCpnt, sg, num, i) {
884
885
886
887 sgt[i].addr = cpu_to_le32(sg_dma_address(sg));
888 sgt[i].len = cpu_to_le32(sg_dma_len(sg));
889
890 if (le32_to_cpu(sgt[i].len) > 0x10000) {
891 nsp32_msg(KERN_ERR,
892 "can't transfer over 64KB at a time, size=0x%lx", le32_to_cpu(sgt[i].len));
893 return FALSE;
894 }
895 nsp32_dbg(NSP32_DEBUG_SGLIST,
896 "num 0x%x : addr 0x%lx len 0x%lx",
897 i,
898 le32_to_cpu(sgt[i].addr),
899 le32_to_cpu(sgt[i].len ));
900 }
901
902
903 l = le32_to_cpu(sgt[num-1].len);
904 sgt[num-1].len = cpu_to_le32(l | SGTEND);
905 }
906
907 return TRUE;
908}
909
910static int nsp32_queuecommand_lck(struct scsi_cmnd *SCpnt, void (*done)(struct scsi_cmnd *))
911{
912 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
913 nsp32_target *target;
914 nsp32_lunt *cur_lunt;
915 int ret;
916
917 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
918 "enter. target: 0x%x LUN: 0x%x cmnd: 0x%x cmndlen: 0x%x "
919 "use_sg: 0x%x reqbuf: 0x%lx reqlen: 0x%x",
920 SCpnt->device->id, SCpnt->device->lun, SCpnt->cmnd[0], SCpnt->cmd_len,
921 scsi_sg_count(SCpnt), scsi_sglist(SCpnt), scsi_bufflen(SCpnt));
922
923 if (data->CurrentSC != NULL) {
924 nsp32_msg(KERN_ERR, "Currentsc != NULL. Cancel this command request");
925 data->CurrentSC = NULL;
926 SCpnt->result = DID_NO_CONNECT << 16;
927 done(SCpnt);
928 return 0;
929 }
930
931
932 if (scmd_id(SCpnt) == SCpnt->device->host->this_id) {
933 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "terget==host???");
934 SCpnt->result = DID_BAD_TARGET << 16;
935 done(SCpnt);
936 return 0;
937 }
938
939
940 if (SCpnt->device->lun >= MAX_LUN) {
941 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "no more lun");
942 SCpnt->result = DID_BAD_TARGET << 16;
943 done(SCpnt);
944 return 0;
945 }
946
947 show_command(SCpnt);
948
949 SCpnt->scsi_done = done;
950 data->CurrentSC = SCpnt;
951 SCpnt->SCp.Status = CHECK_CONDITION;
952 SCpnt->SCp.Message = 0;
953 scsi_set_resid(SCpnt, scsi_bufflen(SCpnt));
954
955 SCpnt->SCp.ptr = (char *)scsi_sglist(SCpnt);
956 SCpnt->SCp.this_residual = scsi_bufflen(SCpnt);
957 SCpnt->SCp.buffer = NULL;
958 SCpnt->SCp.buffers_residual = 0;
959
960
961 data->msgout_len = 0;
962 data->msgin_len = 0;
963 cur_lunt = &(data->lunt[SCpnt->device->id][SCpnt->device->lun]);
964 cur_lunt->SCpnt = SCpnt;
965 cur_lunt->save_datp = 0;
966 cur_lunt->msgin03 = FALSE;
967 data->cur_lunt = cur_lunt;
968 data->cur_id = SCpnt->device->id;
969 data->cur_lun = SCpnt->device->lun;
970
971 ret = nsp32_setup_sg_table(SCpnt);
972 if (ret == FALSE) {
973 nsp32_msg(KERN_ERR, "SGT fail");
974 SCpnt->result = DID_ERROR << 16;
975 nsp32_scsi_done(SCpnt);
976 return 0;
977 }
978
979
980 nsp32_build_identify(SCpnt);
981
982
983
984
985
986
987 target = &data->target[scmd_id(SCpnt)];
988 data->cur_target = target;
989
990 if (!(target->sync_flag & (SDTR_DONE | SDTR_INITIATOR | SDTR_TARGET))) {
991 unsigned char period, offset;
992
993 if (trans_mode != ASYNC_MODE) {
994 nsp32_set_max_sync(data, target, &period, &offset);
995 nsp32_build_sdtr(SCpnt, period, offset);
996 target->sync_flag |= SDTR_INITIATOR;
997 } else {
998 nsp32_set_async(data, target);
999 target->sync_flag |= SDTR_DONE;
1000 }
1001
1002 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1003 "SDTR: entry: %d start_period: 0x%x offset: 0x%x\n",
1004 target->limit_entry, period, offset);
1005 } else if (target->sync_flag & SDTR_INITIATOR) {
1006
1007
1008
1009
1010
1011 nsp32_set_async(data, target);
1012 target->sync_flag &= ~SDTR_INITIATOR;
1013 target->sync_flag |= SDTR_DONE;
1014
1015 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1016 "SDTR_INITIATOR: fall back to async");
1017 } else if (target->sync_flag & SDTR_TARGET) {
1018
1019
1020
1021
1022
1023 nsp32_set_async(data, target);
1024 target->sync_flag &= ~SDTR_TARGET;
1025 target->sync_flag |= SDTR_DONE;
1026
1027 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1028 "Unknown SDTR from target is reached, fall back to async.");
1029 }
1030
1031 nsp32_dbg(NSP32_DEBUG_TARGETFLAG,
1032 "target: %d sync_flag: 0x%x syncreg: 0x%x ackwidth: 0x%x",
1033 SCpnt->device->id, target->sync_flag, target->syncreg,
1034 target->ackwidth);
1035
1036
1037 if (auto_param == 0) {
1038 ret = nsp32_selection_autopara(SCpnt);
1039 } else {
1040 ret = nsp32_selection_autoscsi(SCpnt);
1041 }
1042
1043 if (ret != TRUE) {
1044 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "selection fail");
1045 nsp32_scsi_done(SCpnt);
1046 }
1047
1048 return 0;
1049}
1050
1051static DEF_SCSI_QCMD(nsp32_queuecommand)
1052
1053
1054static int nsp32hw_init(nsp32_hw_data *data)
1055{
1056 unsigned int base = data->BaseAddress;
1057 unsigned short irq_stat;
1058 unsigned long lc_reg;
1059 unsigned char power;
1060
1061 lc_reg = nsp32_index_read4(base, CFG_LATE_CACHE);
1062 if ((lc_reg & 0xff00) == 0) {
1063 lc_reg |= (0x20 << 8);
1064 nsp32_index_write2(base, CFG_LATE_CACHE, lc_reg & 0xffff);
1065 }
1066
1067 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1068 nsp32_write2(base, TRANSFER_CONTROL, 0);
1069 nsp32_write4(base, BM_CNT, 0);
1070 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1071
1072 do {
1073 irq_stat = nsp32_read2(base, IRQ_STATUS);
1074 nsp32_dbg(NSP32_DEBUG_INIT, "irq_stat 0x%x", irq_stat);
1075 } while (irq_stat & IRQSTATUS_ANY_IRQ);
1076
1077
1078
1079
1080
1081 if ((data->trans_method & NSP32_TRANSFER_PIO) ||
1082 (data->trans_method & NSP32_TRANSFER_MMIO)) {
1083 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x40);
1084 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x40);
1085 } else if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1086 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x10);
1087 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x60);
1088 } else {
1089 nsp32_dbg(NSP32_DEBUG_INIT, "unknown transfer mode");
1090 }
1091
1092 nsp32_dbg(NSP32_DEBUG_INIT, "full 0x%x emp 0x%x",
1093 nsp32_index_read1(base, FIFO_FULL_SHLD_COUNT),
1094 nsp32_index_read1(base, FIFO_EMPTY_SHLD_COUNT));
1095
1096 nsp32_index_write1(base, CLOCK_DIV, data->clock);
1097 nsp32_index_write1(base, BM_CYCLE, MEMRD_CMD1 | SGT_AUTO_PARA_MEMED_CMD);
1098 nsp32_write1(base, PARITY_CONTROL, 0);
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115 nsp32_index_write2(base, MISC_WR,
1116 (SCSI_DIRECTION_DETECTOR_SELECT |
1117 DELAYED_BMSTART |
1118 MASTER_TERMINATION_SELECT |
1119 BMREQ_NEGATE_TIMING_SEL |
1120 AUTOSEL_TIMING_SEL |
1121 BMSTOP_CHANGE2_NONDATA_PHASE));
1122
1123 nsp32_index_write1(base, TERM_PWR_CONTROL, 0);
1124 power = nsp32_index_read1(base, TERM_PWR_CONTROL);
1125 if (!(power & SENSE)) {
1126 nsp32_msg(KERN_INFO, "term power on");
1127 nsp32_index_write1(base, TERM_PWR_CONTROL, BPWR);
1128 }
1129
1130 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1131 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1132
1133 nsp32_write1(base, SYNC_REG, 0);
1134 nsp32_write1(base, ACK_WIDTH, 0);
1135 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
1136
1137
1138
1139
1140
1141 nsp32_index_write2(base, IRQ_SELECT, IRQSELECT_TIMER_IRQ |
1142 IRQSELECT_SCSIRESET_IRQ |
1143 IRQSELECT_FIFO_SHLD_IRQ |
1144 IRQSELECT_RESELECT_IRQ |
1145 IRQSELECT_PHASE_CHANGE_IRQ |
1146 IRQSELECT_AUTO_SCSI_SEQ_IRQ |
1147
1148 IRQSELECT_TARGET_ABORT_IRQ |
1149 IRQSELECT_MASTER_ABORT_IRQ );
1150 nsp32_write2(base, IRQ_CONTROL, 0);
1151
1152
1153 nsp32_index_write1(base, EXT_PORT_DDR, LED_OFF);
1154 nsp32_index_write1(base, EXT_PORT, LED_OFF);
1155
1156 return TRUE;
1157}
1158
1159
1160
1161static irqreturn_t do_nsp32_isr(int irq, void *dev_id)
1162{
1163 nsp32_hw_data *data = dev_id;
1164 unsigned int base = data->BaseAddress;
1165 struct scsi_cmnd *SCpnt = data->CurrentSC;
1166 unsigned short auto_stat, irq_stat, trans_stat;
1167 unsigned char busmon, busphase;
1168 unsigned long flags;
1169 int ret;
1170 int handled = 0;
1171 struct Scsi_Host *host = data->Host;
1172
1173 spin_lock_irqsave(host->host_lock, flags);
1174
1175
1176
1177
1178 irq_stat = nsp32_read2(base, IRQ_STATUS);
1179 nsp32_dbg(NSP32_DEBUG_INTR,
1180 "enter IRQ: %d, IRQstatus: 0x%x", irq, irq_stat);
1181
1182 if ((irq_stat & IRQSTATUS_ANY_IRQ) == 0) {
1183 nsp32_dbg(NSP32_DEBUG_INTR, "shared interrupt: irq other 0x%x", irq_stat);
1184 goto out2;
1185 }
1186 handled = 1;
1187 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1188
1189 busmon = nsp32_read1(base, SCSI_BUS_MONITOR);
1190 busphase = busmon & BUSMON_PHASE_MASK;
1191
1192 trans_stat = nsp32_read2(base, TRANSFER_STATUS);
1193 if ((irq_stat == 0xffff) && (trans_stat == 0xffff)) {
1194 nsp32_msg(KERN_INFO, "card disconnect");
1195 if (data->CurrentSC != NULL) {
1196 nsp32_msg(KERN_INFO, "clean up current SCSI command");
1197 SCpnt->result = DID_BAD_TARGET << 16;
1198 nsp32_scsi_done(SCpnt);
1199 }
1200 goto out;
1201 }
1202
1203
1204 if (irq_stat & IRQSTATUS_TIMER_IRQ) {
1205 nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");
1206 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1207 goto out;
1208 }
1209
1210
1211 if (irq_stat & IRQSTATUS_SCSIRESET_IRQ) {
1212 nsp32_msg(KERN_INFO, "detected someone do bus reset");
1213 nsp32_do_bus_reset(data);
1214 if (SCpnt != NULL) {
1215 SCpnt->result = DID_RESET << 16;
1216 nsp32_scsi_done(SCpnt);
1217 }
1218 goto out;
1219 }
1220
1221 if (SCpnt == NULL) {
1222 nsp32_msg(KERN_WARNING, "SCpnt==NULL this can't be happened");
1223 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1224 goto out;
1225 }
1226
1227
1228
1229
1230
1231
1232
1233 if(irq_stat & IRQSTATUS_AUTOSCSI_IRQ) {
1234
1235 auto_stat = nsp32_read2(base, SCSI_EXECUTE_PHASE);
1236 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1237
1238
1239 if (auto_stat & SELECTION_TIMEOUT) {
1240 nsp32_dbg(NSP32_DEBUG_INTR,
1241 "selection timeout occurred");
1242
1243 SCpnt->result = DID_TIME_OUT << 16;
1244 nsp32_scsi_done(SCpnt);
1245 goto out;
1246 }
1247
1248 if (auto_stat & MSGOUT_PHASE) {
1249
1250
1251
1252
1253
1254
1255
1256 if (!(auto_stat & MSG_IN_OCCUER) &&
1257 (data->msgout_len <= 3)) {
1258
1259
1260
1261
1262 data->msgout_len = 0;
1263 };
1264
1265 nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");
1266 }
1267
1268 if ((auto_stat & DATA_IN_PHASE) &&
1269 (scsi_get_resid(SCpnt) > 0) &&
1270 ((nsp32_read2(base, FIFO_REST_CNT) & FIFO_REST_MASK) != 0)) {
1271 printk( "auto+fifo\n");
1272
1273 }
1274
1275 if (auto_stat & (DATA_IN_PHASE | DATA_OUT_PHASE)) {
1276
1277 nsp32_dbg(NSP32_DEBUG_INTR,
1278 "Data in/out phase processed");
1279
1280
1281 nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",
1282 nsp32_read4(base, BM_CNT));
1283 nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",
1284 nsp32_read4(base, SGT_ADR));
1285 nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",
1286 nsp32_read4(base, SACK_CNT));
1287 nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",
1288 nsp32_read4(base, SAVED_SACK_CNT));
1289
1290 scsi_set_resid(SCpnt, 0);
1291 }
1292
1293
1294
1295
1296 if (auto_stat & MSG_IN_OCCUER) {
1297 nsp32_msgin_occur(SCpnt, irq_stat, auto_stat);
1298 }
1299
1300
1301
1302
1303 if (auto_stat & MSG_OUT_OCCUER) {
1304 nsp32_msgout_occur(SCpnt);
1305 }
1306
1307
1308
1309
1310 if (auto_stat & BUS_FREE_OCCUER) {
1311 ret = nsp32_busfree_occur(SCpnt, auto_stat);
1312 if (ret == TRUE) {
1313 goto out;
1314 }
1315 }
1316
1317 if (auto_stat & STATUS_PHASE) {
1318
1319
1320
1321
1322
1323
1324
1325 SCpnt->result = (int)nsp32_read1(base, SCSI_CSB_IN);
1326 }
1327
1328 if (auto_stat & ILLEGAL_PHASE) {
1329
1330 nsp32_msg(KERN_WARNING,
1331 "AUTO SCSI ILLEGAL PHASE OCCUR!!!!");
1332
1333
1334
1335
1336
1337
1338 nsp32_sack_assert(data);
1339 nsp32_wait_req(data, NEGATE);
1340 nsp32_sack_negate(data);
1341
1342 }
1343
1344 if (auto_stat & COMMAND_PHASE) {
1345
1346 nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");
1347 }
1348
1349 if (auto_stat & AUTOSCSI_BUSY) {
1350
1351 }
1352
1353 show_autophase(auto_stat);
1354 }
1355
1356
1357 if (irq_stat & IRQSTATUS_FIFO_SHLD_IRQ) {
1358 nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");
1359
1360 switch(busphase) {
1361 case BUSPHASE_DATA_OUT:
1362 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");
1363
1364
1365
1366 break;
1367
1368 case BUSPHASE_DATA_IN:
1369 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");
1370
1371
1372
1373 break;
1374
1375 case BUSPHASE_STATUS:
1376 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");
1377
1378 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1379
1380 break;
1381 default:
1382 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");
1383 nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1384 show_busphase(busphase);
1385 break;
1386 }
1387
1388 goto out;
1389 }
1390
1391
1392 if (irq_stat & IRQSTATUS_PHASE_CHANGE_IRQ) {
1393 nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");
1394
1395 switch(busphase) {
1396 case BUSPHASE_MESSAGE_IN:
1397 nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");
1398 nsp32_msgin_occur(SCpnt, irq_stat, 0);
1399 break;
1400 default:
1401 nsp32_msg(KERN_WARNING, "phase chg/other phase?");
1402 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x\n",
1403 irq_stat, trans_stat);
1404 show_busphase(busphase);
1405 break;
1406 }
1407 goto out;
1408 }
1409
1410
1411 if (irq_stat & IRQSTATUS_PCI_IRQ) {
1412 nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");
1413
1414 }
1415
1416
1417 if (irq_stat & IRQSTATUS_BMCNTERR_IRQ) {
1418 nsp32_msg(KERN_ERR, "Received unexpected BMCNTERR IRQ! ");
1419
1420
1421
1422
1423
1424 }
1425
1426#if 0
1427 nsp32_dbg(NSP32_DEBUG_INTR,
1428 "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1429 show_busphase(busphase);
1430#endif
1431
1432 out:
1433
1434 nsp32_write2(base, IRQ_CONTROL, 0);
1435
1436 out2:
1437 spin_unlock_irqrestore(host->host_lock, flags);
1438
1439 nsp32_dbg(NSP32_DEBUG_INTR, "exit");
1440
1441 return IRQ_RETVAL(handled);
1442}
1443
1444#undef SPRINTF
1445#define SPRINTF(args...) \
1446 do { \
1447 if(length > (pos - buffer)) { \
1448 pos += snprintf(pos, length - (pos - buffer) + 1, ## args); \
1449 nsp32_dbg(NSP32_DEBUG_PROC, "buffer=0x%p pos=0x%p length=%d %d\n", buffer, pos, length, length - (pos - buffer));\
1450 } \
1451 } while(0)
1452
1453static int nsp32_proc_info(struct Scsi_Host *host, char *buffer, char **start,
1454 off_t offset, int length, int inout)
1455{
1456 char *pos = buffer;
1457 int thislength;
1458 unsigned long flags;
1459 nsp32_hw_data *data;
1460 int hostno;
1461 unsigned int base;
1462 unsigned char mode_reg;
1463 int id, speed;
1464 long model;
1465
1466
1467 if (inout == TRUE) {
1468 return -EINVAL;
1469 }
1470
1471 hostno = host->host_no;
1472 data = (nsp32_hw_data *)host->hostdata;
1473 base = host->io_port;
1474
1475 SPRINTF("NinjaSCSI-32 status\n\n");
1476 SPRINTF("Driver version: %s, $Revision: 1.33 $\n", nsp32_release_version);
1477 SPRINTF("SCSI host No.: %d\n", hostno);
1478 SPRINTF("IRQ: %d\n", host->irq);
1479 SPRINTF("IO: 0x%lx-0x%lx\n", host->io_port, host->io_port + host->n_io_port - 1);
1480 SPRINTF("MMIO(virtual address): 0x%lx-0x%lx\n", host->base, host->base + data->MmioLength - 1);
1481 SPRINTF("sg_tablesize: %d\n", host->sg_tablesize);
1482 SPRINTF("Chip revision: 0x%x\n", (nsp32_read2(base, INDEX_REG) >> 8) & 0xff);
1483
1484 mode_reg = nsp32_index_read1(base, CHIP_MODE);
1485 model = data->pci_devid->driver_data;
1486
1487#ifdef CONFIG_PM
1488 SPRINTF("Power Management: %s\n", (mode_reg & OPTF) ? "yes" : "no");
1489#endif
1490 SPRINTF("OEM: %ld, %s\n", (mode_reg & (OEM0|OEM1)), nsp32_model[model]);
1491
1492 spin_lock_irqsave(&(data->Lock), flags);
1493 SPRINTF("CurrentSC: 0x%p\n\n", data->CurrentSC);
1494 spin_unlock_irqrestore(&(data->Lock), flags);
1495
1496
1497 SPRINTF("SDTR status\n");
1498 for (id = 0; id < ARRAY_SIZE(data->target); id++) {
1499
1500 SPRINTF("id %d: ", id);
1501
1502 if (id == host->this_id) {
1503 SPRINTF("----- NinjaSCSI-32 host adapter\n");
1504 continue;
1505 }
1506
1507 if (data->target[id].sync_flag == SDTR_DONE) {
1508 if (data->target[id].period == 0 &&
1509 data->target[id].offset == ASYNC_OFFSET ) {
1510 SPRINTF("async");
1511 } else {
1512 SPRINTF(" sync");
1513 }
1514 } else {
1515 SPRINTF(" none");
1516 }
1517
1518 if (data->target[id].period != 0) {
1519
1520 speed = 1000000 / (data->target[id].period * 4);
1521
1522 SPRINTF(" transfer %d.%dMB/s, offset %d",
1523 speed / 1000,
1524 speed % 1000,
1525 data->target[id].offset
1526 );
1527 }
1528 SPRINTF("\n");
1529 }
1530
1531
1532 thislength = pos - (buffer + offset);
1533
1534 if(thislength < 0) {
1535 *start = NULL;
1536 return 0;
1537 }
1538
1539
1540 thislength = min(thislength, length);
1541 *start = buffer + offset;
1542
1543 return thislength;
1544}
1545#undef SPRINTF
1546
1547
1548
1549
1550
1551
1552
1553static void nsp32_scsi_done(struct scsi_cmnd *SCpnt)
1554{
1555 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1556 unsigned int base = SCpnt->device->host->io_port;
1557
1558 scsi_dma_unmap(SCpnt);
1559
1560
1561
1562
1563 nsp32_write2(base, TRANSFER_CONTROL, 0);
1564 nsp32_write4(base, BM_CNT, 0);
1565
1566
1567
1568
1569 (*SCpnt->scsi_done)(SCpnt);
1570
1571
1572
1573
1574 data->cur_lunt->SCpnt = NULL;
1575 data->cur_lunt = NULL;
1576 data->cur_target = NULL;
1577 data->CurrentSC = NULL;
1578}
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591static int nsp32_busfree_occur(struct scsi_cmnd *SCpnt, unsigned short execph)
1592{
1593 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1594 unsigned int base = SCpnt->device->host->io_port;
1595
1596 nsp32_dbg(NSP32_DEBUG_BUSFREE, "enter execph=0x%x", execph);
1597 show_autophase(execph);
1598
1599 nsp32_write4(base, BM_CNT, 0);
1600 nsp32_write2(base, TRANSFER_CONTROL, 0);
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613 if (execph & MSGIN_02_VALID) {
1614 nsp32_dbg(NSP32_DEBUG_BUSFREE, "MsgIn02_Valid");
1615
1616
1617
1618
1619
1620 if (!(execph & MSGIN_00_VALID) &&
1621 ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE))) {
1622 unsigned int sacklen, s_sacklen;
1623
1624
1625
1626
1627 sacklen = nsp32_read4(base, SACK_CNT );
1628 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
1629
1630
1631
1632
1633
1634 if (s_sacklen > 0) {
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646 if (sacklen != s_sacklen) {
1647 data->cur_lunt->msgin03 = FALSE;
1648 } else {
1649 data->cur_lunt->msgin03 = TRUE;
1650 }
1651
1652 nsp32_adjust_busfree(SCpnt, s_sacklen);
1653 }
1654 }
1655
1656
1657
1658 } else {
1659
1660
1661
1662 }
1663
1664 if (execph & MSGIN_03_VALID) {
1665
1666 }
1667
1668
1669
1670
1671 if (data->cur_target->sync_flag & SDTR_INITIATOR) {
1672
1673
1674
1675
1676 nsp32_set_async(data, data->cur_target);
1677 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
1678 data->cur_target->sync_flag |= SDTR_DONE;
1679 } else if (data->cur_target->sync_flag & SDTR_TARGET) {
1680
1681
1682
1683
1684 if (execph & (MSGIN_00_VALID | MSGIN_04_VALID)) {
1685
1686
1687
1688
1689 } else {
1690
1691
1692
1693
1694
1695 nsp32_set_async(data, data->cur_target);
1696 }
1697 data->cur_target->sync_flag &= ~SDTR_TARGET;
1698 data->cur_target->sync_flag |= SDTR_DONE;
1699 }
1700
1701
1702
1703
1704
1705
1706
1707 if (execph & MSGIN_00_VALID) {
1708
1709 nsp32_dbg(NSP32_DEBUG_BUSFREE, "command complete");
1710
1711 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1712 SCpnt->SCp.Message = 0;
1713 nsp32_dbg(NSP32_DEBUG_BUSFREE,
1714 "normal end stat=0x%x resid=0x%x\n",
1715 SCpnt->SCp.Status, scsi_get_resid(SCpnt));
1716 SCpnt->result = (DID_OK << 16) |
1717 (SCpnt->SCp.Message << 8) |
1718 (SCpnt->SCp.Status << 0);
1719 nsp32_scsi_done(SCpnt);
1720
1721 return TRUE;
1722 } else if (execph & MSGIN_04_VALID) {
1723
1724 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1725 SCpnt->SCp.Message = 4;
1726
1727 nsp32_dbg(NSP32_DEBUG_BUSFREE, "disconnect");
1728 return TRUE;
1729 } else {
1730
1731 nsp32_msg(KERN_WARNING, "unexpected bus free occurred");
1732
1733
1734
1735 SCpnt->result = DID_ERROR << 16;
1736 nsp32_scsi_done(SCpnt);
1737 return TRUE;
1738 }
1739 return FALSE;
1740}
1741
1742
1743
1744
1745
1746
1747
1748
1749static void nsp32_adjust_busfree(struct scsi_cmnd *SCpnt, unsigned int s_sacklen)
1750{
1751 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1752 int old_entry = data->cur_entry;
1753 int new_entry;
1754 int sg_num = data->cur_lunt->sg_num;
1755 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
1756 unsigned int restlen, sentlen;
1757 u32_le len, addr;
1758
1759 nsp32_dbg(NSP32_DEBUG_SGLIST, "old resid=0x%x", scsi_get_resid(SCpnt));
1760
1761
1762 s_sacklen -= le32_to_cpu(sgt[old_entry].addr) & 3;
1763
1764
1765
1766
1767
1768 sentlen = 0;
1769 for (new_entry = old_entry; new_entry < sg_num; new_entry++) {
1770 sentlen += (le32_to_cpu(sgt[new_entry].len) & ~SGTEND);
1771 if (sentlen > s_sacklen) {
1772 break;
1773 }
1774 }
1775
1776
1777 if (new_entry == sg_num) {
1778 goto last;
1779 }
1780
1781 if (sentlen == s_sacklen) {
1782
1783
1784
1785 }
1786
1787
1788 restlen = sentlen - s_sacklen;
1789
1790
1791 len = le32_to_cpu(sgt[new_entry].len);
1792 addr = le32_to_cpu(sgt[new_entry].addr);
1793 addr += (len - restlen);
1794 sgt[new_entry].addr = cpu_to_le32(addr);
1795 sgt[new_entry].len = cpu_to_le32(restlen);
1796
1797
1798 data->cur_entry = new_entry;
1799
1800 return;
1801
1802 last:
1803 if (scsi_get_resid(SCpnt) < sentlen) {
1804 nsp32_msg(KERN_ERR, "resid underflow");
1805 }
1806
1807 scsi_set_resid(SCpnt, scsi_get_resid(SCpnt) - sentlen);
1808 nsp32_dbg(NSP32_DEBUG_SGLIST, "new resid=0x%x", scsi_get_resid(SCpnt));
1809
1810
1811
1812 return;
1813}
1814
1815
1816
1817
1818
1819
1820
1821
1822static void nsp32_msgout_occur(struct scsi_cmnd *SCpnt)
1823{
1824 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1825 unsigned int base = SCpnt->device->host->io_port;
1826
1827 long new_sgtp;
1828 int i;
1829
1830 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1831 "enter: msgout_len: 0x%x", data->msgout_len);
1832
1833
1834
1835
1836
1837 if (data->msgout_len == 0) {
1838 nsp32_build_nop(SCpnt);
1839 }
1840
1841
1842
1843
1844
1845
1846 new_sgtp = data->cur_lunt->sglun_paddr +
1847 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
1848
1849
1850
1851
1852 for (i = 0; i < data->msgout_len; i++) {
1853 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1854 "%d : 0x%x", i, data->msgoutbuf[i]);
1855
1856
1857
1858
1859 nsp32_wait_req(data, ASSERT);
1860
1861 if (i == (data->msgout_len - 1)) {
1862
1863
1864
1865
1866
1867
1868
1869 nsp32_write2(base, COMMAND_CONTROL,
1870 (CLEAR_CDB_FIFO_POINTER |
1871 AUTO_COMMAND_PHASE |
1872 AUTOSCSI_RESTART |
1873 AUTO_MSGIN_00_OR_04 |
1874 AUTO_MSGIN_02 ));
1875 }
1876
1877
1878
1879
1880 nsp32_write1(base, SCSI_DATA_WITH_ACK, data->msgoutbuf[i]);
1881 nsp32_wait_sack(data, NEGATE);
1882
1883 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "bus: 0x%x\n",
1884 nsp32_read1(base, SCSI_BUS_MONITOR));
1885 };
1886
1887 data->msgout_len = 0;
1888
1889 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "exit");
1890}
1891
1892
1893
1894
1895
1896
1897
1898static void nsp32_restart_autoscsi(struct scsi_cmnd *SCpnt, unsigned short command)
1899{
1900 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1901 unsigned int base = data->BaseAddress;
1902 unsigned short transfer = 0;
1903
1904 nsp32_dbg(NSP32_DEBUG_RESTART, "enter");
1905
1906 if (data->cur_target == NULL || data->cur_lunt == NULL) {
1907 nsp32_msg(KERN_ERR, "Target or Lun is invalid");
1908 }
1909
1910
1911
1912
1913
1914 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
1915
1916
1917
1918
1919 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
1920
1921
1922
1923
1924 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
1925
1926
1927
1928
1929 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
1930
1931
1932
1933
1934 transfer = 0;
1935 transfer |= (TRANSFER_GO | ALL_COUNTER_CLR);
1936 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1937 if (scsi_bufflen(SCpnt) > 0) {
1938 transfer |= BM_START;
1939 }
1940 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
1941 transfer |= CB_MMIO_MODE;
1942 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
1943 transfer |= CB_IO_MODE;
1944 }
1945 nsp32_write2(base, TRANSFER_CONTROL, transfer);
1946
1947
1948
1949
1950
1951
1952 command |= (CLEAR_CDB_FIFO_POINTER |
1953 AUTO_COMMAND_PHASE |
1954 AUTOSCSI_RESTART );
1955 nsp32_write2(base, COMMAND_CONTROL, command);
1956
1957 nsp32_dbg(NSP32_DEBUG_RESTART, "exit");
1958}
1959
1960
1961
1962
1963
1964static void nsp32_msgin_occur(struct scsi_cmnd *SCpnt,
1965 unsigned long irq_status,
1966 unsigned short execph)
1967{
1968 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1969 unsigned int base = SCpnt->device->host->io_port;
1970 unsigned char msg;
1971 unsigned char msgtype;
1972 unsigned char newlun;
1973 unsigned short command = 0;
1974 int msgclear = TRUE;
1975 long new_sgtp;
1976 int ret;
1977
1978
1979
1980
1981
1982
1983 msg = nsp32_read1(base, SCSI_DATA_IN);
1984 data->msginbuf[(unsigned char)data->msgin_len] = msg;
1985 msgtype = data->msginbuf[0];
1986 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR,
1987 "enter: msglen: 0x%x msgin: 0x%x msgtype: 0x%x",
1988 data->msgin_len, msg, msgtype);
1989
1990
1991
1992
1993
1994
1995
1996
1997 nsp32_sack_assert(data);
1998
1999
2000
2001
2002 if (msgtype & 0x80) {
2003 if (!(irq_status & IRQSTATUS_RESELECT_OCCUER)) {
2004
2005 goto reject;
2006 }
2007
2008 newlun = msgtype & 0x1f;
2009 ret = nsp32_reselection(SCpnt, newlun);
2010 if (ret == TRUE) {
2011 goto restart;
2012 } else {
2013 goto reject;
2014 }
2015 }
2016
2017
2018
2019
2020
2021
2022 switch (msgtype) {
2023
2024
2025
2026 case COMMAND_COMPLETE:
2027 case DISCONNECT:
2028
2029
2030
2031
2032 nsp32_msg(KERN_WARNING,
2033 "unexpected message of AutoSCSI MsgIn: 0x%x", msg);
2034 break;
2035
2036 case RESTORE_POINTERS:
2037
2038
2039
2040
2041 if ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE)) {
2042 unsigned int s_sacklen;
2043
2044 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
2045 if ((execph & MSGIN_02_VALID) && (s_sacklen > 0)) {
2046 nsp32_adjust_busfree(SCpnt, s_sacklen);
2047 } else {
2048
2049 }
2050 }
2051 data->cur_lunt->msgin03 = FALSE;
2052
2053
2054
2055
2056 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2057
2058
2059
2060
2061 new_sgtp = data->cur_lunt->sglun_paddr +
2062 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
2063 nsp32_write4(base, SGT_ADR, new_sgtp);
2064
2065 break;
2066
2067 case SAVE_POINTERS:
2068
2069
2070
2071
2072 nsp32_msg (KERN_WARNING,
2073 "unexpected message of AutoSCSI MsgIn: SAVE_POINTERS");
2074
2075 break;
2076
2077 case MESSAGE_REJECT:
2078
2079
2080 if (data->cur_target->sync_flag &
2081 (SDTR_INITIATOR | SDTR_TARGET)) {
2082
2083
2084
2085
2086
2087 nsp32_set_async(data, data->cur_target);
2088 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
2089 data->cur_target->sync_flag |= SDTR_DONE;
2090
2091 }
2092 break;
2093
2094 case LINKED_CMD_COMPLETE:
2095 case LINKED_FLG_CMD_COMPLETE:
2096
2097 nsp32_msg (KERN_WARNING,
2098 "unsupported message: 0x%x", msgtype);
2099 break;
2100
2101 case INITIATE_RECOVERY:
2102
2103
2104
2105 goto reject;
2106
2107
2108
2109
2110 case SIMPLE_QUEUE_TAG:
2111 case 0x23:
2112
2113
2114
2115
2116 if (data->msgin_len >= 1) {
2117 goto reject;
2118 }
2119
2120
2121 msgclear = FALSE;
2122
2123 break;
2124
2125
2126
2127
2128 case EXTENDED_MESSAGE:
2129 if (data->msgin_len < 1) {
2130
2131
2132
2133
2134 msgclear = FALSE;
2135 break;
2136 }
2137
2138 if ((data->msginbuf[1] + 1) > data->msgin_len) {
2139
2140
2141
2142
2143
2144
2145 msgclear = FALSE;
2146 break;
2147 }
2148
2149
2150
2151
2152
2153 switch (data->msginbuf[2]) {
2154 case EXTENDED_MODIFY_DATA_POINTER:
2155
2156 goto reject;
2157 break;
2158
2159 case EXTENDED_SDTR:
2160
2161
2162
2163 if (data->msgin_len != EXTENDED_SDTR_LEN + 1) {
2164
2165
2166
2167 goto reject;
2168 break;
2169 }
2170
2171 nsp32_analyze_sdtr(SCpnt);
2172
2173 break;
2174
2175 case EXTENDED_EXTENDED_IDENTIFY:
2176
2177 goto reject;
2178
2179 break;
2180
2181 case EXTENDED_WDTR:
2182 goto reject;
2183
2184 break;
2185
2186 default:
2187 goto reject;
2188 }
2189 break;
2190
2191 default:
2192 goto reject;
2193 }
2194
2195 restart:
2196 if (msgclear == TRUE) {
2197 data->msgin_len = 0;
2198
2199
2200
2201
2202
2203
2204
2205
2206 if (data->msgout_len > 0) {
2207 nsp32_write4(base, SCSI_MSG_OUT, 0);
2208 command |= AUTO_ATN;
2209 }
2210
2211
2212
2213
2214
2215 command |= (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02);
2216
2217
2218
2219
2220 if (data->cur_lunt->msgin03 == TRUE) {
2221 command |= AUTO_MSGIN_03;
2222 }
2223 data->cur_lunt->msgin03 = FALSE;
2224 } else {
2225 data->msgin_len++;
2226 }
2227
2228
2229
2230
2231 nsp32_restart_autoscsi(SCpnt, command);
2232
2233
2234
2235
2236 nsp32_wait_req(data, NEGATE);
2237
2238
2239
2240
2241 nsp32_sack_negate(data);
2242
2243 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2244
2245 return;
2246
2247 reject:
2248 nsp32_msg(KERN_WARNING,
2249 "invalid or unsupported MessageIn, rejected. "
2250 "current msg: 0x%x (len: 0x%x), processing msg: 0x%x",
2251 msg, data->msgin_len, msgtype);
2252 nsp32_build_reject(SCpnt);
2253 data->msgin_len = 0;
2254
2255 goto restart;
2256}
2257
2258
2259
2260
2261static void nsp32_analyze_sdtr(struct scsi_cmnd *SCpnt)
2262{
2263 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2264 nsp32_target *target = data->cur_target;
2265 nsp32_sync_table *synct;
2266 unsigned char get_period = data->msginbuf[3];
2267 unsigned char get_offset = data->msginbuf[4];
2268 int entry;
2269 int syncnum;
2270
2271 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "enter");
2272
2273 synct = data->synct;
2274 syncnum = data->syncnum;
2275
2276
2277
2278
2279
2280
2281
2282
2283 if (target->sync_flag & SDTR_INITIATOR) {
2284
2285
2286
2287
2288 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target responds SDTR");
2289
2290 target->sync_flag &= ~SDTR_INITIATOR;
2291 target->sync_flag |= SDTR_DONE;
2292
2293
2294
2295
2296 if (get_offset > SYNC_OFFSET) {
2297
2298
2299
2300
2301 goto reject;
2302 }
2303
2304 if (get_offset == ASYNC_OFFSET) {
2305
2306
2307
2308
2309 goto async;
2310 }
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322 if (get_period < data->synct[0].period_num) {
2323
2324
2325
2326
2327 goto reject;
2328 }
2329
2330 entry = nsp32_search_period_entry(data, target, get_period);
2331
2332 if (entry < 0) {
2333
2334
2335
2336
2337 goto reject;
2338 }
2339
2340
2341
2342
2343 nsp32_set_sync_entry(data, target, entry, get_offset);
2344 } else {
2345
2346 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target send SDTR");
2347
2348 target->sync_flag |= SDTR_INITIATOR;
2349
2350
2351 if (get_offset > SYNC_OFFSET) {
2352
2353 get_offset = SYNC_OFFSET;
2354 }
2355
2356
2357 if (get_period < data->synct[0].period_num) {
2358 get_period = data->synct[0].period_num;
2359 }
2360
2361 entry = nsp32_search_period_entry(data, target, get_period);
2362
2363 if (get_offset == ASYNC_OFFSET || entry < 0) {
2364 nsp32_set_async(data, target);
2365 nsp32_build_sdtr(SCpnt, 0, ASYNC_OFFSET);
2366 } else {
2367 nsp32_set_sync_entry(data, target, entry, get_offset);
2368 nsp32_build_sdtr(SCpnt, get_period, get_offset);
2369 }
2370 }
2371
2372 target->period = get_period;
2373 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2374 return;
2375
2376 reject:
2377
2378
2379
2380
2381 nsp32_build_reject(SCpnt);
2382
2383 async:
2384 nsp32_set_async(data, target);
2385
2386 target->period = 0;
2387 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit: set async");
2388 return;
2389}
2390
2391
2392
2393
2394
2395
2396static int nsp32_search_period_entry(nsp32_hw_data *data,
2397 nsp32_target *target,
2398 unsigned char period)
2399{
2400 int i;
2401
2402 if (target->limit_entry >= data->syncnum) {
2403 nsp32_msg(KERN_ERR, "limit_entry exceeds syncnum!");
2404 target->limit_entry = 0;
2405 }
2406
2407 for (i = target->limit_entry; i < data->syncnum; i++) {
2408 if (period >= data->synct[i].start_period &&
2409 period <= data->synct[i].end_period) {
2410 break;
2411 }
2412 }
2413
2414
2415
2416
2417
2418 if (i == data->syncnum) {
2419 i = -1;
2420 }
2421
2422 return i;
2423}
2424
2425
2426
2427
2428
2429static void nsp32_set_async(nsp32_hw_data *data, nsp32_target *target)
2430{
2431 unsigned char period = data->synct[target->limit_entry].period_num;
2432
2433 target->offset = ASYNC_OFFSET;
2434 target->period = 0;
2435 target->syncreg = TO_SYNCREG(period, ASYNC_OFFSET);
2436 target->ackwidth = 0;
2437 target->sample_reg = 0;
2438
2439 nsp32_dbg(NSP32_DEBUG_SYNC, "set async");
2440}
2441
2442
2443
2444
2445
2446static void nsp32_set_max_sync(nsp32_hw_data *data,
2447 nsp32_target *target,
2448 unsigned char *period,
2449 unsigned char *offset)
2450{
2451 unsigned char period_num, ackwidth;
2452
2453 period_num = data->synct[target->limit_entry].period_num;
2454 *period = data->synct[target->limit_entry].start_period;
2455 ackwidth = data->synct[target->limit_entry].ackwidth;
2456 *offset = SYNC_OFFSET;
2457
2458 target->syncreg = TO_SYNCREG(period_num, *offset);
2459 target->ackwidth = ackwidth;
2460 target->offset = *offset;
2461 target->sample_reg = 0;
2462}
2463
2464
2465
2466
2467
2468static void nsp32_set_sync_entry(nsp32_hw_data *data,
2469 nsp32_target *target,
2470 int entry,
2471 unsigned char offset)
2472{
2473 unsigned char period, ackwidth, sample_rate;
2474
2475 period = data->synct[entry].period_num;
2476 ackwidth = data->synct[entry].ackwidth;
2477 offset = offset;
2478 sample_rate = data->synct[entry].sample_rate;
2479
2480 target->syncreg = TO_SYNCREG(period, offset);
2481 target->ackwidth = ackwidth;
2482 target->offset = offset;
2483 target->sample_reg = sample_rate | SAMPLING_ENABLE;
2484
2485 nsp32_dbg(NSP32_DEBUG_SYNC, "set sync");
2486}
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497static void nsp32_wait_req(nsp32_hw_data *data, int state)
2498{
2499 unsigned int base = data->BaseAddress;
2500 int wait_time = 0;
2501 unsigned char bus, req_bit;
2502
2503 if (!((state == ASSERT) || (state == NEGATE))) {
2504 nsp32_msg(KERN_ERR, "unknown state designation");
2505 }
2506
2507 req_bit = (state == ASSERT ? BUSMON_REQ : 0);
2508
2509 do {
2510 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2511 if ((bus & BUSMON_REQ) == req_bit) {
2512 nsp32_dbg(NSP32_DEBUG_WAIT,
2513 "wait_time: %d", wait_time);
2514 return;
2515 }
2516 udelay(1);
2517 wait_time++;
2518 } while (wait_time < REQSACK_TIMEOUT_TIME);
2519
2520 nsp32_msg(KERN_WARNING, "wait REQ timeout, req_bit: 0x%x", req_bit);
2521}
2522
2523
2524
2525
2526static void nsp32_wait_sack(nsp32_hw_data *data, int state)
2527{
2528 unsigned int base = data->BaseAddress;
2529 int wait_time = 0;
2530 unsigned char bus, ack_bit;
2531
2532 if (!((state == ASSERT) || (state == NEGATE))) {
2533 nsp32_msg(KERN_ERR, "unknown state designation");
2534 }
2535
2536 ack_bit = (state == ASSERT ? BUSMON_ACK : 0);
2537
2538 do {
2539 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2540 if ((bus & BUSMON_ACK) == ack_bit) {
2541 nsp32_dbg(NSP32_DEBUG_WAIT,
2542 "wait_time: %d", wait_time);
2543 return;
2544 }
2545 udelay(1);
2546 wait_time++;
2547 } while (wait_time < REQSACK_TIMEOUT_TIME);
2548
2549 nsp32_msg(KERN_WARNING, "wait SACK timeout, ack_bit: 0x%x", ack_bit);
2550}
2551
2552
2553
2554
2555
2556
2557static void nsp32_sack_assert(nsp32_hw_data *data)
2558{
2559 unsigned int base = data->BaseAddress;
2560 unsigned char busctrl;
2561
2562 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2563 busctrl |= (BUSCTL_ACK | AUTODIRECTION | ACKENB);
2564 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2565}
2566
2567
2568
2569
2570static void nsp32_sack_negate(nsp32_hw_data *data)
2571{
2572 unsigned int base = data->BaseAddress;
2573 unsigned char busctrl;
2574
2575 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2576 busctrl &= ~BUSCTL_ACK;
2577 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2578}
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589static int nsp32_detect(struct pci_dev *pdev)
2590{
2591 struct Scsi_Host *host;
2592 struct resource *res;
2593 nsp32_hw_data *data;
2594 int ret;
2595 int i, j;
2596
2597 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
2598
2599
2600
2601
2602 host = scsi_host_alloc(&nsp32_template, sizeof(nsp32_hw_data));
2603 if (host == NULL) {
2604 nsp32_msg (KERN_ERR, "failed to scsi register");
2605 goto err;
2606 }
2607
2608
2609
2610
2611 data = (nsp32_hw_data *)host->hostdata;
2612
2613 memcpy(data, &nsp32_data_base, sizeof(nsp32_hw_data));
2614
2615 host->irq = data->IrqNumber;
2616 host->io_port = data->BaseAddress;
2617 host->unique_id = data->BaseAddress;
2618 host->n_io_port = data->NumAddress;
2619 host->base = (unsigned long)data->MmioAddress;
2620
2621 data->Host = host;
2622 spin_lock_init(&(data->Lock));
2623
2624 data->cur_lunt = NULL;
2625 data->cur_target = NULL;
2626
2627
2628
2629
2630 data->trans_method = NSP32_TRANSFER_BUSMASTER;
2631
2632
2633
2634
2635
2636
2637 data->clock = CLOCK_4;
2638
2639
2640
2641
2642 switch (data->clock) {
2643 case CLOCK_4:
2644
2645 data->synct = nsp32_sync_table_40M;
2646 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2647 break;
2648 case CLOCK_2:
2649
2650 data->synct = nsp32_sync_table_20M;
2651 data->syncnum = ARRAY_SIZE(nsp32_sync_table_20M);
2652 break;
2653 case PCICLK:
2654
2655 data->synct = nsp32_sync_table_pci;
2656 data->syncnum = ARRAY_SIZE(nsp32_sync_table_pci);
2657 break;
2658 default:
2659 nsp32_msg(KERN_WARNING,
2660 "Invalid clock div is selected, set CLOCK_4.");
2661
2662 data->clock = CLOCK_4;
2663 data->synct = nsp32_sync_table_40M;
2664 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2665 }
2666
2667
2668
2669
2670
2671
2672
2673
2674 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
2675 nsp32_msg (KERN_ERR, "failed to set PCI DMA mask");
2676 goto scsi_unregister;
2677 }
2678
2679
2680
2681
2682 data->autoparam = pci_alloc_consistent(pdev, sizeof(nsp32_autoparam), &(data->auto_paddr));
2683 if (data->autoparam == NULL) {
2684 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2685 goto scsi_unregister;
2686 }
2687
2688
2689
2690
2691 data->sg_list = pci_alloc_consistent(pdev, NSP32_SG_TABLE_SIZE,
2692 &(data->sg_paddr));
2693 if (data->sg_list == NULL) {
2694 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2695 goto free_autoparam;
2696 }
2697
2698 for (i = 0; i < ARRAY_SIZE(data->lunt); i++) {
2699 for (j = 0; j < ARRAY_SIZE(data->lunt[0]); j++) {
2700 int offset = i * ARRAY_SIZE(data->lunt[0]) + j;
2701 nsp32_lunt tmp = {
2702 .SCpnt = NULL,
2703 .save_datp = 0,
2704 .msgin03 = FALSE,
2705 .sg_num = 0,
2706 .cur_entry = 0,
2707 .sglun = &(data->sg_list[offset]),
2708 .sglun_paddr = data->sg_paddr + (offset * sizeof(nsp32_sglun)),
2709 };
2710
2711 data->lunt[i][j] = tmp;
2712 }
2713 }
2714
2715
2716
2717
2718 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2719 nsp32_target *target = &(data->target[i]);
2720
2721 target->limit_entry = 0;
2722 target->sync_flag = 0;
2723 nsp32_set_async(data, target);
2724 }
2725
2726
2727
2728
2729 ret = nsp32_getprom_param(data);
2730 if (ret == FALSE) {
2731 data->resettime = 3;
2732 }
2733
2734
2735
2736
2737 nsp32hw_init(data);
2738
2739 snprintf(data->info_str, sizeof(data->info_str),
2740 "NinjaSCSI-32Bi/UDE: irq %d, io 0x%lx+0x%x",
2741 host->irq, host->io_port, host->n_io_port);
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761 nsp32_do_bus_reset(data);
2762
2763 ret = request_irq(host->irq, do_nsp32_isr, IRQF_SHARED, "nsp32", data);
2764 if (ret < 0) {
2765 nsp32_msg(KERN_ERR, "Unable to allocate IRQ for NinjaSCSI32 "
2766 "SCSI PCI controller. Interrupt: %d", host->irq);
2767 goto free_sg_list;
2768 }
2769
2770
2771
2772
2773 res = request_region(host->io_port, host->n_io_port, "nsp32");
2774 if (res == NULL) {
2775 nsp32_msg(KERN_ERR,
2776 "I/O region 0x%lx+0x%lx is already used",
2777 data->BaseAddress, data->NumAddress);
2778 goto free_irq;
2779 }
2780
2781 ret = scsi_add_host(host, &pdev->dev);
2782 if (ret) {
2783 nsp32_msg(KERN_ERR, "failed to add scsi host");
2784 goto free_region;
2785 }
2786 scsi_scan_host(host);
2787 pci_set_drvdata(pdev, host);
2788 return 0;
2789
2790 free_region:
2791 release_region(host->io_port, host->n_io_port);
2792
2793 free_irq:
2794 free_irq(host->irq, data);
2795
2796 free_sg_list:
2797 pci_free_consistent(pdev, NSP32_SG_TABLE_SIZE,
2798 data->sg_list, data->sg_paddr);
2799
2800 free_autoparam:
2801 pci_free_consistent(pdev, sizeof(nsp32_autoparam),
2802 data->autoparam, data->auto_paddr);
2803
2804 scsi_unregister:
2805 scsi_host_put(host);
2806
2807 err:
2808 return 1;
2809}
2810
2811static int nsp32_release(struct Scsi_Host *host)
2812{
2813 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2814
2815 if (data->autoparam) {
2816 pci_free_consistent(data->Pci, sizeof(nsp32_autoparam),
2817 data->autoparam, data->auto_paddr);
2818 }
2819
2820 if (data->sg_list) {
2821 pci_free_consistent(data->Pci, NSP32_SG_TABLE_SIZE,
2822 data->sg_list, data->sg_paddr);
2823 }
2824
2825 if (host->irq) {
2826 free_irq(host->irq, data);
2827 }
2828
2829 if (host->io_port && host->n_io_port) {
2830 release_region(host->io_port, host->n_io_port);
2831 }
2832
2833 if (data->MmioAddress) {
2834 iounmap(data->MmioAddress);
2835 }
2836
2837 return 0;
2838}
2839
2840static const char *nsp32_info(struct Scsi_Host *shpnt)
2841{
2842 nsp32_hw_data *data = (nsp32_hw_data *)shpnt->hostdata;
2843
2844 return data->info_str;
2845}
2846
2847
2848
2849
2850
2851static int nsp32_eh_abort(struct scsi_cmnd *SCpnt)
2852{
2853 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2854 unsigned int base = SCpnt->device->host->io_port;
2855
2856 nsp32_msg(KERN_WARNING, "abort");
2857
2858 if (data->cur_lunt->SCpnt == NULL) {
2859 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort failed");
2860 return FAILED;
2861 }
2862
2863 if (data->cur_target->sync_flag & (SDTR_INITIATOR | SDTR_TARGET)) {
2864
2865 data->cur_target->sync_flag = 0;
2866 nsp32_set_async(data, data->cur_target);
2867 }
2868
2869 nsp32_write2(base, TRANSFER_CONTROL, 0);
2870 nsp32_write2(base, BM_CNT, 0);
2871
2872 SCpnt->result = DID_ABORT << 16;
2873 nsp32_scsi_done(SCpnt);
2874
2875 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort success");
2876 return SUCCESS;
2877}
2878
2879static int nsp32_eh_bus_reset(struct scsi_cmnd *SCpnt)
2880{
2881 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2882 unsigned int base = SCpnt->device->host->io_port;
2883
2884 spin_lock_irq(SCpnt->device->host->host_lock);
2885
2886 nsp32_msg(KERN_INFO, "Bus Reset");
2887 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt);
2888
2889 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
2890 nsp32_do_bus_reset(data);
2891 nsp32_write2(base, IRQ_CONTROL, 0);
2892
2893 spin_unlock_irq(SCpnt->device->host->host_lock);
2894 return SUCCESS;
2895}
2896
2897static void nsp32_do_bus_reset(nsp32_hw_data *data)
2898{
2899 unsigned int base = data->BaseAddress;
2900 unsigned short intrdat;
2901 int i;
2902
2903 nsp32_dbg(NSP32_DEBUG_BUSRESET, "in");
2904
2905
2906
2907
2908
2909
2910 nsp32_write2(base, TRANSFER_CONTROL, 0);
2911 nsp32_write4(base, BM_CNT, 0);
2912 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2913
2914
2915
2916
2917
2918 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2919 nsp32_target *target = &data->target[i];
2920
2921 target->sync_flag = 0;
2922 nsp32_set_async(data, target);
2923 }
2924
2925
2926
2927
2928 nsp32_write1(base, SCSI_BUS_CONTROL, BUSCTL_RST);
2929 udelay(RESET_HOLD_TIME);
2930 nsp32_write1(base, SCSI_BUS_CONTROL, 0);
2931 for(i = 0; i < 5; i++) {
2932 intrdat = nsp32_read2(base, IRQ_STATUS);
2933 nsp32_dbg(NSP32_DEBUG_BUSRESET, "irq:1: 0x%x", intrdat);
2934 }
2935
2936 data->CurrentSC = NULL;
2937}
2938
2939static int nsp32_eh_host_reset(struct scsi_cmnd *SCpnt)
2940{
2941 struct Scsi_Host *host = SCpnt->device->host;
2942 unsigned int base = SCpnt->device->host->io_port;
2943 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2944
2945 nsp32_msg(KERN_INFO, "Host Reset");
2946 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt);
2947
2948 spin_lock_irq(SCpnt->device->host->host_lock);
2949
2950 nsp32hw_init(data);
2951 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
2952 nsp32_do_bus_reset(data);
2953 nsp32_write2(base, IRQ_CONTROL, 0);
2954
2955 spin_unlock_irq(SCpnt->device->host->host_lock);
2956 return SUCCESS;
2957}
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967static int nsp32_getprom_param(nsp32_hw_data *data)
2968{
2969 int vendor = data->pci_devid->vendor;
2970 int device = data->pci_devid->device;
2971 int ret, val, i;
2972
2973
2974
2975
2976 ret = nsp32_prom_read(data, 0x7e);
2977 if (ret != 0x55) {
2978 nsp32_msg(KERN_INFO, "No EEPROM detected: 0x%x", ret);
2979 return FALSE;
2980 }
2981 ret = nsp32_prom_read(data, 0x7f);
2982 if (ret != 0xaa) {
2983 nsp32_msg(KERN_INFO, "Invalid number: 0x%x", ret);
2984 return FALSE;
2985 }
2986
2987
2988
2989
2990 if (vendor == PCI_VENDOR_ID_WORKBIT &&
2991 device == PCI_DEVICE_ID_WORKBIT_STANDARD) {
2992 ret = nsp32_getprom_c16(data);
2993 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2994 device == PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC) {
2995 ret = nsp32_getprom_at24(data);
2996 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2997 device == PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO ) {
2998 ret = nsp32_getprom_at24(data);
2999 } else {
3000 nsp32_msg(KERN_WARNING, "Unknown EEPROM");
3001 ret = FALSE;
3002 }
3003
3004
3005 for (i = 0; i <= 0x1f; i++) {
3006 val = nsp32_prom_read(data, i);
3007 nsp32_dbg(NSP32_DEBUG_EEPROM,
3008 "rom address 0x%x : 0x%x", i, val);
3009 }
3010
3011 return ret;
3012}
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042static int nsp32_getprom_at24(nsp32_hw_data *data)
3043{
3044 int ret, i;
3045 int auto_sync;
3046 nsp32_target *target;
3047 int entry;
3048
3049
3050
3051
3052
3053
3054 data->resettime = nsp32_prom_read(data, 0x12);
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069 ret = nsp32_prom_read(data, 0x07);
3070 switch (ret) {
3071 case 0:
3072 auto_sync = TRUE;
3073 break;
3074 case 1:
3075 auto_sync = FALSE;
3076 break;
3077 default:
3078 nsp32_msg(KERN_WARNING,
3079 "Unsupported Auto Sync mode. Fall back to manual mode.");
3080 auto_sync = TRUE;
3081 }
3082
3083 if (trans_mode == ULTRA20M_MODE) {
3084 auto_sync = TRUE;
3085 }
3086
3087
3088
3089
3090 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3091 target = &data->target[i];
3092 if (auto_sync == TRUE) {
3093 target->limit_entry = 0;
3094 } else {
3095 ret = nsp32_prom_read(data, i);
3096 entry = nsp32_search_period_entry(data, target, ret);
3097 if (entry < 0) {
3098
3099 entry = 0;
3100 }
3101 target->limit_entry = entry;
3102 }
3103 }
3104
3105 return TRUE;
3106}
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129static int nsp32_getprom_c16(nsp32_hw_data *data)
3130{
3131 int ret, i;
3132 nsp32_target *target;
3133 int entry, val;
3134
3135
3136
3137
3138
3139
3140 data->resettime = nsp32_prom_read(data, 0x11);
3141
3142
3143
3144
3145 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3146 target = &data->target[i];
3147 ret = nsp32_prom_read(data, i);
3148 switch (ret) {
3149 case 0:
3150 val = 0x0c;
3151 break;
3152 case 1:
3153 val = 0x19;
3154 break;
3155 case 2:
3156 val = 0x32;
3157 break;
3158 case 3:
3159 val = 0x00;
3160 break;
3161 default:
3162 val = 0x0c;
3163 break;
3164 }
3165 entry = nsp32_search_period_entry(data, target, val);
3166 if (entry < 0 || trans_mode == ULTRA20M_MODE) {
3167
3168 entry = 0;
3169 }
3170 target->limit_entry = entry;
3171 }
3172
3173 return TRUE;
3174}
3175
3176
3177
3178
3179
3180static int nsp32_prom_read(nsp32_hw_data *data, int romaddr)
3181{
3182 int i, val;
3183
3184
3185 nsp32_prom_start(data);
3186
3187
3188 nsp32_prom_write_bit(data, 1);
3189 nsp32_prom_write_bit(data, 0);
3190 nsp32_prom_write_bit(data, 1);
3191 nsp32_prom_write_bit(data, 0);
3192 nsp32_prom_write_bit(data, 0);
3193 nsp32_prom_write_bit(data, 0);
3194 nsp32_prom_write_bit(data, 0);
3195
3196
3197 nsp32_prom_write_bit(data, 0);
3198
3199
3200 nsp32_prom_write_bit(data, 0);
3201
3202
3203 for (i = 7; i >= 0; i--) {
3204 nsp32_prom_write_bit(data, ((romaddr >> i) & 1));
3205 }
3206
3207
3208 nsp32_prom_write_bit(data, 0);
3209
3210
3211 nsp32_prom_start(data);
3212
3213
3214 nsp32_prom_write_bit(data, 1);
3215 nsp32_prom_write_bit(data, 0);
3216 nsp32_prom_write_bit(data, 1);
3217 nsp32_prom_write_bit(data, 0);
3218 nsp32_prom_write_bit(data, 0);
3219 nsp32_prom_write_bit(data, 0);
3220 nsp32_prom_write_bit(data, 0);
3221
3222
3223 nsp32_prom_write_bit(data, 1);
3224
3225
3226 nsp32_prom_write_bit(data, 0);
3227
3228
3229 val = 0;
3230 for (i = 7; i >= 0; i--) {
3231 val += (nsp32_prom_read_bit(data) << i);
3232 }
3233
3234
3235 nsp32_prom_write_bit(data, 1);
3236
3237
3238 nsp32_prom_stop(data);
3239
3240 return val;
3241}
3242
3243static void nsp32_prom_set(nsp32_hw_data *data, int bit, int val)
3244{
3245 int base = data->BaseAddress;
3246 int tmp;
3247
3248 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL);
3249
3250 if (val == 0) {
3251 tmp &= ~bit;
3252 } else {
3253 tmp |= bit;
3254 }
3255
3256 nsp32_index_write1(base, SERIAL_ROM_CTL, tmp);
3257
3258 udelay(10);
3259}
3260
3261static int nsp32_prom_get(nsp32_hw_data *data, int bit)
3262{
3263 int base = data->BaseAddress;
3264 int tmp, ret;
3265
3266 if (bit != SDA) {
3267 nsp32_msg(KERN_ERR, "return value is not appropriate");
3268 return 0;
3269 }
3270
3271
3272 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL) & bit;
3273
3274 if (tmp == 0) {
3275 ret = 0;
3276 } else {
3277 ret = 1;
3278 }
3279
3280 udelay(10);
3281
3282 return ret;
3283}
3284
3285static void nsp32_prom_start (nsp32_hw_data *data)
3286{
3287
3288 nsp32_prom_set(data, SCL, 1);
3289 nsp32_prom_set(data, SDA, 1);
3290 nsp32_prom_set(data, ENA, 1);
3291 nsp32_prom_set(data, SDA, 0);
3292
3293 nsp32_prom_set(data, SCL, 0);
3294}
3295
3296static void nsp32_prom_stop (nsp32_hw_data *data)
3297{
3298
3299 nsp32_prom_set(data, SCL, 1);
3300 nsp32_prom_set(data, SDA, 0);
3301 nsp32_prom_set(data, ENA, 1);
3302 nsp32_prom_set(data, SDA, 1);
3303 nsp32_prom_set(data, SCL, 0);
3304}
3305
3306static void nsp32_prom_write_bit(nsp32_hw_data *data, int val)
3307{
3308
3309 nsp32_prom_set(data, SDA, val);
3310 nsp32_prom_set(data, SCL, 1 );
3311 nsp32_prom_set(data, SCL, 0 );
3312}
3313
3314static int nsp32_prom_read_bit(nsp32_hw_data *data)
3315{
3316 int val;
3317
3318
3319 nsp32_prom_set(data, ENA, 0);
3320 nsp32_prom_set(data, SCL, 1);
3321
3322 val = nsp32_prom_get(data, SDA);
3323
3324 nsp32_prom_set(data, SCL, 0);
3325 nsp32_prom_set(data, ENA, 1);
3326
3327 return val;
3328}
3329
3330
3331
3332
3333
3334#ifdef CONFIG_PM
3335
3336
3337static int nsp32_suspend(struct pci_dev *pdev, pm_message_t state)
3338{
3339 struct Scsi_Host *host = pci_get_drvdata(pdev);
3340
3341 nsp32_msg(KERN_INFO, "pci-suspend: pdev=0x%p, state=%ld, slot=%s, host=0x%p", pdev, state, pci_name(pdev), host);
3342
3343 pci_save_state (pdev);
3344 pci_disable_device (pdev);
3345 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3346
3347 return 0;
3348}
3349
3350
3351static int nsp32_resume(struct pci_dev *pdev)
3352{
3353 struct Scsi_Host *host = pci_get_drvdata(pdev);
3354 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
3355 unsigned short reg;
3356
3357 nsp32_msg(KERN_INFO, "pci-resume: pdev=0x%p, slot=%s, host=0x%p", pdev, pci_name(pdev), host);
3358
3359 pci_set_power_state(pdev, PCI_D0);
3360 pci_enable_wake (pdev, PCI_D0, 0);
3361 pci_restore_state (pdev);
3362
3363 reg = nsp32_read2(data->BaseAddress, INDEX_REG);
3364
3365 nsp32_msg(KERN_INFO, "io=0x%x reg=0x%x", data->BaseAddress, reg);
3366
3367 if (reg == 0xffff) {
3368 nsp32_msg(KERN_INFO, "missing device. abort resume.");
3369 return 0;
3370 }
3371
3372 nsp32hw_init (data);
3373 nsp32_do_bus_reset(data);
3374
3375 nsp32_msg(KERN_INFO, "resume success");
3376
3377 return 0;
3378}
3379
3380#endif
3381
3382
3383
3384
3385static int __devinit nsp32_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3386{
3387 int ret;
3388 nsp32_hw_data *data = &nsp32_data_base;
3389
3390 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3391
3392 ret = pci_enable_device(pdev);
3393 if (ret) {
3394 nsp32_msg(KERN_ERR, "failed to enable pci device");
3395 return ret;
3396 }
3397
3398 data->Pci = pdev;
3399 data->pci_devid = id;
3400 data->IrqNumber = pdev->irq;
3401 data->BaseAddress = pci_resource_start(pdev, 0);
3402 data->NumAddress = pci_resource_len (pdev, 0);
3403 data->MmioAddress = pci_ioremap_bar(pdev, 1);
3404 data->MmioLength = pci_resource_len (pdev, 1);
3405
3406 pci_set_master(pdev);
3407
3408 ret = nsp32_detect(pdev);
3409
3410 nsp32_msg(KERN_INFO, "irq: %i mmio: %p+0x%lx slot: %s model: %s",
3411 pdev->irq,
3412 data->MmioAddress, data->MmioLength,
3413 pci_name(pdev),
3414 nsp32_model[id->driver_data]);
3415
3416 nsp32_dbg(NSP32_DEBUG_REGISTER, "exit %d", ret);
3417
3418 return ret;
3419}
3420
3421static void __devexit nsp32_remove(struct pci_dev *pdev)
3422{
3423 struct Scsi_Host *host = pci_get_drvdata(pdev);
3424
3425 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3426
3427 scsi_remove_host(host);
3428
3429 nsp32_release(host);
3430
3431 scsi_host_put(host);
3432}
3433
3434static struct pci_driver nsp32_driver = {
3435 .name = "nsp32",
3436 .id_table = nsp32_pci_table,
3437 .probe = nsp32_probe,
3438 .remove = __devexit_p(nsp32_remove),
3439#ifdef CONFIG_PM
3440 .suspend = nsp32_suspend,
3441 .resume = nsp32_resume,
3442#endif
3443};
3444
3445
3446
3447
3448static int __init init_nsp32(void) {
3449 nsp32_msg(KERN_INFO, "loading...");
3450 return pci_register_driver(&nsp32_driver);
3451}
3452
3453static void __exit exit_nsp32(void) {
3454 nsp32_msg(KERN_INFO, "unloading...");
3455 pci_unregister_driver(&nsp32_driver);
3456}
3457
3458module_init(init_nsp32);
3459module_exit(exit_nsp32);
3460
3461
3462