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9#include <linux/module.h>
10#include <linux/mutex.h>
11#include <linux/delay.h>
12
13#include <asm/octeon/octeon.h>
14#include <asm/octeon/cvmx-uctlx-defs.h>
15
16static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
17
18static int octeon2_usb_clock_start_cnt;
19
20void octeon2_usb_clocks_start(void)
21{
22 u64 div;
23 union cvmx_uctlx_if_ena if_ena;
24 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
25 union cvmx_uctlx_uphy_ctl_status uphy_ctl_status;
26 union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
27 int i;
28 unsigned long io_clk_64_to_ns;
29
30
31 mutex_lock(&octeon2_usb_clocks_mutex);
32
33 octeon2_usb_clock_start_cnt++;
34 if (octeon2_usb_clock_start_cnt != 1)
35 goto exit;
36
37 io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
38
39
40
41
42
43
44
45 if_ena.u64 = 0;
46 if_ena.s.en = 1;
47 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
48
49
50 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
51
52
53
54
55
56 if (clk_rst_ctl.s.hrst)
57 goto end_clock;
58
59 clk_rst_ctl.s.p_por = 1;
60 clk_rst_ctl.s.hrst = 0;
61 clk_rst_ctl.s.p_prst = 0;
62 clk_rst_ctl.s.h_clkdiv_rst = 0;
63 clk_rst_ctl.s.o_clkdiv_rst = 0;
64 clk_rst_ctl.s.h_clkdiv_en = 0;
65 clk_rst_ctl.s.o_clkdiv_en = 0;
66 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
67
68
69
70 clk_rst_ctl.s.p_refclk_sel = 0;
71 clk_rst_ctl.s.p_refclk_div = 0;
72 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
73
74
75 div = octeon_get_io_clock_rate() / 130000000ull;
76
77 switch (div) {
78 case 0:
79 div = 1;
80 break;
81 case 1:
82 case 2:
83 case 3:
84 case 4:
85 break;
86 case 5:
87 div = 4;
88 break;
89 case 6:
90 case 7:
91 div = 6;
92 break;
93 case 8:
94 case 9:
95 case 10:
96 case 11:
97 div = 8;
98 break;
99 default:
100 div = 12;
101 break;
102 }
103 clk_rst_ctl.s.h_div = div;
104 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
105
106 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
107 clk_rst_ctl.s.h_clkdiv_en = 1;
108 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
109
110 clk_rst_ctl.s.h_clkdiv_rst = 1;
111 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
112
113
114 ndelay(io_clk_64_to_ns);
115
116
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118
119
120 clk_rst_ctl.s.p_por = 0;
121 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
122
123
124 mdelay(1);
125
126
127
128
129
130 uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0));
131 uphy_ctl_status.s.ate_reset = 1;
132 cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
133
134
135 ndelay(10);
136
137
138 uphy_ctl_status.s.ate_reset = 0;
139 cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
140
141
142
143
144
145 ndelay(20);
146
147
148
149 clk_rst_ctl.s.o_clkdiv_rst = 1;
150 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
151
152
153 clk_rst_ctl.s.o_clkdiv_en = 1;
154 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
155
156
157 ndelay(io_clk_64_to_ns);
158
159
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161
162
163 clk_rst_ctl.s.p_prst = 1;
164 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
165
166
167 udelay(1);
168
169
170 clk_rst_ctl.s.hrst = 1;
171 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
172
173end_clock:
174
175
176 for (i = 0; i <= 1; i++) {
177 port_ctl_status.u64 =
178 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
179
180 port_ctl_status.s.txvreftune = 15;
181 port_ctl_status.s.txrisetune = 1;
182 port_ctl_status.s.txpreemphasistune = 1;
183 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
184 port_ctl_status.u64);
185 }
186
187
188 cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
189exit:
190 mutex_unlock(&octeon2_usb_clocks_mutex);
191}
192EXPORT_SYMBOL(octeon2_usb_clocks_start);
193
194void octeon2_usb_clocks_stop(void)
195{
196 mutex_lock(&octeon2_usb_clocks_mutex);
197 octeon2_usb_clock_start_cnt--;
198 mutex_unlock(&octeon2_usb_clocks_mutex);
199}
200EXPORT_SYMBOL(octeon2_usb_clocks_stop);
201