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32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/errno.h>
35#include <linux/string.h>
36#include <linux/mm.h>
37#include <linux/slab.h>
38#include <linux/delay.h>
39#include <linux/fb.h>
40#include <linux/init.h>
41#include <linux/pci.h>
42#include <linux/backlight.h>
43#include <linux/bitrev.h>
44#ifdef CONFIG_MTRR
45#include <asm/mtrr.h>
46#endif
47#ifdef CONFIG_PPC_OF
48#include <asm/prom.h>
49#include <asm/pci-bridge.h>
50#endif
51#ifdef CONFIG_PMAC_BACKLIGHT
52#include <asm/machdep.h>
53#include <asm/backlight.h>
54#endif
55
56#include "rivafb.h"
57#include "nvreg.h"
58
59
60#define RIVAFB_VERSION "0.9.5b"
61
62
63
64
65
66
67#ifdef CONFIG_FB_RIVA_DEBUG
68#define NVTRACE printk
69#else
70#define NVTRACE if(0) printk
71#endif
72
73#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__)
74#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__)
75
76#ifdef CONFIG_FB_RIVA_DEBUG
77#define assert(expr) \
78 if(!(expr)) { \
79 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
80 #expr,__FILE__,__func__,__LINE__); \
81 BUG(); \
82 }
83#else
84#define assert(expr)
85#endif
86
87#define PFX "rivafb: "
88
89
90#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
91#define SetBit(n) (1<<(n))
92#define Set8Bits(value) ((value)&0xff)
93
94
95#define MAX_CURS 32
96
97
98
99
100
101
102
103static int rivafb_blank(int blank, struct fb_info *info);
104
105
106
107
108
109
110
111static struct pci_device_id rivafb_pci_tbl[] = {
112 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
114 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
116 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
148 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
150 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
152
153 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
157 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
193 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
195 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
197 { 0, }
198};
199MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
200
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207
208static int flatpanel __devinitdata = -1;
209static int forceCRTC __devinitdata = -1;
210static bool noaccel __devinitdata = 0;
211#ifdef CONFIG_MTRR
212static bool nomtrr __devinitdata = 0;
213#endif
214#ifdef CONFIG_PMAC_BACKLIGHT
215static int backlight __devinitdata = 1;
216#else
217static int backlight __devinitdata = 0;
218#endif
219
220static char *mode_option __devinitdata = NULL;
221static bool strictmode = 0;
222
223static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
224 .type = FB_TYPE_PACKED_PIXELS,
225 .xpanstep = 1,
226 .ypanstep = 1,
227};
228
229static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
230 .xres = 640,
231 .yres = 480,
232 .xres_virtual = 640,
233 .yres_virtual = 480,
234 .bits_per_pixel = 8,
235 .red = {0, 8, 0},
236 .green = {0, 8, 0},
237 .blue = {0, 8, 0},
238 .transp = {0, 0, 0},
239 .activate = FB_ACTIVATE_NOW,
240 .height = -1,
241 .width = -1,
242 .pixclock = 39721,
243 .left_margin = 40,
244 .right_margin = 24,
245 .upper_margin = 32,
246 .lower_margin = 11,
247 .hsync_len = 96,
248 .vsync_len = 2,
249 .vmode = FB_VMODE_NONINTERLACED
250};
251
252
253static const struct riva_regs reg_template = {
254 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
255 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
256 0x41, 0x01, 0x0F, 0x00, 0x00},
257 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
258 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3,
260 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
262 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
263 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
264 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
265 0x00,
266 },
267 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
268 0xFF},
269 {0x03, 0x01, 0x0F, 0x00, 0x0E},
270 0xEB
271};
272
273
274
275
276#ifdef CONFIG_FB_RIVA_BACKLIGHT
277
278
279
280#define MIN_LEVEL 0x158
281#define MAX_LEVEL 0x534
282#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
283
284static int riva_bl_get_level_brightness(struct riva_par *par,
285 int level)
286{
287 struct fb_info *info = pci_get_drvdata(par->pdev);
288 int nlevel;
289
290
291
292 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
293
294 if (nlevel < 0)
295 nlevel = 0;
296 else if (nlevel < MIN_LEVEL)
297 nlevel = MIN_LEVEL;
298 else if (nlevel > MAX_LEVEL)
299 nlevel = MAX_LEVEL;
300
301 return nlevel;
302}
303
304static int riva_bl_update_status(struct backlight_device *bd)
305{
306 struct riva_par *par = bl_get_data(bd);
307 U032 tmp_pcrt, tmp_pmc;
308 int level;
309
310 if (bd->props.power != FB_BLANK_UNBLANK ||
311 bd->props.fb_blank != FB_BLANK_UNBLANK)
312 level = 0;
313 else
314 level = bd->props.brightness;
315
316 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
317 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC;
318 if(level > 0) {
319 tmp_pcrt |= 0x1;
320 tmp_pmc |= (1 << 31);
321 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16;
322 }
323 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt);
324 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc);
325
326 return 0;
327}
328
329static int riva_bl_get_brightness(struct backlight_device *bd)
330{
331 return bd->props.brightness;
332}
333
334static const struct backlight_ops riva_bl_ops = {
335 .get_brightness = riva_bl_get_brightness,
336 .update_status = riva_bl_update_status,
337};
338
339static void riva_bl_init(struct riva_par *par)
340{
341 struct backlight_properties props;
342 struct fb_info *info = pci_get_drvdata(par->pdev);
343 struct backlight_device *bd;
344 char name[12];
345
346 if (!par->FlatPanel)
347 return;
348
349#ifdef CONFIG_PMAC_BACKLIGHT
350 if (!machine_is(powermac) ||
351 !pmac_has_backlight_type("mnca"))
352 return;
353#endif
354
355 snprintf(name, sizeof(name), "rivabl%d", info->node);
356
357 memset(&props, 0, sizeof(struct backlight_properties));
358 props.type = BACKLIGHT_RAW;
359 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
360 bd = backlight_device_register(name, info->dev, par, &riva_bl_ops,
361 &props);
362 if (IS_ERR(bd)) {
363 info->bl_dev = NULL;
364 printk(KERN_WARNING "riva: Backlight registration failed\n");
365 goto error;
366 }
367
368 info->bl_dev = bd;
369 fb_bl_default_curve(info, 0,
370 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL,
371 FB_BACKLIGHT_MAX);
372
373 bd->props.brightness = bd->props.max_brightness;
374 bd->props.power = FB_BLANK_UNBLANK;
375 backlight_update_status(bd);
376
377 printk("riva: Backlight initialized (%s)\n", name);
378
379 return;
380
381error:
382 return;
383}
384
385static void riva_bl_exit(struct fb_info *info)
386{
387 struct backlight_device *bd = info->bl_dev;
388
389 backlight_device_unregister(bd);
390 printk("riva: Backlight unloaded\n");
391}
392#else
393static inline void riva_bl_init(struct riva_par *par) {}
394static inline void riva_bl_exit(struct fb_info *info) {}
395#endif
396
397
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401
402
403static inline void CRTCout(struct riva_par *par, unsigned char index,
404 unsigned char val)
405{
406 VGA_WR08(par->riva.PCIO, 0x3d4, index);
407 VGA_WR08(par->riva.PCIO, 0x3d5, val);
408}
409
410static inline unsigned char CRTCin(struct riva_par *par,
411 unsigned char index)
412{
413 VGA_WR08(par->riva.PCIO, 0x3d4, index);
414 return (VGA_RD08(par->riva.PCIO, 0x3d5));
415}
416
417static inline void GRAout(struct riva_par *par, unsigned char index,
418 unsigned char val)
419{
420 VGA_WR08(par->riva.PVIO, 0x3ce, index);
421 VGA_WR08(par->riva.PVIO, 0x3cf, val);
422}
423
424static inline unsigned char GRAin(struct riva_par *par,
425 unsigned char index)
426{
427 VGA_WR08(par->riva.PVIO, 0x3ce, index);
428 return (VGA_RD08(par->riva.PVIO, 0x3cf));
429}
430
431static inline void SEQout(struct riva_par *par, unsigned char index,
432 unsigned char val)
433{
434 VGA_WR08(par->riva.PVIO, 0x3c4, index);
435 VGA_WR08(par->riva.PVIO, 0x3c5, val);
436}
437
438static inline unsigned char SEQin(struct riva_par *par,
439 unsigned char index)
440{
441 VGA_WR08(par->riva.PVIO, 0x3c4, index);
442 return (VGA_RD08(par->riva.PVIO, 0x3c5));
443}
444
445static inline void ATTRout(struct riva_par *par, unsigned char index,
446 unsigned char val)
447{
448 VGA_WR08(par->riva.PCIO, 0x3c0, index);
449 VGA_WR08(par->riva.PCIO, 0x3c0, val);
450}
451
452static inline unsigned char ATTRin(struct riva_par *par,
453 unsigned char index)
454{
455 VGA_WR08(par->riva.PCIO, 0x3c0, index);
456 return (VGA_RD08(par->riva.PCIO, 0x3c1));
457}
458
459static inline void MISCout(struct riva_par *par, unsigned char val)
460{
461 VGA_WR08(par->riva.PVIO, 0x3c2, val);
462}
463
464static inline unsigned char MISCin(struct riva_par *par)
465{
466 return (VGA_RD08(par->riva.PVIO, 0x3cc));
467}
468
469static inline void reverse_order(u32 *l)
470{
471 u8 *a = (u8 *)l;
472 a[0] = bitrev8(a[0]);
473 a[1] = bitrev8(a[1]);
474 a[2] = bitrev8(a[2]);
475 a[3] = bitrev8(a[3]);
476}
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502static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
503 u16 bg, u16 fg, u32 w, u32 h)
504{
505 int i, j, k = 0;
506 u32 b, tmp;
507 u32 *data = (u32 *)data8;
508 bg = le16_to_cpu(bg);
509 fg = le16_to_cpu(fg);
510
511 w = (w + 1) & ~1;
512
513 for (i = 0; i < h; i++) {
514 b = *data++;
515 reverse_order(&b);
516
517 for (j = 0; j < w/2; j++) {
518 tmp = 0;
519#if defined (__BIG_ENDIAN)
520 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
521 b <<= 1;
522 tmp |= (b & (1 << 31)) ? fg : bg;
523 b <<= 1;
524#else
525 tmp = (b & 1) ? fg : bg;
526 b >>= 1;
527 tmp |= (b & 1) ? fg << 16 : bg << 16;
528 b >>= 1;
529#endif
530 writel(tmp, &par->riva.CURSOR[k++]);
531 }
532 k += (MAX_CURS - w)/2;
533 }
534}
535
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555
556static void riva_wclut(RIVA_HW_INST *chip,
557 unsigned char regnum, unsigned char red,
558 unsigned char green, unsigned char blue)
559{
560 VGA_WR08(chip->PDIO, 0x3c8, regnum);
561 VGA_WR08(chip->PDIO, 0x3c9, red);
562 VGA_WR08(chip->PDIO, 0x3c9, green);
563 VGA_WR08(chip->PDIO, 0x3c9, blue);
564}
565
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579
580static void riva_rclut(RIVA_HW_INST *chip,
581 unsigned char regnum, unsigned char *red,
582 unsigned char *green, unsigned char *blue)
583{
584
585 VGA_WR08(chip->PDIO, 0x3c7, regnum);
586 *red = VGA_RD08(chip->PDIO, 0x3c9);
587 *green = VGA_RD08(chip->PDIO, 0x3c9);
588 *blue = VGA_RD08(chip->PDIO, 0x3c9);
589}
590
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602
603static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
604{
605 int i;
606
607 NVTRACE_ENTER();
608 par->riva.LockUnlock(&par->riva, 0);
609
610 par->riva.UnloadStateExt(&par->riva, ®s->ext);
611
612 regs->misc_output = MISCin(par);
613
614 for (i = 0; i < NUM_CRT_REGS; i++)
615 regs->crtc[i] = CRTCin(par, i);
616
617 for (i = 0; i < NUM_ATC_REGS; i++)
618 regs->attr[i] = ATTRin(par, i);
619
620 for (i = 0; i < NUM_GRC_REGS; i++)
621 regs->gra[i] = GRAin(par, i);
622
623 for (i = 0; i < NUM_SEQ_REGS; i++)
624 regs->seq[i] = SEQin(par, i);
625 NVTRACE_LEAVE();
626}
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641
642static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
643{
644 RIVA_HW_STATE *state = ®s->ext;
645 int i;
646
647 NVTRACE_ENTER();
648 CRTCout(par, 0x11, 0x00);
649
650 par->riva.LockUnlock(&par->riva, 0);
651
652 par->riva.LoadStateExt(&par->riva, state);
653
654 MISCout(par, regs->misc_output);
655
656 for (i = 0; i < NUM_CRT_REGS; i++) {
657 switch (i) {
658 case 0x19:
659 case 0x20 ... 0x40:
660 break;
661 default:
662 CRTCout(par, i, regs->crtc[i]);
663 }
664 }
665
666 for (i = 0; i < NUM_ATC_REGS; i++)
667 ATTRout(par, i, regs->attr[i]);
668
669 for (i = 0; i < NUM_GRC_REGS; i++)
670 GRAout(par, i, regs->gra[i]);
671
672 for (i = 0; i < NUM_SEQ_REGS; i++)
673 SEQout(par, i, regs->seq[i]);
674 NVTRACE_LEAVE();
675}
676
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686
687static int riva_load_video_mode(struct fb_info *info)
688{
689 int bpp, width, hDisplaySize, hDisplay, hStart,
690 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
691 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
692 int rc;
693 struct riva_par *par = info->par;
694 struct riva_regs newmode;
695
696 NVTRACE_ENTER();
697
698 rivafb_blank(FB_BLANK_NORMAL, info);
699
700 bpp = info->var.bits_per_pixel;
701 if (bpp == 16 && info->var.green.length == 5)
702 bpp = 15;
703 width = info->var.xres_virtual;
704 hDisplaySize = info->var.xres;
705 hDisplay = (hDisplaySize / 8) - 1;
706 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
707 hEnd = (hDisplaySize + info->var.right_margin +
708 info->var.hsync_len) / 8 - 1;
709 hTotal = (hDisplaySize + info->var.right_margin +
710 info->var.hsync_len + info->var.left_margin) / 8 - 5;
711 hBlankStart = hDisplay;
712 hBlankEnd = hTotal + 4;
713
714 height = info->var.yres_virtual;
715 vDisplay = info->var.yres - 1;
716 vStart = info->var.yres + info->var.lower_margin - 1;
717 vEnd = info->var.yres + info->var.lower_margin +
718 info->var.vsync_len - 1;
719 vTotal = info->var.yres + info->var.lower_margin +
720 info->var.vsync_len + info->var.upper_margin + 2;
721 vBlankStart = vDisplay;
722 vBlankEnd = vTotal + 1;
723 dotClock = 1000000000 / info->var.pixclock;
724
725 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
726
727 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
728 vTotal |= 1;
729
730 if (par->FlatPanel) {
731 vStart = vTotal - 3;
732 vEnd = vTotal - 2;
733 vBlankStart = vStart;
734 hStart = hTotal - 3;
735 hEnd = hTotal - 2;
736 hBlankEnd = hTotal + 4;
737 }
738
739 newmode.crtc[0x0] = Set8Bits (hTotal);
740 newmode.crtc[0x1] = Set8Bits (hDisplay);
741 newmode.crtc[0x2] = Set8Bits (hBlankStart);
742 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
743 newmode.crtc[0x4] = Set8Bits (hStart);
744 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
745 | SetBitField (hEnd, 4: 0, 4:0);
746 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
747 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
748 | SetBitField (vDisplay, 8: 8, 1:1)
749 | SetBitField (vStart, 8: 8, 2:2)
750 | SetBitField (vBlankStart, 8: 8, 3:3)
751 | SetBit (4)
752 | SetBitField (vTotal, 9: 9, 5:5)
753 | SetBitField (vDisplay, 9: 9, 6:6)
754 | SetBitField (vStart, 9: 9, 7:7);
755 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
756 | SetBit (6);
757 newmode.crtc[0x10] = Set8Bits (vStart);
758 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
759 | SetBit (5);
760 newmode.crtc[0x12] = Set8Bits (vDisplay);
761 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
762 newmode.crtc[0x15] = Set8Bits (vBlankStart);
763 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
764
765 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
766 | SetBitField(vBlankStart,10:10,3:3)
767 | SetBitField(vStart,10:10,2:2)
768 | SetBitField(vDisplay,10:10,1:1)
769 | SetBitField(vTotal,10:10,0:0);
770 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
771 | SetBitField(hDisplay,8:8,1:1)
772 | SetBitField(hBlankStart,8:8,2:2)
773 | SetBitField(hStart,8:8,3:3);
774 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
775 | SetBitField(vDisplay,11:11,2:2)
776 | SetBitField(vStart,11:11,4:4)
777 | SetBitField(vBlankStart,11:11,6:6);
778
779 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
780 int tmp = (hTotal >> 1) & ~1;
781 newmode.ext.interlace = Set8Bits(tmp);
782 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
783 } else
784 newmode.ext.interlace = 0xff;
785
786 if (par->riva.Architecture >= NV_ARCH_10)
787 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
788
789 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
790 newmode.misc_output &= ~0x40;
791 else
792 newmode.misc_output |= 0x40;
793 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
794 newmode.misc_output &= ~0x80;
795 else
796 newmode.misc_output |= 0x80;
797
798 rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width,
799 hDisplaySize, height, dotClock);
800 if (rc)
801 goto out;
802
803 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
804 0xfff000ff;
805 if (par->FlatPanel == 1) {
806 newmode.ext.pixel |= (1 << 7);
807 newmode.ext.scale |= (1 << 8);
808 }
809 if (par->SecondCRTC) {
810 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
811 ~0x00001000;
812 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
813 0x00001000;
814 newmode.ext.crtcOwner = 3;
815 newmode.ext.pllsel |= 0x20000800;
816 newmode.ext.vpll2 = newmode.ext.vpll;
817 } else if (par->riva.twoHeads) {
818 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
819 0x00001000;
820 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
821 ~0x00001000;
822 newmode.ext.crtcOwner = 0;
823 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
824 }
825 if (par->FlatPanel == 1) {
826 newmode.ext.pixel |= (1 << 7);
827 newmode.ext.scale |= (1 << 8);
828 }
829 newmode.ext.cursorConfig = 0x02000100;
830 par->current_state = newmode;
831 riva_load_state(par, &par->current_state);
832 par->riva.LockUnlock(&par->riva, 0);
833
834out:
835 rivafb_blank(FB_BLANK_UNBLANK, info);
836 NVTRACE_LEAVE();
837
838 return rc;
839}
840
841static void riva_update_var(struct fb_var_screeninfo *var,
842 const struct fb_videomode *modedb)
843{
844 NVTRACE_ENTER();
845 var->xres = var->xres_virtual = modedb->xres;
846 var->yres = modedb->yres;
847 if (var->yres_virtual < var->yres)
848 var->yres_virtual = var->yres;
849 var->xoffset = var->yoffset = 0;
850 var->pixclock = modedb->pixclock;
851 var->left_margin = modedb->left_margin;
852 var->right_margin = modedb->right_margin;
853 var->upper_margin = modedb->upper_margin;
854 var->lower_margin = modedb->lower_margin;
855 var->hsync_len = modedb->hsync_len;
856 var->vsync_len = modedb->vsync_len;
857 var->sync = modedb->sync;
858 var->vmode = modedb->vmode;
859 NVTRACE_LEAVE();
860}
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879static int rivafb_do_maximize(struct fb_info *info,
880 struct fb_var_screeninfo *var,
881 int nom, int den)
882{
883 static struct {
884 int xres, yres;
885 } modes[] = {
886 {1600, 1280},
887 {1280, 1024},
888 {1024, 768},
889 {800, 600},
890 {640, 480},
891 {-1, -1}
892 };
893 int i;
894
895 NVTRACE_ENTER();
896
897 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
898 printk(KERN_WARNING PFX
899 "using maximum available virtual resolution\n");
900 for (i = 0; modes[i].xres != -1; i++) {
901 if (modes[i].xres * nom / den * modes[i].yres <
902 info->fix.smem_len)
903 break;
904 }
905 if (modes[i].xres == -1) {
906 printk(KERN_ERR PFX
907 "could not find a virtual resolution that fits into video memory!!\n");
908 NVTRACE("EXIT - EINVAL error\n");
909 return -EINVAL;
910 }
911 var->xres_virtual = modes[i].xres;
912 var->yres_virtual = modes[i].yres;
913
914 printk(KERN_INFO PFX
915 "virtual resolution set to maximum of %dx%d\n",
916 var->xres_virtual, var->yres_virtual);
917 } else if (var->xres_virtual == -1) {
918 var->xres_virtual = (info->fix.smem_len * den /
919 (nom * var->yres_virtual)) & ~15;
920 printk(KERN_WARNING PFX
921 "setting virtual X resolution to %d\n", var->xres_virtual);
922 } else if (var->yres_virtual == -1) {
923 var->xres_virtual = (var->xres_virtual + 15) & ~15;
924 var->yres_virtual = info->fix.smem_len * den /
925 (nom * var->xres_virtual);
926 printk(KERN_WARNING PFX
927 "setting virtual Y resolution to %d\n", var->yres_virtual);
928 } else {
929 var->xres_virtual = (var->xres_virtual + 15) & ~15;
930 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
931 printk(KERN_ERR PFX
932 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
933 var->xres, var->yres, var->bits_per_pixel);
934 NVTRACE("EXIT - EINVAL error\n");
935 return -EINVAL;
936 }
937 }
938
939 if (var->xres_virtual * nom / den >= 8192) {
940 printk(KERN_WARNING PFX
941 "virtual X resolution (%d) is too high, lowering to %d\n",
942 var->xres_virtual, 8192 * den / nom - 16);
943 var->xres_virtual = 8192 * den / nom - 16;
944 }
945
946 if (var->xres_virtual < var->xres) {
947 printk(KERN_ERR PFX
948 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
949 return -EINVAL;
950 }
951
952 if (var->yres_virtual < var->yres) {
953 printk(KERN_ERR PFX
954 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
955 return -EINVAL;
956 }
957 if (var->yres_virtual > 0x7fff/nom)
958 var->yres_virtual = 0x7fff/nom;
959 if (var->xres_virtual > 0x7fff/nom)
960 var->xres_virtual = 0x7fff/nom;
961 NVTRACE_LEAVE();
962 return 0;
963}
964
965static void
966riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
967{
968 RIVA_FIFO_FREE(par->riva, Patt, 4);
969 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
970 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
971 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
972 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
973}
974
975
976static inline void wait_for_idle(struct riva_par *par)
977{
978 while (par->riva.Busy(&par->riva));
979}
980
981
982
983
984static void
985riva_set_rop_solid(struct riva_par *par, int rop)
986{
987 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
988 RIVA_FIFO_FREE(par->riva, Rop, 1);
989 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
990
991}
992
993static void riva_setup_accel(struct fb_info *info)
994{
995 struct riva_par *par = info->par;
996
997 RIVA_FIFO_FREE(par->riva, Clip, 2);
998 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
999 NV_WR32(&par->riva.Clip->WidthHeight, 0,
1000 (info->var.xres_virtual & 0xffff) |
1001 (info->var.yres_virtual << 16));
1002 riva_set_rop_solid(par, 0xcc);
1003 wait_for_idle(par);
1004}
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1020{
1021 int rc = 256;
1022
1023 switch (var->green.length) {
1024 case 8:
1025 rc = 256;
1026 break;
1027 case 5:
1028 rc = 32;
1029 break;
1030 case 6:
1031 rc = 64;
1032 break;
1033 default:
1034
1035 break;
1036 }
1037 return rc;
1038}
1039
1040
1041
1042
1043
1044
1045
1046static int rivafb_open(struct fb_info *info, int user)
1047{
1048 struct riva_par *par = info->par;
1049
1050 NVTRACE_ENTER();
1051 mutex_lock(&par->open_lock);
1052 if (!par->ref_count) {
1053#ifdef CONFIG_X86
1054 memset(&par->state, 0, sizeof(struct vgastate));
1055 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1056
1057 if (par->riva.Architecture == NV_ARCH_03)
1058 par->state.flags |= VGA_SAVE_CMAP;
1059 save_vga(&par->state);
1060#endif
1061
1062 CRTCout(par, 0x11, 0xFF);
1063 par->riva.LockUnlock(&par->riva, 0);
1064
1065 riva_save_state(par, &par->initial_state);
1066 }
1067 par->ref_count++;
1068 mutex_unlock(&par->open_lock);
1069 NVTRACE_LEAVE();
1070 return 0;
1071}
1072
1073static int rivafb_release(struct fb_info *info, int user)
1074{
1075 struct riva_par *par = info->par;
1076
1077 NVTRACE_ENTER();
1078 mutex_lock(&par->open_lock);
1079 if (!par->ref_count) {
1080 mutex_unlock(&par->open_lock);
1081 return -EINVAL;
1082 }
1083 if (par->ref_count == 1) {
1084 par->riva.LockUnlock(&par->riva, 0);
1085 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1086 riva_load_state(par, &par->initial_state);
1087#ifdef CONFIG_X86
1088 restore_vga(&par->state);
1089#endif
1090 par->riva.LockUnlock(&par->riva, 1);
1091 }
1092 par->ref_count--;
1093 mutex_unlock(&par->open_lock);
1094 NVTRACE_LEAVE();
1095 return 0;
1096}
1097
1098static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1099{
1100 const struct fb_videomode *mode;
1101 struct riva_par *par = info->par;
1102 int nom, den;
1103 int mode_valid = 0;
1104
1105 NVTRACE_ENTER();
1106 switch (var->bits_per_pixel) {
1107 case 1 ... 8:
1108 var->red.offset = var->green.offset = var->blue.offset = 0;
1109 var->red.length = var->green.length = var->blue.length = 8;
1110 var->bits_per_pixel = 8;
1111 nom = den = 1;
1112 break;
1113 case 9 ... 15:
1114 var->green.length = 5;
1115
1116 case 16:
1117 var->bits_per_pixel = 16;
1118
1119 if (par->riva.Architecture == NV_ARCH_03)
1120 var->green.length = 5;
1121 if (var->green.length == 5) {
1122
1123 var->red.offset = 10;
1124 var->green.offset = 5;
1125 var->blue.offset = 0;
1126 var->red.length = 5;
1127 var->green.length = 5;
1128 var->blue.length = 5;
1129 } else {
1130
1131 var->red.offset = 11;
1132 var->green.offset = 5;
1133 var->blue.offset = 0;
1134 var->red.length = 5;
1135 var->green.length = 6;
1136 var->blue.length = 5;
1137 }
1138 nom = 2;
1139 den = 1;
1140 break;
1141 case 17 ... 32:
1142 var->red.length = var->green.length = var->blue.length = 8;
1143 var->bits_per_pixel = 32;
1144 var->red.offset = 16;
1145 var->green.offset = 8;
1146 var->blue.offset = 0;
1147 nom = 4;
1148 den = 1;
1149 break;
1150 default:
1151 printk(KERN_ERR PFX
1152 "mode %dx%dx%d rejected...color depth not supported.\n",
1153 var->xres, var->yres, var->bits_per_pixel);
1154 NVTRACE("EXIT, returning -EINVAL\n");
1155 return -EINVAL;
1156 }
1157
1158 if (!strictmode) {
1159 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1160 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1161 mode_valid = 1;
1162 }
1163
1164
1165 if (!mode_valid && info->monspecs.gtf) {
1166 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1167 mode_valid = 1;
1168 }
1169
1170 if (!mode_valid) {
1171 mode = fb_find_best_mode(var, &info->modelist);
1172 if (mode) {
1173 riva_update_var(var, mode);
1174 mode_valid = 1;
1175 }
1176 }
1177
1178 if (!mode_valid && info->monspecs.modedb_len)
1179 return -EINVAL;
1180
1181 if (var->xres_virtual < var->xres)
1182 var->xres_virtual = var->xres;
1183 if (var->yres_virtual <= var->yres)
1184 var->yres_virtual = -1;
1185 if (rivafb_do_maximize(info, var, nom, den) < 0)
1186 return -EINVAL;
1187
1188 if (var->xoffset < 0)
1189 var->xoffset = 0;
1190 if (var->yoffset < 0)
1191 var->yoffset = 0;
1192
1193
1194 if (var->xoffset > var->xres_virtual - var->xres)
1195 var->xoffset = var->xres_virtual - var->xres - 1;
1196
1197 if (var->yoffset > var->yres_virtual - var->yres)
1198 var->yoffset = var->yres_virtual - var->yres - 1;
1199
1200 var->red.msb_right =
1201 var->green.msb_right =
1202 var->blue.msb_right =
1203 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1204 NVTRACE_LEAVE();
1205 return 0;
1206}
1207
1208static int rivafb_set_par(struct fb_info *info)
1209{
1210 struct riva_par *par = info->par;
1211 int rc = 0;
1212
1213 NVTRACE_ENTER();
1214
1215 CRTCout(par, 0x11, 0xFF);
1216 par->riva.LockUnlock(&par->riva, 0);
1217 rc = riva_load_video_mode(info);
1218 if (rc)
1219 goto out;
1220 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1221 riva_setup_accel(info);
1222
1223 par->cursor_reset = 1;
1224 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1225 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1226 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1227
1228 if (info->flags & FBINFO_HWACCEL_DISABLED)
1229 info->pixmap.scan_align = 1;
1230 else
1231 info->pixmap.scan_align = 4;
1232
1233out:
1234 NVTRACE_LEAVE();
1235 return rc;
1236}
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251static int rivafb_pan_display(struct fb_var_screeninfo *var,
1252 struct fb_info *info)
1253{
1254 struct riva_par *par = info->par;
1255 unsigned int base;
1256
1257 NVTRACE_ENTER();
1258 base = var->yoffset * info->fix.line_length + var->xoffset;
1259 par->riva.SetStartAddress(&par->riva, base);
1260 NVTRACE_LEAVE();
1261 return 0;
1262}
1263
1264static int rivafb_blank(int blank, struct fb_info *info)
1265{
1266 struct riva_par *par= info->par;
1267 unsigned char tmp, vesa;
1268
1269 tmp = SEQin(par, 0x01) & ~0x20;
1270 vesa = CRTCin(par, 0x1a) & ~0xc0;
1271
1272 NVTRACE_ENTER();
1273
1274 if (blank)
1275 tmp |= 0x20;
1276
1277 switch (blank) {
1278 case FB_BLANK_UNBLANK:
1279 case FB_BLANK_NORMAL:
1280 break;
1281 case FB_BLANK_VSYNC_SUSPEND:
1282 vesa |= 0x80;
1283 break;
1284 case FB_BLANK_HSYNC_SUSPEND:
1285 vesa |= 0x40;
1286 break;
1287 case FB_BLANK_POWERDOWN:
1288 vesa |= 0xc0;
1289 break;
1290 }
1291
1292 SEQout(par, 0x01, tmp);
1293 CRTCout(par, 0x1a, vesa);
1294
1295 NVTRACE_LEAVE();
1296
1297 return 0;
1298}
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1320 unsigned blue, unsigned transp,
1321 struct fb_info *info)
1322{
1323 struct riva_par *par = info->par;
1324 RIVA_HW_INST *chip = &par->riva;
1325 int i;
1326
1327 if (regno >= riva_get_cmap_len(&info->var))
1328 return -EINVAL;
1329
1330 if (info->var.grayscale) {
1331
1332 red = green = blue =
1333 (red * 77 + green * 151 + blue * 28) >> 8;
1334 }
1335
1336 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1337 ((u32 *) info->pseudo_palette)[regno] =
1338 (regno << info->var.red.offset) |
1339 (regno << info->var.green.offset) |
1340 (regno << info->var.blue.offset);
1341
1342
1343
1344
1345 if (par->riva.Architecture == NV_ARCH_03) {
1346 switch (info->var.bits_per_pixel) {
1347 case 16:
1348 par->palette[regno] = ((red & 0xf800) >> 1) |
1349 ((green & 0xf800) >> 6) |
1350 ((blue & 0xf800) >> 11);
1351 break;
1352 case 32:
1353 par->palette[regno] = ((red & 0xff00) << 8) |
1354 ((green & 0xff00)) |
1355 ((blue & 0xff00) >> 8);
1356 break;
1357 }
1358 }
1359 }
1360
1361 switch (info->var.bits_per_pixel) {
1362 case 8:
1363
1364 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1365 break;
1366 case 16:
1367 if (info->var.green.length == 5) {
1368 for (i = 0; i < 8; i++) {
1369 riva_wclut(chip, regno*8+i, red >> 8,
1370 green >> 8, blue >> 8);
1371 }
1372 } else {
1373 u8 r, g, b;
1374
1375 if (regno < 32) {
1376 for (i = 0; i < 8; i++) {
1377 riva_wclut(chip, regno*8+i,
1378 red >> 8, green >> 8,
1379 blue >> 8);
1380 }
1381 }
1382 riva_rclut(chip, regno*4, &r, &g, &b);
1383 for (i = 0; i < 4; i++)
1384 riva_wclut(chip, regno*4+i, r,
1385 green >> 8, b);
1386 }
1387 break;
1388 case 32:
1389 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1390 break;
1391 default:
1392
1393 break;
1394 }
1395 return 0;
1396}
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1411{
1412 struct riva_par *par = info->par;
1413 u_int color, rop = 0;
1414
1415 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1416 cfb_fillrect(info, rect);
1417 return;
1418 }
1419
1420 if (info->var.bits_per_pixel == 8)
1421 color = rect->color;
1422 else {
1423 if (par->riva.Architecture != NV_ARCH_03)
1424 color = ((u32 *)info->pseudo_palette)[rect->color];
1425 else
1426 color = par->palette[rect->color];
1427 }
1428
1429 switch (rect->rop) {
1430 case ROP_XOR:
1431 rop = 0x66;
1432 break;
1433 case ROP_COPY:
1434 default:
1435 rop = 0xCC;
1436 break;
1437 }
1438
1439 riva_set_rop_solid(par, rop);
1440
1441 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1442 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1443
1444 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1445 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1446 (rect->dx << 16) | rect->dy);
1447 mb();
1448 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1449 (rect->width << 16) | rect->height);
1450 mb();
1451 riva_set_rop_solid(par, 0xcc);
1452
1453}
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1467{
1468 struct riva_par *par = info->par;
1469
1470 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1471 cfb_copyarea(info, region);
1472 return;
1473 }
1474
1475 RIVA_FIFO_FREE(par->riva, Blt, 3);
1476 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1477 (region->sy << 16) | region->sx);
1478 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1479 (region->dy << 16) | region->dx);
1480 mb();
1481 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1482 (region->height << 16) | region->width);
1483 mb();
1484}
1485
1486static inline void convert_bgcolor_16(u32 *col)
1487{
1488 *col = ((*col & 0x0000F800) << 8)
1489 | ((*col & 0x00007E0) << 5)
1490 | ((*col & 0x0000001F) << 3)
1491 | 0xFF000000;
1492 mb();
1493}
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511static void rivafb_imageblit(struct fb_info *info,
1512 const struct fb_image *image)
1513{
1514 struct riva_par *par = info->par;
1515 u32 fgx = 0, bgx = 0, width, tmp;
1516 u8 *cdat = (u8 *) image->data;
1517 volatile u32 __iomem *d;
1518 int i, size;
1519
1520 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1521 cfb_imageblit(info, image);
1522 return;
1523 }
1524
1525 switch (info->var.bits_per_pixel) {
1526 case 8:
1527 fgx = image->fg_color;
1528 bgx = image->bg_color;
1529 break;
1530 case 16:
1531 case 32:
1532 if (par->riva.Architecture != NV_ARCH_03) {
1533 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1534 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1535 } else {
1536 fgx = par->palette[image->fg_color];
1537 bgx = par->palette[image->bg_color];
1538 }
1539 if (info->var.green.length == 6)
1540 convert_bgcolor_16(&bgx);
1541 break;
1542 }
1543
1544 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1545 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1546 (image->dy << 16) | (image->dx & 0xFFFF));
1547 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1548 (((image->dy + image->height) << 16) |
1549 ((image->dx + image->width) & 0xffff)));
1550 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1551 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1552 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1553 (image->height << 16) | ((image->width + 31) & ~31));
1554 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1555 (image->height << 16) | ((image->width + 31) & ~31));
1556 NV_WR32(&par->riva.Bitmap->PointE, 0,
1557 (image->dy << 16) | (image->dx & 0xFFFF));
1558
1559 d = &par->riva.Bitmap->MonochromeData01E;
1560
1561 width = (image->width + 31)/32;
1562 size = width * image->height;
1563 while (size >= 16) {
1564 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1565 for (i = 0; i < 16; i++) {
1566 tmp = *((u32 *)cdat);
1567 cdat = (u8 *)((u32 *)cdat + 1);
1568 reverse_order(&tmp);
1569 NV_WR32(d, i*4, tmp);
1570 }
1571 size -= 16;
1572 }
1573 if (size) {
1574 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1575 for (i = 0; i < size; i++) {
1576 tmp = *((u32 *) cdat);
1577 cdat = (u8 *)((u32 *)cdat + 1);
1578 reverse_order(&tmp);
1579 NV_WR32(d, i*4, tmp);
1580 }
1581 }
1582}
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1598{
1599 struct riva_par *par = info->par;
1600 u8 data[MAX_CURS * MAX_CURS/8];
1601 int i, set = cursor->set;
1602 u16 fg, bg;
1603
1604 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1605 return -ENXIO;
1606
1607 par->riva.ShowHideCursor(&par->riva, 0);
1608
1609 if (par->cursor_reset) {
1610 set = FB_CUR_SETALL;
1611 par->cursor_reset = 0;
1612 }
1613
1614 if (set & FB_CUR_SETSIZE)
1615 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1616
1617 if (set & FB_CUR_SETPOS) {
1618 u32 xx, yy, temp;
1619
1620 yy = cursor->image.dy - info->var.yoffset;
1621 xx = cursor->image.dx - info->var.xoffset;
1622 temp = xx & 0xFFFF;
1623 temp |= yy << 16;
1624
1625 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1626 }
1627
1628
1629 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1630 u32 bg_idx = cursor->image.bg_color;
1631 u32 fg_idx = cursor->image.fg_color;
1632 u32 s_pitch = (cursor->image.width+7) >> 3;
1633 u32 d_pitch = MAX_CURS/8;
1634 u8 *dat = (u8 *) cursor->image.data;
1635 u8 *msk = (u8 *) cursor->mask;
1636 u8 *src;
1637
1638 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1639
1640 if (src) {
1641 switch (cursor->rop) {
1642 case ROP_XOR:
1643 for (i = 0; i < s_pitch * cursor->image.height; i++)
1644 src[i] = dat[i] ^ msk[i];
1645 break;
1646 case ROP_COPY:
1647 default:
1648 for (i = 0; i < s_pitch * cursor->image.height; i++)
1649 src[i] = dat[i] & msk[i];
1650 break;
1651 }
1652
1653 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1654 cursor->image.height);
1655
1656 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1657 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1658 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1659 1 << 15;
1660
1661 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1662 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1663 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1664 1 << 15;
1665
1666 par->riva.LockUnlock(&par->riva, 0);
1667
1668 rivafb_load_cursor_image(par, data, bg, fg,
1669 cursor->image.width,
1670 cursor->image.height);
1671 kfree(src);
1672 }
1673 }
1674
1675 if (cursor->enable)
1676 par->riva.ShowHideCursor(&par->riva, 1);
1677
1678 return 0;
1679}
1680
1681static int rivafb_sync(struct fb_info *info)
1682{
1683 struct riva_par *par = info->par;
1684
1685 wait_for_idle(par);
1686 return 0;
1687}
1688
1689
1690
1691
1692
1693
1694
1695
1696static struct fb_ops riva_fb_ops = {
1697 .owner = THIS_MODULE,
1698 .fb_open = rivafb_open,
1699 .fb_release = rivafb_release,
1700 .fb_check_var = rivafb_check_var,
1701 .fb_set_par = rivafb_set_par,
1702 .fb_setcolreg = rivafb_setcolreg,
1703 .fb_pan_display = rivafb_pan_display,
1704 .fb_blank = rivafb_blank,
1705 .fb_fillrect = rivafb_fillrect,
1706 .fb_copyarea = rivafb_copyarea,
1707 .fb_imageblit = rivafb_imageblit,
1708 .fb_cursor = rivafb_cursor,
1709 .fb_sync = rivafb_sync,
1710};
1711
1712static int __devinit riva_set_fbinfo(struct fb_info *info)
1713{
1714 unsigned int cmap_len;
1715 struct riva_par *par = info->par;
1716
1717 NVTRACE_ENTER();
1718 info->flags = FBINFO_DEFAULT
1719 | FBINFO_HWACCEL_XPAN
1720 | FBINFO_HWACCEL_YPAN
1721 | FBINFO_HWACCEL_COPYAREA
1722 | FBINFO_HWACCEL_FILLRECT
1723 | FBINFO_HWACCEL_IMAGEBLIT;
1724
1725
1726 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1727 printk(KERN_DEBUG PFX "disabling acceleration\n");
1728 info->flags |= FBINFO_HWACCEL_DISABLED;
1729 }
1730
1731 info->var = rivafb_default_var;
1732 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1733 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1734
1735 info->pseudo_palette = par->pseudo_palette;
1736
1737 cmap_len = riva_get_cmap_len(&info->var);
1738 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1739
1740 info->pixmap.size = 8 * 1024;
1741 info->pixmap.buf_align = 4;
1742 info->pixmap.access_align = 32;
1743 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1744 info->var.yres_virtual = -1;
1745 NVTRACE_LEAVE();
1746 return (rivafb_check_var(&info->var, info));
1747}
1748
1749#ifdef CONFIG_PPC_OF
1750static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1751{
1752 struct riva_par *par = info->par;
1753 struct device_node *dp;
1754 const unsigned char *pedid = NULL;
1755 const unsigned char *disptype = NULL;
1756 static char *propnames[] = {
1757 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1758 int i;
1759
1760 NVTRACE_ENTER();
1761 dp = pci_device_to_OF_node(pd);
1762 for (; dp != NULL; dp = dp->child) {
1763 disptype = of_get_property(dp, "display-type", NULL);
1764 if (disptype == NULL)
1765 continue;
1766 if (strncmp(disptype, "LCD", 3) != 0)
1767 continue;
1768 for (i = 0; propnames[i] != NULL; ++i) {
1769 pedid = of_get_property(dp, propnames[i], NULL);
1770 if (pedid != NULL) {
1771 par->EDID = (unsigned char *)pedid;
1772 NVTRACE("LCD found.\n");
1773 return 1;
1774 }
1775 }
1776 }
1777 NVTRACE_LEAVE();
1778 return 0;
1779}
1780#endif
1781
1782#if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1783static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1784{
1785 struct riva_par *par = info->par;
1786 struct fb_var_screeninfo var;
1787 int i;
1788
1789 NVTRACE_ENTER();
1790 riva_create_i2c_busses(par);
1791 for (i = 0; i < 3; i++) {
1792 if (!par->chan[i].par)
1793 continue;
1794 riva_probe_i2c_connector(par, i, &par->EDID);
1795 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1796 printk(PFX "Found EDID Block from BUS %i\n", i);
1797 break;
1798 }
1799 }
1800
1801 NVTRACE_LEAVE();
1802 return (par->EDID) ? 1 : 0;
1803}
1804#endif
1805
1806static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1807 struct fb_info *info)
1808{
1809 struct fb_monspecs *specs = &info->monspecs;
1810 struct fb_videomode modedb;
1811
1812 NVTRACE_ENTER();
1813
1814 if (mode_option) {
1815 fb_find_mode(var, info, mode_option,
1816 specs->modedb, specs->modedb_len,
1817 NULL, 8);
1818 } else if (specs->modedb != NULL) {
1819
1820 modedb = specs->modedb[0];
1821
1822 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1823 int i;
1824
1825 for (i = 0; i < specs->modedb_len; i++) {
1826 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1827 modedb = specs->modedb[i];
1828 break;
1829 }
1830 }
1831 }
1832 var->bits_per_pixel = 8;
1833 riva_update_var(var, &modedb);
1834 }
1835 NVTRACE_LEAVE();
1836}
1837
1838
1839static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1840{
1841 NVTRACE_ENTER();
1842#ifdef CONFIG_PPC_OF
1843 if (!riva_get_EDID_OF(info, pdev))
1844 printk(PFX "could not retrieve EDID from OF\n");
1845#elif defined(CONFIG_FB_RIVA_I2C)
1846 if (!riva_get_EDID_i2c(info))
1847 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1848#endif
1849 NVTRACE_LEAVE();
1850}
1851
1852
1853static void __devinit riva_get_edidinfo(struct fb_info *info)
1854{
1855 struct fb_var_screeninfo *var = &rivafb_default_var;
1856 struct riva_par *par = info->par;
1857
1858 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1859 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1860 &info->modelist);
1861 riva_update_default_var(var, info);
1862
1863
1864 if (info->monspecs.input & FB_DISP_DDI)
1865 par->FlatPanel = 1;
1866}
1867
1868
1869
1870
1871
1872
1873
1874static u32 __devinit riva_get_arch(struct pci_dev *pd)
1875{
1876 u32 arch = 0;
1877
1878 switch (pd->device & 0x0ff0) {
1879 case 0x0100:
1880 case 0x0110:
1881 case 0x0150:
1882 case 0x0170:
1883 case 0x0180:
1884 case 0x01A0:
1885 case 0x01F0:
1886 arch = NV_ARCH_10;
1887 break;
1888 case 0x0200:
1889 case 0x0250:
1890 case 0x0280:
1891 arch = NV_ARCH_20;
1892 break;
1893 case 0x0300:
1894 case 0x0310:
1895 case 0x0320:
1896 case 0x0330:
1897 case 0x0340:
1898 arch = NV_ARCH_30;
1899 break;
1900 case 0x0020:
1901 arch = NV_ARCH_04;
1902 break;
1903 case 0x0010:
1904 arch = NV_ARCH_03;
1905 break;
1906 default:
1907 break;
1908 }
1909 return arch;
1910}
1911
1912static int __devinit rivafb_probe(struct pci_dev *pd,
1913 const struct pci_device_id *ent)
1914{
1915 struct riva_par *default_par;
1916 struct fb_info *info;
1917 int ret;
1918
1919 NVTRACE_ENTER();
1920 assert(pd != NULL);
1921
1922 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1923 if (!info) {
1924 printk (KERN_ERR PFX "could not allocate memory\n");
1925 ret = -ENOMEM;
1926 goto err_ret;
1927 }
1928 default_par = info->par;
1929 default_par->pdev = pd;
1930
1931 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1932 if (info->pixmap.addr == NULL) {
1933 ret = -ENOMEM;
1934 goto err_framebuffer_release;
1935 }
1936
1937 ret = pci_enable_device(pd);
1938 if (ret < 0) {
1939 printk(KERN_ERR PFX "cannot enable PCI device\n");
1940 goto err_free_pixmap;
1941 }
1942
1943 ret = pci_request_regions(pd, "rivafb");
1944 if (ret < 0) {
1945 printk(KERN_ERR PFX "cannot request PCI regions\n");
1946 goto err_disable_device;
1947 }
1948
1949 mutex_init(&default_par->open_lock);
1950 default_par->riva.Architecture = riva_get_arch(pd);
1951
1952 default_par->Chipset = (pd->vendor << 16) | pd->device;
1953 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1954
1955 if(default_par->riva.Architecture == 0) {
1956 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1957 ret=-ENODEV;
1958 goto err_release_region;
1959 }
1960 if(default_par->riva.Architecture == NV_ARCH_10 ||
1961 default_par->riva.Architecture == NV_ARCH_20 ||
1962 default_par->riva.Architecture == NV_ARCH_30) {
1963 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1964 } else {
1965 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1966 }
1967
1968 default_par->FlatPanel = flatpanel;
1969 if (flatpanel == 1)
1970 printk(KERN_INFO PFX "flatpanel support enabled\n");
1971 default_par->forceCRTC = forceCRTC;
1972
1973 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1974 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1975
1976 {
1977
1978 unsigned short cmd;
1979
1980 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1981 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1982 pci_write_config_word(pd, PCI_COMMAND, cmd);
1983 }
1984
1985 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1986 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1987
1988 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1989 rivafb_fix.mmio_len);
1990 if (!default_par->ctrl_base) {
1991 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1992 ret = -EIO;
1993 goto err_release_region;
1994 }
1995
1996 switch (default_par->riva.Architecture) {
1997 case NV_ARCH_03:
1998
1999
2000
2001
2002 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
2003 if (!default_par->riva.PRAMIN) {
2004 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
2005 ret = -EIO;
2006 goto err_iounmap_ctrl_base;
2007 }
2008 break;
2009 case NV_ARCH_04:
2010 case NV_ARCH_10:
2011 case NV_ARCH_20:
2012 case NV_ARCH_30:
2013 default_par->riva.PCRTC0 =
2014 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2015 default_par->riva.PRAMIN =
2016 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2017 break;
2018 }
2019 riva_common_setup(default_par);
2020
2021 if (default_par->riva.Architecture == NV_ARCH_03) {
2022 default_par->riva.PCRTC = default_par->riva.PCRTC0
2023 = default_par->riva.PGRAPH;
2024 }
2025
2026 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2027 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2028 info->screen_base = ioremap(rivafb_fix.smem_start,
2029 rivafb_fix.smem_len);
2030 if (!info->screen_base) {
2031 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2032 ret = -EIO;
2033 goto err_iounmap_pramin;
2034 }
2035
2036#ifdef CONFIG_MTRR
2037 if (!nomtrr) {
2038 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2039 rivafb_fix.smem_len,
2040 MTRR_TYPE_WRCOMB, 1);
2041 if (default_par->mtrr.vram < 0) {
2042 printk(KERN_ERR PFX "unable to setup MTRR\n");
2043 } else {
2044 default_par->mtrr.vram_valid = 1;
2045
2046 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2047 }
2048 }
2049#endif
2050
2051 info->fbops = &riva_fb_ops;
2052 info->fix = rivafb_fix;
2053 riva_get_EDID(info, pd);
2054 riva_get_edidinfo(info);
2055
2056 ret=riva_set_fbinfo(info);
2057 if (ret < 0) {
2058 printk(KERN_ERR PFX "error setting initial video mode\n");
2059 goto err_iounmap_screen_base;
2060 }
2061
2062 fb_destroy_modedb(info->monspecs.modedb);
2063 info->monspecs.modedb = NULL;
2064
2065 pci_set_drvdata(pd, info);
2066
2067 if (backlight)
2068 riva_bl_init(info->par);
2069
2070 ret = register_framebuffer(info);
2071 if (ret < 0) {
2072 printk(KERN_ERR PFX
2073 "error registering riva framebuffer\n");
2074 goto err_iounmap_screen_base;
2075 }
2076
2077 printk(KERN_INFO PFX
2078 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2079 info->fix.id,
2080 RIVAFB_VERSION,
2081 info->fix.smem_len / (1024 * 1024),
2082 info->fix.smem_start);
2083
2084 NVTRACE_LEAVE();
2085 return 0;
2086
2087err_iounmap_screen_base:
2088#ifdef CONFIG_FB_RIVA_I2C
2089 riva_delete_i2c_busses(info->par);
2090#endif
2091 iounmap(info->screen_base);
2092err_iounmap_pramin:
2093 if (default_par->riva.Architecture == NV_ARCH_03)
2094 iounmap(default_par->riva.PRAMIN);
2095err_iounmap_ctrl_base:
2096 iounmap(default_par->ctrl_base);
2097err_release_region:
2098 pci_release_regions(pd);
2099err_disable_device:
2100err_free_pixmap:
2101 kfree(info->pixmap.addr);
2102err_framebuffer_release:
2103 framebuffer_release(info);
2104err_ret:
2105 return ret;
2106}
2107
2108static void __devexit rivafb_remove(struct pci_dev *pd)
2109{
2110 struct fb_info *info = pci_get_drvdata(pd);
2111 struct riva_par *par = info->par;
2112
2113 NVTRACE_ENTER();
2114
2115#ifdef CONFIG_FB_RIVA_I2C
2116 riva_delete_i2c_busses(par);
2117 kfree(par->EDID);
2118#endif
2119
2120 unregister_framebuffer(info);
2121
2122 riva_bl_exit(info);
2123
2124#ifdef CONFIG_MTRR
2125 if (par->mtrr.vram_valid)
2126 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2127 info->fix.smem_len);
2128#endif
2129
2130 iounmap(par->ctrl_base);
2131 iounmap(info->screen_base);
2132 if (par->riva.Architecture == NV_ARCH_03)
2133 iounmap(par->riva.PRAMIN);
2134 pci_release_regions(pd);
2135 kfree(info->pixmap.addr);
2136 framebuffer_release(info);
2137 pci_set_drvdata(pd, NULL);
2138 NVTRACE_LEAVE();
2139}
2140
2141
2142
2143
2144
2145
2146
2147#ifndef MODULE
2148static int __devinit rivafb_setup(char *options)
2149{
2150 char *this_opt;
2151
2152 NVTRACE_ENTER();
2153 if (!options || !*options)
2154 return 0;
2155
2156 while ((this_opt = strsep(&options, ",")) != NULL) {
2157 if (!strncmp(this_opt, "forceCRTC", 9)) {
2158 char *p;
2159
2160 p = this_opt + 9;
2161 if (!*p || !*(++p)) continue;
2162 forceCRTC = *p - '0';
2163 if (forceCRTC < 0 || forceCRTC > 1)
2164 forceCRTC = -1;
2165 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2166 flatpanel = 1;
2167 } else if (!strncmp(this_opt, "backlight:", 10)) {
2168 backlight = simple_strtoul(this_opt+10, NULL, 0);
2169#ifdef CONFIG_MTRR
2170 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2171 nomtrr = 1;
2172#endif
2173 } else if (!strncmp(this_opt, "strictmode", 10)) {
2174 strictmode = 1;
2175 } else if (!strncmp(this_opt, "noaccel", 7)) {
2176 noaccel = 1;
2177 } else
2178 mode_option = this_opt;
2179 }
2180 NVTRACE_LEAVE();
2181 return 0;
2182}
2183#endif
2184
2185static struct pci_driver rivafb_driver = {
2186 .name = "rivafb",
2187 .id_table = rivafb_pci_tbl,
2188 .probe = rivafb_probe,
2189 .remove = __devexit_p(rivafb_remove),
2190};
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200static int __devinit rivafb_init(void)
2201{
2202#ifndef MODULE
2203 char *option = NULL;
2204
2205 if (fb_get_options("rivafb", &option))
2206 return -ENODEV;
2207 rivafb_setup(option);
2208#endif
2209 return pci_register_driver(&rivafb_driver);
2210}
2211
2212
2213module_init(rivafb_init);
2214
2215static void __exit rivafb_exit(void)
2216{
2217 pci_unregister_driver(&rivafb_driver);
2218}
2219
2220module_exit(rivafb_exit);
2221
2222module_param(noaccel, bool, 0);
2223MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2224module_param(flatpanel, int, 0);
2225MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2226module_param(forceCRTC, int, 0);
2227MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2228#ifdef CONFIG_MTRR
2229module_param(nomtrr, bool, 0);
2230MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2231#endif
2232module_param(strictmode, bool, 0);
2233MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2234
2235MODULE_AUTHOR("Ani Joshi, maintainer");
2236MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2237MODULE_LICENSE("GPL");
2238
