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16#include <linux/init.h>
17#include <linux/suspend.h>
18#include <linux/syscore_ops.h>
19#include <linux/io.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22
23#include <asm/cacheflush.h>
24#include <asm/hardware/cache-l2x0.h>
25#include <asm/smp_scu.h>
26
27#include <plat/cpu.h>
28#include <plat/pm.h>
29#include <plat/pll.h>
30#include <plat/regs-srom.h>
31
32#include <mach/regs-irq.h>
33#include <mach/regs-gpio.h>
34#include <mach/regs-clock.h>
35#include <mach/regs-pmu.h>
36#include <mach/pm-core.h>
37#include <mach/pmu.h>
38
39static struct sleep_save exynos4_set_clksrc[] = {
40 { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
41 { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
42 { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
43 { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
44 { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
45 { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
46 { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
47 { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
48 { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
49};
50
51static struct sleep_save exynos4210_set_clksrc[] = {
52 { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
53};
54
55static struct sleep_save exynos4_epll_save[] = {
56 SAVE_ITEM(EXYNOS4_EPLL_CON0),
57 SAVE_ITEM(EXYNOS4_EPLL_CON1),
58};
59
60static struct sleep_save exynos4_vpll_save[] = {
61 SAVE_ITEM(EXYNOS4_VPLL_CON0),
62 SAVE_ITEM(EXYNOS4_VPLL_CON1),
63};
64
65static struct sleep_save exynos_core_save[] = {
66
67 SAVE_ITEM(S5P_SROM_BW),
68 SAVE_ITEM(S5P_SROM_BC0),
69 SAVE_ITEM(S5P_SROM_BC1),
70 SAVE_ITEM(S5P_SROM_BC2),
71 SAVE_ITEM(S5P_SROM_BC3),
72};
73
74
75
76static unsigned int save_arm_register[2];
77
78static int exynos_cpu_suspend(unsigned long arg)
79{
80#ifdef CONFIG_CACHE_L2X0
81 outer_flush_all();
82#endif
83
84
85 cpu_do_idle();
86
87
88 panic("sleep resumed to originator?");
89}
90
91static void exynos_pm_prepare(void)
92{
93 unsigned int tmp;
94
95 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
96
97 if (!soc_is_exynos5250()) {
98 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
99 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
100 } else {
101
102 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
103 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
104 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
105 }
106
107
108
109 exynos_sys_powerdown_conf(SYS_SLEEP);
110 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
111
112
113
114 __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
115
116
117
118 if (!soc_is_exynos5250())
119 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
120
121 if (soc_is_exynos4210())
122 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
123
124}
125
126static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
127{
128 pm_cpu_prep = exynos_pm_prepare;
129 pm_cpu_sleep = exynos_cpu_suspend;
130
131 return 0;
132}
133
134static unsigned long pll_base_rate;
135
136static void exynos4_restore_pll(void)
137{
138 unsigned long pll_con, locktime, lockcnt;
139 unsigned long pll_in_rate;
140 unsigned int p_div, epll_wait = 0, vpll_wait = 0;
141
142 if (pll_base_rate == 0)
143 return;
144
145 pll_in_rate = pll_base_rate;
146
147
148 pll_con = exynos4_epll_save[0].val;
149
150 if (pll_con & (1 << 31)) {
151 pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
152 p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
153
154 pll_in_rate /= 1000000;
155
156 locktime = (3000 / pll_in_rate) * p_div;
157 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
158
159 __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
160
161 s3c_pm_do_restore_core(exynos4_epll_save,
162 ARRAY_SIZE(exynos4_epll_save));
163 epll_wait = 1;
164 }
165
166 pll_in_rate = pll_base_rate;
167
168
169 pll_con = exynos4_vpll_save[0].val;
170
171 if (pll_con & (1 << 31)) {
172 pll_in_rate /= 1000000;
173
174 locktime = 750;
175 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
176
177 __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
178
179 s3c_pm_do_restore_core(exynos4_vpll_save,
180 ARRAY_SIZE(exynos4_vpll_save));
181 vpll_wait = 1;
182 }
183
184
185
186 do {
187 if (epll_wait) {
188 pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
189 if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
190 epll_wait = 0;
191 }
192
193 if (vpll_wait) {
194 pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
195 if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
196 vpll_wait = 0;
197 }
198 } while (epll_wait || vpll_wait);
199}
200
201static struct subsys_interface exynos_pm_interface = {
202 .name = "exynos_pm",
203 .subsys = &exynos_subsys,
204 .add_dev = exynos_pm_add,
205};
206
207static __init int exynos_pm_drvinit(void)
208{
209 struct clk *pll_base;
210 unsigned int tmp;
211
212 s3c_pm_init();
213
214
215
216 tmp = __raw_readl(S5P_WAKEUP_MASK);
217 tmp |= ((0xFF << 8) | (0x1F << 1));
218 __raw_writel(tmp, S5P_WAKEUP_MASK);
219
220 if (!soc_is_exynos5250()) {
221 pll_base = clk_get(NULL, "xtal");
222
223 if (!IS_ERR(pll_base)) {
224 pll_base_rate = clk_get_rate(pll_base);
225 clk_put(pll_base);
226 }
227 }
228
229 return subsys_interface_register(&exynos_pm_interface);
230}
231arch_initcall(exynos_pm_drvinit);
232
233static int exynos_pm_suspend(void)
234{
235 unsigned long tmp;
236
237
238
239 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
240 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
241 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
242
243
244
245 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
246 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
247
248 if (!soc_is_exynos5250()) {
249
250 asm ("mrc p15, 0, %0, c15, c0, 0"
251 : "=r" (tmp) : : "cc");
252 save_arm_register[0] = tmp;
253
254
255 asm ("mrc p15, 0, %0, c15, c0, 1"
256 : "=r" (tmp) : : "cc");
257 save_arm_register[1] = tmp;
258 }
259
260 return 0;
261}
262
263static void exynos_pm_resume(void)
264{
265 unsigned long tmp;
266
267
268
269
270
271
272
273 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
274 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
275 tmp |= S5P_CENTRAL_LOWPWR_CFG;
276 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
277
278 goto early_wakeup;
279 }
280 if (!soc_is_exynos5250()) {
281
282 tmp = save_arm_register[0];
283 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
284 : : "r" (tmp)
285 : "cc");
286
287
288 tmp = save_arm_register[1];
289 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
290 : : "r" (tmp)
291 : "cc");
292 }
293
294
295
296 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
297 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
298 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
299 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
300 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
301 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
302 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
303
304 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
305
306 if (!soc_is_exynos5250()) {
307 exynos4_restore_pll();
308
309#ifdef CONFIG_SMP
310 scu_enable(S5P_VA_SCU);
311#endif
312 }
313
314early_wakeup:
315 return;
316}
317
318static struct syscore_ops exynos_pm_syscore_ops = {
319 .suspend = exynos_pm_suspend,
320 .resume = exynos_pm_resume,
321};
322
323static __init int exynos_pm_syscore_init(void)
324{
325 register_syscore_ops(&exynos_pm_syscore_ops);
326 return 0;
327}
328arch_initcall(exynos_pm_syscore_init);
329
