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24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/interrupt.h>
32#include <linux/ioport.h>
33#include <linux/mutex.h>
34#include <linux/clk.h>
35#include <linux/io.h>
36#include <linux/serial_core.h>
37
38#include <mach/hardware.h>
39#include <linux/atomic.h>
40#include <asm/irq.h>
41
42#include <mach/regs-clock.h>
43
44#include <plat/clock.h>
45#include <plat/cpu.h>
46#include <plat/regs-serial.h>
47
48
49
50static unsigned long s3c2440_camif_upll_round(struct clk *clk,
51 unsigned long rate)
52{
53 unsigned long parent_rate = clk_get_rate(clk->parent);
54 int div;
55
56 if (rate > parent_rate)
57 return parent_rate;
58
59
60
61 div = (parent_rate / rate) / 2;
62
63 if (div < 1)
64 div = 1;
65 else if (div > 16)
66 div = 16;
67
68 return parent_rate / (div * 2);
69}
70
71static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
72{
73 unsigned long parent_rate = clk_get_rate(clk->parent);
74 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
75
76 rate = s3c2440_camif_upll_round(clk, rate);
77
78 camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
79
80 if (rate != parent_rate) {
81 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
82 camdivn |= (((parent_rate / rate) / 2) - 1);
83 }
84
85 __raw_writel(camdivn, S3C2440_CAMDIVN);
86
87 return 0;
88}
89
90static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
91{
92 unsigned long parent_rate = clk_get_rate(clk->parent);
93 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
94
95 if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
96 return parent_rate;
97
98 camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;
99
100 return parent_rate / (camdivn + 1) / 2;
101}
102
103
104
105static struct clk s3c2440_clk_cam = {
106 .name = "camif",
107 .enable = s3c2410_clkcon_enable,
108 .ctrlbit = S3C2440_CLKCON_CAMERA,
109};
110
111static struct clk s3c2440_clk_cam_upll = {
112 .name = "camif-upll",
113 .ops = &(struct clk_ops) {
114 .set_rate = s3c2440_camif_upll_setrate,
115 .get_rate = s3c2440_camif_upll_getrate,
116 .round_rate = s3c2440_camif_upll_round,
117 },
118};
119
120static struct clk s3c2440_clk_ac97 = {
121 .name = "ac97",
122 .enable = s3c2410_clkcon_enable,
123 .ctrlbit = S3C2440_CLKCON_AC97,
124};
125
126static unsigned long s3c2440_fclk_n_getrate(struct clk *clk)
127{
128 unsigned long ucon0, ucon1, ucon2, divisor;
129
130
131 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
132 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
133 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
134
135 ucon0 &= S3C2440_UCON0_DIVMASK;
136 ucon1 &= S3C2440_UCON1_DIVMASK;
137 ucon2 &= S3C2440_UCON2_DIVMASK;
138
139 if (ucon0 != 0)
140 divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
141 else if (ucon1 != 0)
142 divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
143 else if (ucon2 != 0)
144 divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
145 else
146
147 divisor = 9;
148
149 return clk_get_rate(clk->parent) / divisor;
150}
151
152static struct clk s3c2440_clk_fclk_n = {
153 .name = "fclk_n",
154 .parent = &clk_f,
155 .ops = &(struct clk_ops) {
156 .get_rate = s3c2440_fclk_n_getrate,
157 },
158};
159
160static struct clk_lookup s3c2440_clk_lookup[] = {
161 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
162 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
163 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
164};
165
166static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
167{
168 struct clk *clock_upll;
169 struct clk *clock_h;
170 struct clk *clock_p;
171
172 clock_p = clk_get(NULL, "pclk");
173 clock_h = clk_get(NULL, "hclk");
174 clock_upll = clk_get(NULL, "upll");
175
176 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
177 printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
178 return -EINVAL;
179 }
180
181 s3c2440_clk_cam.parent = clock_h;
182 s3c2440_clk_ac97.parent = clock_p;
183 s3c2440_clk_cam_upll.parent = clock_upll;
184 s3c24xx_register_clock(&s3c2440_clk_fclk_n);
185
186 s3c24xx_register_clock(&s3c2440_clk_ac97);
187 s3c24xx_register_clock(&s3c2440_clk_cam);
188 s3c24xx_register_clock(&s3c2440_clk_cam_upll);
189 clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
190
191 clk_disable(&s3c2440_clk_ac97);
192 clk_disable(&s3c2440_clk_cam);
193
194 return 0;
195}
196
197static struct subsys_interface s3c2440_clk_interface = {
198 .name = "s3c2440_clk",
199 .subsys = &s3c2440_subsys,
200 .add_dev = s3c2440_clk_add,
201};
202
203static __init int s3c24xx_clk_init(void)
204{
205 return subsys_interface_register(&s3c2440_clk_interface);
206}
207
208arch_initcall(s3c24xx_clk_init);
209
