LXR linux/arch/blackfin/lib/outs.S

   1/*
   2 * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
   3 *
   4 * Copyright 2005-2009 Analog Devices Inc.
   5 *                2005 BuyWays BV
   6 *                      Bas Vermeulen <bas@buyways.nl>
   7 *
   8 * Licensed under the GPL-2.
   9 */
  10
  11#include <linux/linkage.h>
  12
  13.align 2
  14
  15ENTRY(_outsl)
  16        CC = R2 == 0;
  17        IF CC JUMP 1f;
  18        P0 = R0;        /* P0 = port */
  19        P1 = R1;        /* P1 = address */
  20        P2 = R2;        /* P2 = count */
  21
  22        LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
  23.Llong_loop_s: R0 = [P1++];
  24.Llong_loop_e: [P0] = R0;
  251:      RTS;
  26ENDPROC(_outsl)
  27
  28ENTRY(_outsw)
  29        CC = R2 == 0;
  30        IF CC JUMP 1f;
  31        P0 = R0;        /* P0 = port */
  32        P1 = R1;        /* P1 = address */
  33        P2 = R2;        /* P2 = count */
  34
  35        LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
  36.Lword_loop_s: R0 = W[P1++];
  37.Lword_loop_e: W[P0] = R0;
  381:      RTS;
  39ENDPROC(_outsw)
  40
  41ENTRY(_outsb)
  42        CC = R2 == 0;
  43        IF CC JUMP 1f;
  44        P0 = R0;        /* P0 = port */
  45        P1 = R1;        /* P1 = address */
  46        P2 = R2;        /* P2 = count */
  47
  48        LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
  49.Lbyte_loop_s: R0 = B[P1++];
  50.Lbyte_loop_e: B[P0] = R0;
  511:      RTS;
  52ENDPROC(_outsb)
  53
  54ENTRY(_outsw_8)
  55        CC = R2 == 0;
  56        IF CC JUMP 1f;
  57        P0 = R0;        /* P0 = port */
  58        P1 = R1;        /* P1 = address */
  59        P2 = R2;        /* P2 = count */
  60
  61        LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
  62.Lword8_loop_s: R1 = B[P1++];
  63                R0 = B[P1++];
  64                R0 = R0 << 8;
  65                R0 = R0 + R1;
  66.Lword8_loop_e: W[P0] = R0;
  671:      RTS;
  68ENDPROC(_outsw_8)
  69