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34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/gfp.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/device.h>
43#include <scsi/scsi.h>
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46#include <linux/libata.h>
47#include "sata_promise.h"
48
49#define DRV_NAME "sata_promise"
50#define DRV_VERSION "2.12"
51
52enum {
53 PDC_MAX_PORTS = 4,
54 PDC_MMIO_BAR = 3,
55 PDC_MAX_PRD = LIBATA_MAX_PRD - 1,
56
57
58 PDC_INT_SEQMASK = 0x40,
59 PDC_FLASH_CTL = 0x44,
60 PDC_PCI_CTL = 0x48,
61 PDC_SATA_PLUG_CSR = 0x6C,
62 PDC2_SATA_PLUG_CSR = 0x60,
63 PDC_TBG_MODE = 0x41C,
64 PDC_SLEW_CTL = 0x470,
65
66
67 PDC_FEATURE = 0x04,
68 PDC_SECTOR_COUNT = 0x08,
69 PDC_SECTOR_NUMBER = 0x0C,
70 PDC_CYLINDER_LOW = 0x10,
71 PDC_CYLINDER_HIGH = 0x14,
72 PDC_DEVICE = 0x18,
73 PDC_COMMAND = 0x1C,
74 PDC_ALTSTATUS = 0x38,
75 PDC_PKT_SUBMIT = 0x40,
76 PDC_GLOBAL_CTL = 0x48,
77 PDC_CTLSTAT = 0x60,
78
79
80 PDC_SATA_ERROR = 0x04,
81 PDC_PHYMODE4 = 0x14,
82 PDC_LINK_LAYER_ERRORS = 0x6C,
83 PDC_FPDMA_CTLSTAT = 0xD8,
84 PDC_INTERNAL_DEBUG_1 = 0xF8,
85 PDC_INTERNAL_DEBUG_2 = 0xFC,
86
87
88 PDC_FPDMA_CTLSTAT_RESET = 1 << 3,
89 PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10,
90 PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11,
91
92
93 PDC_PH_ERR = (1 << 8),
94 PDC_SH_ERR = (1 << 9),
95 PDC_DH_ERR = (1 << 10),
96 PDC2_HTO_ERR = (1 << 12),
97 PDC2_ATA_HBA_ERR = (1 << 13),
98 PDC2_ATA_DMA_CNT_ERR = (1 << 14),
99 PDC_OVERRUN_ERR = (1 << 19),
100 PDC_UNDERRUN_ERR = (1 << 20),
101 PDC_DRIVE_ERR = (1 << 21),
102 PDC_PCI_SYS_ERR = (1 << 22),
103 PDC1_PCI_PARITY_ERR = (1 << 23),
104 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
105 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
106 PDC2_ATA_DMA_CNT_ERR,
107 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
108 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
109 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
110 PDC1_ERR_MASK | PDC2_ERR_MASK,
111
112 board_2037x = 0,
113 board_2037x_pata = 1,
114 board_20319 = 2,
115 board_20619 = 3,
116 board_2057x = 4,
117 board_2057x_pata = 5,
118 board_40518 = 6,
119
120 PDC_HAS_PATA = (1 << 1),
121
122
123 PDC_SEQCNTRL_INT_MASK = (1 << 5),
124
125
126 PDC_FEATURE_ATAPI_PIO = 0x00,
127 PDC_FEATURE_ATAPI_DMA = 0x01,
128
129
130 PDC_DEVICE_SATA = 0xE0,
131
132
133 PDC_DMA_ENABLE = (1 << 7),
134 PDC_IRQ_DISABLE = (1 << 10),
135 PDC_RESET = (1 << 11),
136
137 PDC_COMMON_FLAGS = ATA_FLAG_PIO_POLLING,
138
139
140 PDC_FLAG_GEN_II = (1 << 24),
141 PDC_FLAG_SATA_PATA = (1 << 25),
142 PDC_FLAG_4_PORTS = (1 << 26),
143};
144
145struct pdc_port_priv {
146 u8 *pkt;
147 dma_addr_t pkt_dma;
148};
149
150static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
151static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
152static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
153static int pdc_common_port_start(struct ata_port *ap);
154static int pdc_sata_port_start(struct ata_port *ap);
155static void pdc_qc_prep(struct ata_queued_cmd *qc);
156static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
157static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
158static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
159static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
160static void pdc_irq_clear(struct ata_port *ap);
161static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
162static void pdc_freeze(struct ata_port *ap);
163static void pdc_sata_freeze(struct ata_port *ap);
164static void pdc_thaw(struct ata_port *ap);
165static void pdc_sata_thaw(struct ata_port *ap);
166static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
167 unsigned long deadline);
168static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
169 unsigned long deadline);
170static void pdc_error_handler(struct ata_port *ap);
171static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
172static int pdc_pata_cable_detect(struct ata_port *ap);
173static int pdc_sata_cable_detect(struct ata_port *ap);
174
175static struct scsi_host_template pdc_ata_sht = {
176 ATA_BASE_SHT(DRV_NAME),
177 .sg_tablesize = PDC_MAX_PRD,
178 .dma_boundary = ATA_DMA_BOUNDARY,
179};
180
181static const struct ata_port_operations pdc_common_ops = {
182 .inherits = &ata_sff_port_ops,
183
184 .sff_tf_load = pdc_tf_load_mmio,
185 .sff_exec_command = pdc_exec_command_mmio,
186 .check_atapi_dma = pdc_check_atapi_dma,
187 .qc_prep = pdc_qc_prep,
188 .qc_issue = pdc_qc_issue,
189
190 .sff_irq_clear = pdc_irq_clear,
191 .lost_interrupt = ATA_OP_NULL,
192
193 .post_internal_cmd = pdc_post_internal_cmd,
194 .error_handler = pdc_error_handler,
195};
196
197static struct ata_port_operations pdc_sata_ops = {
198 .inherits = &pdc_common_ops,
199 .cable_detect = pdc_sata_cable_detect,
200 .freeze = pdc_sata_freeze,
201 .thaw = pdc_sata_thaw,
202 .scr_read = pdc_sata_scr_read,
203 .scr_write = pdc_sata_scr_write,
204 .port_start = pdc_sata_port_start,
205 .hardreset = pdc_sata_hardreset,
206};
207
208
209
210static struct ata_port_operations pdc_old_sata_ops = {
211 .inherits = &pdc_sata_ops,
212 .freeze = pdc_freeze,
213 .thaw = pdc_thaw,
214 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
215};
216
217static struct ata_port_operations pdc_pata_ops = {
218 .inherits = &pdc_common_ops,
219 .cable_detect = pdc_pata_cable_detect,
220 .freeze = pdc_freeze,
221 .thaw = pdc_thaw,
222 .port_start = pdc_common_port_start,
223 .softreset = pdc_pata_softreset,
224};
225
226static const struct ata_port_info pdc_port_info[] = {
227 [board_2037x] =
228 {
229 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
230 PDC_FLAG_SATA_PATA,
231 .pio_mask = ATA_PIO4,
232 .mwdma_mask = ATA_MWDMA2,
233 .udma_mask = ATA_UDMA6,
234 .port_ops = &pdc_old_sata_ops,
235 },
236
237 [board_2037x_pata] =
238 {
239 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
240 .pio_mask = ATA_PIO4,
241 .mwdma_mask = ATA_MWDMA2,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &pdc_pata_ops,
244 },
245
246 [board_20319] =
247 {
248 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
249 PDC_FLAG_4_PORTS,
250 .pio_mask = ATA_PIO4,
251 .mwdma_mask = ATA_MWDMA2,
252 .udma_mask = ATA_UDMA6,
253 .port_ops = &pdc_old_sata_ops,
254 },
255
256 [board_20619] =
257 {
258 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
259 PDC_FLAG_4_PORTS,
260 .pio_mask = ATA_PIO4,
261 .mwdma_mask = ATA_MWDMA2,
262 .udma_mask = ATA_UDMA6,
263 .port_ops = &pdc_pata_ops,
264 },
265
266 [board_2057x] =
267 {
268 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
269 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
270 .pio_mask = ATA_PIO4,
271 .mwdma_mask = ATA_MWDMA2,
272 .udma_mask = ATA_UDMA6,
273 .port_ops = &pdc_sata_ops,
274 },
275
276 [board_2057x_pata] =
277 {
278 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
279 PDC_FLAG_GEN_II,
280 .pio_mask = ATA_PIO4,
281 .mwdma_mask = ATA_MWDMA2,
282 .udma_mask = ATA_UDMA6,
283 .port_ops = &pdc_pata_ops,
284 },
285
286 [board_40518] =
287 {
288 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
289 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
290 .pio_mask = ATA_PIO4,
291 .mwdma_mask = ATA_MWDMA2,
292 .udma_mask = ATA_UDMA6,
293 .port_ops = &pdc_sata_ops,
294 },
295};
296
297static const struct pci_device_id pdc_ata_pci_tbl[] = {
298 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
299 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
300 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
301 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
302 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
303 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
304 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
305 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
306 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
307 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
308
309 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
310 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
311 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
312 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
313 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
314 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
315
316 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
317
318 { }
319};
320
321static struct pci_driver pdc_ata_pci_driver = {
322 .name = DRV_NAME,
323 .id_table = pdc_ata_pci_tbl,
324 .probe = pdc_ata_init_one,
325 .remove = ata_pci_remove_one,
326};
327
328static int pdc_common_port_start(struct ata_port *ap)
329{
330 struct device *dev = ap->host->dev;
331 struct pdc_port_priv *pp;
332 int rc;
333
334
335 rc = ata_bmdma_port_start(ap);
336 if (rc)
337 return rc;
338
339 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
340 if (!pp)
341 return -ENOMEM;
342
343 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
344 if (!pp->pkt)
345 return -ENOMEM;
346
347 ap->private_data = pp;
348
349 return 0;
350}
351
352static int pdc_sata_port_start(struct ata_port *ap)
353{
354 int rc;
355
356 rc = pdc_common_port_start(ap);
357 if (rc)
358 return rc;
359
360
361 if (ap->flags & PDC_FLAG_GEN_II) {
362 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
363 unsigned int tmp;
364
365 tmp = readl(sata_mmio + PDC_PHYMODE4);
366 tmp = (tmp & ~3) | 1;
367 writel(tmp, sata_mmio + PDC_PHYMODE4);
368 }
369
370 return 0;
371}
372
373static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap)
374{
375 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
376 u32 tmp;
377
378 tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT);
379 tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG;
380 tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG;
381
382
383
384 writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1);
385 readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1);
386}
387
388static void pdc_fpdma_reset(struct ata_port *ap)
389{
390 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
391 u8 tmp;
392
393 tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT);
394 tmp &= 0x7F;
395 tmp |= PDC_FPDMA_CTLSTAT_RESET;
396 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
397 readl(sata_mmio + PDC_FPDMA_CTLSTAT);
398 udelay(100);
399 tmp &= ~PDC_FPDMA_CTLSTAT_RESET;
400 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
401 readl(sata_mmio + PDC_FPDMA_CTLSTAT);
402
403 pdc_fpdma_clear_interrupt_flag(ap);
404}
405
406static void pdc_not_at_command_packet_phase(struct ata_port *ap)
407{
408 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
409 unsigned int i;
410 u32 tmp;
411
412
413 for (i = 0; i < 100; ++i) {
414 writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
415 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2);
416 if ((tmp & 0xF) != 1)
417 break;
418 udelay(100);
419 }
420}
421
422static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap)
423{
424 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
425
426 writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
427 writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
428}
429
430static void pdc_reset_port(struct ata_port *ap)
431{
432 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
433 unsigned int i;
434 u32 tmp;
435
436 if (ap->flags & PDC_FLAG_GEN_II)
437 pdc_not_at_command_packet_phase(ap);
438
439 tmp = readl(ata_ctlstat_mmio);
440 tmp |= PDC_RESET;
441 writel(tmp, ata_ctlstat_mmio);
442
443 for (i = 11; i > 0; i--) {
444 tmp = readl(ata_ctlstat_mmio);
445 if (tmp & PDC_RESET)
446 break;
447
448 udelay(100);
449
450 tmp |= PDC_RESET;
451 writel(tmp, ata_ctlstat_mmio);
452 }
453
454 tmp &= ~PDC_RESET;
455 writel(tmp, ata_ctlstat_mmio);
456 readl(ata_ctlstat_mmio);
457
458 if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) {
459 pdc_fpdma_reset(ap);
460 pdc_clear_internal_debug_record_error_register(ap);
461 }
462}
463
464static int pdc_pata_cable_detect(struct ata_port *ap)
465{
466 u8 tmp;
467 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
468
469 tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
470 if (tmp & 0x01)
471 return ATA_CBL_PATA40;
472 return ATA_CBL_PATA80;
473}
474
475static int pdc_sata_cable_detect(struct ata_port *ap)
476{
477 return ATA_CBL_SATA;
478}
479
480static int pdc_sata_scr_read(struct ata_link *link,
481 unsigned int sc_reg, u32 *val)
482{
483 if (sc_reg > SCR_CONTROL)
484 return -EINVAL;
485 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
486 return 0;
487}
488
489static int pdc_sata_scr_write(struct ata_link *link,
490 unsigned int sc_reg, u32 val)
491{
492 if (sc_reg > SCR_CONTROL)
493 return -EINVAL;
494 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
495 return 0;
496}
497
498static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
499{
500 struct ata_port *ap = qc->ap;
501 dma_addr_t sg_table = ap->bmdma_prd_dma;
502 unsigned int cdb_len = qc->dev->cdb_len;
503 u8 *cdb = qc->cdb;
504 struct pdc_port_priv *pp = ap->private_data;
505 u8 *buf = pp->pkt;
506 __le32 *buf32 = (__le32 *) buf;
507 unsigned int dev_sel, feature;
508
509
510
511
512 switch (qc->tf.protocol) {
513 case ATAPI_PROT_DMA:
514 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
515 buf32[0] = cpu_to_le32(PDC_PKT_READ);
516 else
517 buf32[0] = 0;
518 break;
519 case ATAPI_PROT_NODATA:
520 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
521 break;
522 default:
523 BUG();
524 break;
525 }
526 buf32[1] = cpu_to_le32(sg_table);
527 buf32[2] = 0;
528
529
530 if (sata_scr_valid(&ap->link))
531 dev_sel = PDC_DEVICE_SATA;
532 else
533 dev_sel = qc->tf.device;
534
535 buf[12] = (1 << 5) | ATA_REG_DEVICE;
536 buf[13] = dev_sel;
537 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
538 buf[15] = dev_sel;
539
540 buf[16] = (1 << 5) | ATA_REG_NSECT;
541 buf[17] = qc->tf.nsect;
542 buf[18] = (1 << 5) | ATA_REG_LBAL;
543 buf[19] = qc->tf.lbal;
544
545
546 if (qc->tf.protocol != ATAPI_PROT_DMA)
547 feature = PDC_FEATURE_ATAPI_PIO;
548 else
549 feature = PDC_FEATURE_ATAPI_DMA;
550
551 buf[20] = (1 << 5) | ATA_REG_FEATURE;
552 buf[21] = feature;
553 buf[22] = (1 << 5) | ATA_REG_BYTEL;
554 buf[23] = qc->tf.lbam;
555 buf[24] = (1 << 5) | ATA_REG_BYTEH;
556 buf[25] = qc->tf.lbah;
557
558
559 buf[26] = (1 << 5) | ATA_REG_CMD;
560 buf[27] = qc->tf.command;
561
562
563 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
564 buf[29] = dev_sel;
565
566
567 BUG_ON(cdb_len & ~0x1E);
568
569
570 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
571 memcpy(buf+31, cdb, cdb_len);
572}
573
574
575
576
577
578
579
580
581
582
583
584
585
586static void pdc_fill_sg(struct ata_queued_cmd *qc)
587{
588 struct ata_port *ap = qc->ap;
589 struct ata_bmdma_prd *prd = ap->bmdma_prd;
590 struct scatterlist *sg;
591 const u32 SG_COUNT_ASIC_BUG = 41*4;
592 unsigned int si, idx;
593 u32 len;
594
595 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
596 return;
597
598 idx = 0;
599 for_each_sg(qc->sg, sg, qc->n_elem, si) {
600 u32 addr, offset;
601 u32 sg_len;
602
603
604
605
606
607 addr = (u32) sg_dma_address(sg);
608 sg_len = sg_dma_len(sg);
609
610 while (sg_len) {
611 offset = addr & 0xffff;
612 len = sg_len;
613 if ((offset + sg_len) > 0x10000)
614 len = 0x10000 - offset;
615
616 prd[idx].addr = cpu_to_le32(addr);
617 prd[idx].flags_len = cpu_to_le32(len & 0xffff);
618 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
619
620 idx++;
621 sg_len -= len;
622 addr += len;
623 }
624 }
625
626 len = le32_to_cpu(prd[idx - 1].flags_len);
627
628 if (len > SG_COUNT_ASIC_BUG) {
629 u32 addr;
630
631 VPRINTK("Splitting last PRD.\n");
632
633 addr = le32_to_cpu(prd[idx - 1].addr);
634 prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
635 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
636
637 addr = addr + len - SG_COUNT_ASIC_BUG;
638 len = SG_COUNT_ASIC_BUG;
639 prd[idx].addr = cpu_to_le32(addr);
640 prd[idx].flags_len = cpu_to_le32(len);
641 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
642
643 idx++;
644 }
645
646 prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
647}
648
649static void pdc_qc_prep(struct ata_queued_cmd *qc)
650{
651 struct pdc_port_priv *pp = qc->ap->private_data;
652 unsigned int i;
653
654 VPRINTK("ENTER\n");
655
656 switch (qc->tf.protocol) {
657 case ATA_PROT_DMA:
658 pdc_fill_sg(qc);
659
660 case ATA_PROT_NODATA:
661 i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma,
662 qc->dev->devno, pp->pkt);
663 if (qc->tf.flags & ATA_TFLAG_LBA48)
664 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
665 else
666 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
667 pdc_pkt_footer(&qc->tf, pp->pkt, i);
668 break;
669 case ATAPI_PROT_PIO:
670 pdc_fill_sg(qc);
671 break;
672 case ATAPI_PROT_DMA:
673 pdc_fill_sg(qc);
674
675 case ATAPI_PROT_NODATA:
676 pdc_atapi_pkt(qc);
677 break;
678 default:
679 break;
680 }
681}
682
683static int pdc_is_sataii_tx4(unsigned long flags)
684{
685 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
686 return (flags & mask) == mask;
687}
688
689static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
690 int is_sataii_tx4)
691{
692 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
693 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
694}
695
696static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
697{
698 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
699}
700
701static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
702{
703 const struct ata_host *host = ap->host;
704 unsigned int nr_ports = pdc_sata_nr_ports(ap);
705 unsigned int i;
706
707 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
708 ;
709 BUG_ON(i >= nr_ports);
710 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
711}
712
713static void pdc_freeze(struct ata_port *ap)
714{
715 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
716 u32 tmp;
717
718 tmp = readl(ata_mmio + PDC_CTLSTAT);
719 tmp |= PDC_IRQ_DISABLE;
720 tmp &= ~PDC_DMA_ENABLE;
721 writel(tmp, ata_mmio + PDC_CTLSTAT);
722 readl(ata_mmio + PDC_CTLSTAT);
723}
724
725static void pdc_sata_freeze(struct ata_port *ap)
726{
727 struct ata_host *host = ap->host;
728 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
729 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
730 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
731 u32 hotplug_status;
732
733
734
735
736
737
738
739
740 hotplug_status = readl(host_mmio + hotplug_offset);
741 hotplug_status |= 0x11 << (ata_no + 16);
742 writel(hotplug_status, host_mmio + hotplug_offset);
743 readl(host_mmio + hotplug_offset);
744
745 pdc_freeze(ap);
746}
747
748static void pdc_thaw(struct ata_port *ap)
749{
750 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
751 u32 tmp;
752
753
754 readl(ata_mmio + PDC_COMMAND);
755
756
757 tmp = readl(ata_mmio + PDC_CTLSTAT);
758 tmp &= ~PDC_IRQ_DISABLE;
759 writel(tmp, ata_mmio + PDC_CTLSTAT);
760 readl(ata_mmio + PDC_CTLSTAT);
761}
762
763static void pdc_sata_thaw(struct ata_port *ap)
764{
765 struct ata_host *host = ap->host;
766 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
767 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
768 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
769 u32 hotplug_status;
770
771 pdc_thaw(ap);
772
773
774
775
776 hotplug_status = readl(host_mmio + hotplug_offset);
777 hotplug_status |= 0x11 << ata_no;
778 hotplug_status &= ~(0x11 << (ata_no + 16));
779 writel(hotplug_status, host_mmio + hotplug_offset);
780 readl(host_mmio + hotplug_offset);
781}
782
783static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
784 unsigned long deadline)
785{
786 pdc_reset_port(link->ap);
787 return ata_sff_softreset(link, class, deadline);
788}
789
790static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap)
791{
792 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
793 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
794
795
796 return (ata_mmio - host_mmio - 0x200) / 0x80;
797}
798
799static void pdc_hard_reset_port(struct ata_port *ap)
800{
801 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
802 void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1;
803 unsigned int ata_no = pdc_ata_port_to_ata_no(ap);
804 u8 tmp;
805
806 spin_lock(&ap->host->lock);
807
808 tmp = readb(pcictl_b1_mmio);
809 tmp &= ~(0x10 << ata_no);
810 writeb(tmp, pcictl_b1_mmio);
811 readb(pcictl_b1_mmio);
812 udelay(100);
813 tmp |= (0x10 << ata_no);
814 writeb(tmp, pcictl_b1_mmio);
815 readb(pcictl_b1_mmio);
816
817 spin_unlock(&ap->host->lock);
818}
819
820static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
821 unsigned long deadline)
822{
823 if (link->ap->flags & PDC_FLAG_GEN_II)
824 pdc_not_at_command_packet_phase(link->ap);
825
826 pdc_hard_reset_port(link->ap);
827 pdc_reset_port(link->ap);
828
829
830
831
832
833 return sata_std_hardreset(link, class, deadline);
834}
835
836static void pdc_error_handler(struct ata_port *ap)
837{
838 if (!(ap->pflags & ATA_PFLAG_FROZEN))
839 pdc_reset_port(ap);
840
841 ata_sff_error_handler(ap);
842}
843
844static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
845{
846 struct ata_port *ap = qc->ap;
847
848
849 if (qc->flags & ATA_QCFLAG_FAILED)
850 pdc_reset_port(ap);
851}
852
853static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
854 u32 port_status, u32 err_mask)
855{
856 struct ata_eh_info *ehi = &ap->link.eh_info;
857 unsigned int ac_err_mask = 0;
858
859 ata_ehi_clear_desc(ehi);
860 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
861 port_status &= err_mask;
862
863 if (port_status & PDC_DRIVE_ERR)
864 ac_err_mask |= AC_ERR_DEV;
865 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
866 ac_err_mask |= AC_ERR_OTHER;
867 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
868 ac_err_mask |= AC_ERR_ATA_BUS;
869 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
870 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
871 ac_err_mask |= AC_ERR_HOST_BUS;
872
873 if (sata_scr_valid(&ap->link)) {
874 u32 serror;
875
876 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
877 ehi->serror |= serror;
878 }
879
880 qc->err_mask |= ac_err_mask;
881
882 pdc_reset_port(ap);
883
884 ata_port_abort(ap);
885}
886
887static unsigned int pdc_host_intr(struct ata_port *ap,
888 struct ata_queued_cmd *qc)
889{
890 unsigned int handled = 0;
891 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
892 u32 port_status, err_mask;
893
894 err_mask = PDC_ERR_MASK;
895 if (ap->flags & PDC_FLAG_GEN_II)
896 err_mask &= ~PDC1_ERR_MASK;
897 else
898 err_mask &= ~PDC2_ERR_MASK;
899 port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
900 if (unlikely(port_status & err_mask)) {
901 pdc_error_intr(ap, qc, port_status, err_mask);
902 return 1;
903 }
904
905 switch (qc->tf.protocol) {
906 case ATA_PROT_DMA:
907 case ATA_PROT_NODATA:
908 case ATAPI_PROT_DMA:
909 case ATAPI_PROT_NODATA:
910 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
911 ata_qc_complete(qc);
912 handled = 1;
913 break;
914 default:
915 ap->stats.idle_irq++;
916 break;
917 }
918
919 return handled;
920}
921
922static void pdc_irq_clear(struct ata_port *ap)
923{
924 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
925
926 readl(ata_mmio + PDC_COMMAND);
927}
928
929static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
930{
931 struct ata_host *host = dev_instance;
932 struct ata_port *ap;
933 u32 mask = 0;
934 unsigned int i, tmp;
935 unsigned int handled = 0;
936 void __iomem *host_mmio;
937 unsigned int hotplug_offset, ata_no;
938 u32 hotplug_status;
939 int is_sataii_tx4;
940
941 VPRINTK("ENTER\n");
942
943 if (!host || !host->iomap[PDC_MMIO_BAR]) {
944 VPRINTK("QUICK EXIT\n");
945 return IRQ_NONE;
946 }
947
948 host_mmio = host->iomap[PDC_MMIO_BAR];
949
950 spin_lock(&host->lock);
951
952
953 if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
954 hotplug_offset = PDC2_SATA_PLUG_CSR;
955 hotplug_status = readl(host_mmio + hotplug_offset);
956 if (hotplug_status & 0xff)
957 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
958 hotplug_status &= 0xff;
959 } else
960 hotplug_status = 0;
961
962
963 mask = readl(host_mmio + PDC_INT_SEQMASK);
964
965 if (mask == 0xffffffff && hotplug_status == 0) {
966 VPRINTK("QUICK EXIT 2\n");
967 goto done_irq;
968 }
969
970 mask &= 0xffff;
971 if (mask == 0 && hotplug_status == 0) {
972 VPRINTK("QUICK EXIT 3\n");
973 goto done_irq;
974 }
975
976 writel(mask, host_mmio + PDC_INT_SEQMASK);
977
978 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
979
980 for (i = 0; i < host->n_ports; i++) {
981 VPRINTK("port %u\n", i);
982 ap = host->ports[i];
983
984
985 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
986 tmp = hotplug_status & (0x11 << ata_no);
987 if (tmp) {
988 struct ata_eh_info *ehi = &ap->link.eh_info;
989 ata_ehi_clear_desc(ehi);
990 ata_ehi_hotplugged(ehi);
991 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
992 ata_port_freeze(ap);
993 ++handled;
994 continue;
995 }
996
997
998 tmp = mask & (1 << (i + 1));
999 if (tmp) {
1000 struct ata_queued_cmd *qc;
1001
1002 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1003 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1004 handled += pdc_host_intr(ap, qc);
1005 }
1006 }
1007
1008 VPRINTK("EXIT\n");
1009
1010done_irq:
1011 spin_unlock(&host->lock);
1012 return IRQ_RETVAL(handled);
1013}
1014
1015static void pdc_packet_start(struct ata_queued_cmd *qc)
1016{
1017 struct ata_port *ap = qc->ap;
1018 struct pdc_port_priv *pp = ap->private_data;
1019 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
1020 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
1021 unsigned int port_no = ap->port_no;
1022 u8 seq = (u8) (port_no + 1);
1023
1024 VPRINTK("ENTER, ap %p\n", ap);
1025
1026 writel(0x00000001, host_mmio + (seq * 4));
1027 readl(host_mmio + (seq * 4));
1028
1029 pp->pkt[2] = seq;
1030 wmb();
1031 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
1032 readl(ata_mmio + PDC_PKT_SUBMIT);
1033}
1034
1035static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
1036{
1037 switch (qc->tf.protocol) {
1038 case ATAPI_PROT_NODATA:
1039 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1040 break;
1041
1042 case ATA_PROT_NODATA:
1043 if (qc->tf.flags & ATA_TFLAG_POLLING)
1044 break;
1045
1046 case ATAPI_PROT_DMA:
1047 case ATA_PROT_DMA:
1048 pdc_packet_start(qc);
1049 return 0;
1050 default:
1051 break;
1052 }
1053 return ata_sff_qc_issue(qc);
1054}
1055
1056static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1057{
1058 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1059 ata_sff_tf_load(ap, tf);
1060}
1061
1062static void pdc_exec_command_mmio(struct ata_port *ap,
1063 const struct ata_taskfile *tf)
1064{
1065 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1066 ata_sff_exec_command(ap, tf);
1067}
1068
1069static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
1070{
1071 u8 *scsicmd = qc->scsicmd->cmnd;
1072 int pio = 1;
1073
1074
1075 switch (scsicmd[0]) {
1076 case WRITE_12:
1077 case WRITE_10:
1078 case WRITE_6:
1079 case READ_12:
1080 case READ_10:
1081 case READ_6:
1082 case 0xad:
1083 case 0xbe:
1084 pio = 0;
1085 }
1086
1087 if (scsicmd[0] == WRITE_10) {
1088 unsigned int lba =
1089 (scsicmd[2] << 24) |
1090 (scsicmd[3] << 16) |
1091 (scsicmd[4] << 8) |
1092 scsicmd[5];
1093 if (lba >= 0xFFFF4FA2)
1094 pio = 1;
1095 }
1096 return pio;
1097}
1098
1099static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
1100{
1101
1102 return 1;
1103}
1104
1105static void pdc_ata_setup_port(struct ata_port *ap,
1106 void __iomem *base, void __iomem *scr_addr)
1107{
1108 ap->ioaddr.cmd_addr = base;
1109 ap->ioaddr.data_addr = base;
1110 ap->ioaddr.feature_addr =
1111 ap->ioaddr.error_addr = base + 0x4;
1112 ap->ioaddr.nsect_addr = base + 0x8;
1113 ap->ioaddr.lbal_addr = base + 0xc;
1114 ap->ioaddr.lbam_addr = base + 0x10;
1115 ap->ioaddr.lbah_addr = base + 0x14;
1116 ap->ioaddr.device_addr = base + 0x18;
1117 ap->ioaddr.command_addr =
1118 ap->ioaddr.status_addr = base + 0x1c;
1119 ap->ioaddr.altstatus_addr =
1120 ap->ioaddr.ctl_addr = base + 0x38;
1121 ap->ioaddr.scr_addr = scr_addr;
1122}
1123
1124static void pdc_host_init(struct ata_host *host)
1125{
1126 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
1127 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1128 int hotplug_offset;
1129 u32 tmp;
1130
1131 if (is_gen2)
1132 hotplug_offset = PDC2_SATA_PLUG_CSR;
1133 else
1134 hotplug_offset = PDC_SATA_PLUG_CSR;
1135
1136
1137
1138
1139
1140
1141
1142
1143 tmp = readl(host_mmio + PDC_FLASH_CTL);
1144 tmp |= 0x02000;
1145 if (!is_gen2)
1146 tmp |= 0x10000;
1147 writel(tmp, host_mmio + PDC_FLASH_CTL);
1148
1149
1150 tmp = readl(host_mmio + hotplug_offset);
1151 writel(tmp | 0xff, host_mmio + hotplug_offset);
1152
1153 tmp = readl(host_mmio + hotplug_offset);
1154 if (is_gen2)
1155 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1156 else
1157 writel(tmp | 0xff0000, host_mmio + hotplug_offset);
1158
1159
1160 if (is_gen2)
1161 return;
1162
1163
1164 tmp = readl(host_mmio + PDC_TBG_MODE);
1165 tmp &= ~0x30000;
1166 tmp |= 0x10000;
1167 writel(tmp, host_mmio + PDC_TBG_MODE);
1168
1169 readl(host_mmio + PDC_TBG_MODE);
1170 msleep(10);
1171
1172
1173 tmp = readl(host_mmio + PDC_SLEW_CTL);
1174 tmp &= 0xFFFFF03F;
1175 tmp |= 0x00000900;
1176 writel(tmp, host_mmio + PDC_SLEW_CTL);
1177}
1178
1179static int pdc_ata_init_one(struct pci_dev *pdev,
1180 const struct pci_device_id *ent)
1181{
1182 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1183 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1184 struct ata_host *host;
1185 void __iomem *host_mmio;
1186 int n_ports, i, rc;
1187 int is_sataii_tx4;
1188
1189 ata_print_version_once(&pdev->dev, DRV_VERSION);
1190
1191
1192 rc = pcim_enable_device(pdev);
1193 if (rc)
1194 return rc;
1195
1196 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1197 if (rc == -EBUSY)
1198 pcim_pin_device(pdev);
1199 if (rc)
1200 return rc;
1201 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1202
1203
1204 n_ports = 2;
1205 if (pi->flags & PDC_FLAG_4_PORTS)
1206 n_ports = 4;
1207 for (i = 0; i < n_ports; i++)
1208 ppi[i] = pi;
1209
1210 if (pi->flags & PDC_FLAG_SATA_PATA) {
1211 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
1212 if (!(tmp & 0x80))
1213 ppi[n_ports++] = pi + 1;
1214 }
1215
1216 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1217 if (!host) {
1218 dev_err(&pdev->dev, "failed to allocate host\n");
1219 return -ENOMEM;
1220 }
1221 host->iomap = pcim_iomap_table(pdev);
1222
1223 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1224 for (i = 0; i < host->n_ports; i++) {
1225 struct ata_port *ap = host->ports[i];
1226 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1227 unsigned int ata_offset = 0x200 + ata_no * 0x80;
1228 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1229
1230 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
1231
1232 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1233 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
1234 }
1235
1236
1237 pdc_host_init(host);
1238
1239 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1240 if (rc)
1241 return rc;
1242 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1243 if (rc)
1244 return rc;
1245
1246
1247 pci_set_master(pdev);
1248 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1249 &pdc_ata_sht);
1250}
1251
1252module_pci_driver(pdc_ata_pci_driver);
1253
1254MODULE_AUTHOR("Jeff Garzik");
1255MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1256MODULE_LICENSE("GPL");
1257MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1258MODULE_VERSION(DRV_VERSION);
1259
