LXR linux/drivers/bcma/driver_chipcommon

   1/*
   2 * Broadcom specific AMBA
   3 * ChipCommon Power Management Unit driver
   4 *
   5 * Copyright 2009, Michael Buesch <m@bues.ch>
   6 * Copyright 2007, 2011, Broadcom Corporation
   7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
   8 *
   9 * Licensed under the GNU/GPL. See COPYING for details.
  10 */
  11
  12#include "bcma_private.h"
  13#include <linux/export.h>
  14#include <linux/bcma/bcma.h>
  15
  16static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
  17{
  18        bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  19        bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  20        return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
  21}
  22
  23void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
  24{
  25        bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  26        bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  27        bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
  28}
  29EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
  30
  31void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
  32                             u32 set)
  33{
  34        bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  35        bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  36        bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
  37}
  38EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
  39
  40void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
  41                                 u32 offset, u32 mask, u32 set)
  42{
  43        bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
  44        bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
  45        bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
  46}
  47EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
  48
  49void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
  50                                u32 set)
  51{
  52        bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
  53        bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
  54        bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
  55}
  56EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
  57
  58static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
  59{
  60        struct bcma_bus *bus = cc->core->bus;
  61        u32 min_msk = 0, max_msk = 0;
  62
  63        switch (bus->chipinfo.id) {
  64        case BCMA_CHIP_ID_BCM4313:
  65                min_msk = 0x200D;
  66                max_msk = 0xFFFF;
  67                break;
  68        default:
  69                bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
  70                           bus->chipinfo.id);
  71        }
  72
  73        /* Set the resource masks. */
  74        if (min_msk)
  75                bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
  76        if (max_msk)
  77                bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
  78
  79        /*
  80         * Add some delay; allow resources to come up and settle.
  81         * Delay is required for SoC (early init).
  82         */
  83        mdelay(2);
  84}
  85
  86/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
  87void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
  88{
  89        struct bcma_bus *bus = cc->core->bus;
  90        u32 val;
  91
  92        val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
  93        if (enable) {
  94                val |= BCMA_CHIPCTL_4331_EXTPA_EN;
  95                if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
  96                        val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
  97                else if (bus->chipinfo.rev > 0)
  98                        val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
  99        } else {
 100                val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
 101                val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
 102                val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
 103        }
 104        bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
 105}
 106
 107static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
 108{
 109        struct bcma_bus *bus = cc->core->bus;
 110
 111        switch (bus->chipinfo.id) {
 112        case BCMA_CHIP_ID_BCM4313:
 113                /* enable 12 mA drive strenth for 4313 and set chipControl
 114                   register bit 1 */
 115                bcma_chipco_chipctl_maskset(cc, 0,
 116                                            ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
 117                                            BCMA_CCTRL_4313_12MA_LED_DRIVE);
 118                break;
 119        case BCMA_CHIP_ID_BCM4331:
 120        case BCMA_CHIP_ID_BCM43431:
 121                /* Ext PA lines must be enabled for tx on BCM4331 */
 122                bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
 123                break;
 124        case BCMA_CHIP_ID_BCM43224:
 125        case BCMA_CHIP_ID_BCM43421:
 126                /* enable 12 mA drive strenth for 43224 and set chipControl
 127                   register bit 15 */
 128                if (bus->chipinfo.rev == 0) {
 129                        bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
 130                                          ~BCMA_CCTRL_43224_GPIO_TOGGLE,
 131                                          BCMA_CCTRL_43224_GPIO_TOGGLE);
 132                        bcma_chipco_chipctl_maskset(cc, 0,
 133                                                    ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
 134                                                    BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
 135                } else {
 136                        bcma_chipco_chipctl_maskset(cc, 0,
 137                                                    ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
 138                                                    BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
 139                }
 140                break;
 141        default:
 142                bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
 143                           bus->chipinfo.id);
 144        }
 145}
 146
 147void bcma_pmu_init(struct bcma_drv_cc *cc)
 148{
 149        u32 pmucap;
 150
 151        pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
 152        cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
 153
 154        bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
 155                   cc->pmu.rev, pmucap);
 156
 157        if (cc->pmu.rev == 1)
 158                bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
 159                              ~BCMA_CC_PMU_CTL_NOILPONW);
 160        else
 161                bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
 162                             BCMA_CC_PMU_CTL_NOILPONW);
 163
 164        bcma_pmu_resources_init(cc);
 165        bcma_pmu_workarounds(cc);
 166}
 167
 168u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
 169{
 170        struct bcma_bus *bus = cc->core->bus;
 171
 172        switch (bus->chipinfo.id) {
 173        case BCMA_CHIP_ID_BCM4716:
 174        case BCMA_CHIP_ID_BCM4748:
 175        case BCMA_CHIP_ID_BCM47162:
 176        case BCMA_CHIP_ID_BCM4313:
 177        case BCMA_CHIP_ID_BCM5357:
 178        case BCMA_CHIP_ID_BCM4749:
 179        case BCMA_CHIP_ID_BCM53572:
 180                /* always 20Mhz */
 181                return 20000 * 1000;
 182        case BCMA_CHIP_ID_BCM5356:
 183        case BCMA_CHIP_ID_BCM4706:
 184                /* always 25Mhz */
 185                return 25000 * 1000;
 186        default:
 187                bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
 188                          bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
 189        }
 190        return BCMA_CC_PMU_ALP_CLOCK;
 191}
 192
 193/* Find the output of the "m" pll divider given pll controls that start with
 194 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
 195 */
 196static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 197{
 198        u32 tmp, div, ndiv, p1, p2, fc;
 199        struct bcma_bus *bus = cc->core->bus;
 200
 201        BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
 202
 203        BUG_ON(!m || m > 4);
 204
 205        if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
 206            bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
 207                /* Detect failure in clock setting */
 208                tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
 209                if (tmp & 0x40000)
 210                        return 133 * 1000000;
 211        }
 212
 213        tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
 214        p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
 215        p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
 216
 217        tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
 218        div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
 219                BCMA_CC_PPL_MDIV_MASK;
 220
 221        tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
 222        ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
 223
 224        /* Do calculation in Mhz */
 225        fc = bcma_pmu_alp_clock(cc) / 1000000;
 226        fc = (p1 * ndiv * fc) / p2;
 227
 228        /* Return clock in Hertz */
 229        return (fc / div) * 1000000;
 230}
 231
 232static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 233{
 234        u32 tmp, ndiv, p1div, p2div;
 235        u32 clock;
 236
 237        BUG_ON(!m || m > 4);
 238
 239        /* Get N, P1 and P2 dividers to determine CPU clock */
 240        tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
 241        ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
 242                >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
 243        p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
 244                >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
 245        p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
 246                >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
 247
 248        tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
 249        if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
 250                /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
 251                clock = (25000000 / 4) * ndiv * p2div / p1div;
 252        else
 253                /* Fixed reference clock 25MHz and m = 2 */
 254                clock = (25000000 / 2) * ndiv * p2div / p1div;
 255
 256        if (m == BCMA_CC_PMU5_MAINPLL_SSB)
 257                clock = clock / 4;
 258
 259        return clock;
 260}
 261
 262/* query bus clock frequency for PMU-enabled chipcommon */
 263static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
 264{
 265        struct bcma_bus *bus = cc->core->bus;
 266
 267        switch (bus->chipinfo.id) {
 268        case BCMA_CHIP_ID_BCM4716:
 269        case BCMA_CHIP_ID_BCM4748:
 270        case BCMA_CHIP_ID_BCM47162:
 271                return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
 272                                      BCMA_CC_PMU5_MAINPLL_SSB);
 273        case BCMA_CHIP_ID_BCM5356:
 274                return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
 275                                      BCMA_CC_PMU5_MAINPLL_SSB);
 276        case BCMA_CHIP_ID_BCM5357:
 277        case BCMA_CHIP_ID_BCM4749:
 278                return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
 279                                      BCMA_CC_PMU5_MAINPLL_SSB);
 280        case BCMA_CHIP_ID_BCM4706:
 281                return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
 282                                              BCMA_CC_PMU5_MAINPLL_SSB);
 283        case BCMA_CHIP_ID_BCM53572:
 284                return 75000000;
 285        default:
 286                bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
 287                          bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
 288        }
 289        return BCMA_CC_PMU_HT_CLOCK;
 290}
 291
 292/* query cpu clock frequency for PMU-enabled chipcommon */
 293u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
 294{
 295        struct bcma_bus *bus = cc->core->bus;
 296
 297        if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
 298                return 300000000;
 299
 300        if (cc->pmu.rev >= 5) {
 301                u32 pll;
 302                switch (bus->chipinfo.id) {
 303                case BCMA_CHIP_ID_BCM4706:
 304                        return bcma_pmu_clock_bcm4706(cc,
 305                                                BCMA_CC_PMU4706_MAINPLL_PLL0,
 306                                                BCMA_CC_PMU5_MAINPLL_CPU);
 307                case BCMA_CHIP_ID_BCM5356:
 308                        pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
 309                        break;
 310                case BCMA_CHIP_ID_BCM5357:
 311                case BCMA_CHIP_ID_BCM4749:
 312                        pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
 313                        break;
 314                default:
 315                        pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
 316                        break;
 317                }
 318
 319                return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
 320        }
 321
 322        return bcma_pmu_get_clockcontrol(cc);
 323}
 324
 325static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
 326                                         u32 value)
 327{
 328        bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
 329        bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
 330}
 331
 332void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
 333{
 334        u32 tmp = 0;
 335        u8 phypll_offset = 0;
 336        u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
 337        u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
 338        struct bcma_bus *bus = cc->core->bus;
 339
 340        switch (bus->chipinfo.id) {
 341        case BCMA_CHIP_ID_BCM5357:
 342        case BCMA_CHIP_ID_BCM4749:
 343        case BCMA_CHIP_ID_BCM53572:
 344                /* 5357[ab]0, 43236[ab]0, and 6362b0 */
 345
 346                /* BCM5357 needs to touch PLL1_PLLCTL[02],
 347                   so offset PLL0_PLLCTL[02] by 6 */
 348                phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
 349                       bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
 350                       bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
 351
 352                /* RMW only the P1 divider */
 353                bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
 354                                BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
 355                tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
 356                tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
 357                tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
 358                bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
 359
 360                /* RMW only the int feedback divider */
 361                bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
 362                                BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
 363                tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
 364                tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
 365                tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
 366                bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
 367
 368                tmp = 1 << 10;
 369                break;
 370
 371        case BCMA_CHIP_ID_BCM4331:
 372        case BCMA_CHIP_ID_BCM43431:
 373                if (spuravoid == 2) {
 374                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 375                                                     0x11500014);
 376                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 377                                                     0x0FC00a08);
 378                } else if (spuravoid == 1) {
 379                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 380                                                     0x11500014);
 381                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 382                                                     0x0F600a08);
 383                } else {
 384                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 385                                                     0x11100014);
 386                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 387                                                     0x03000a08);
 388                }
 389                tmp = 1 << 10;
 390                break;
 391
 392        case BCMA_CHIP_ID_BCM43224:
 393        case BCMA_CHIP_ID_BCM43225:
 394        case BCMA_CHIP_ID_BCM43421:
 395                if (spuravoid == 1) {
 396                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 397                                                     0x11500010);
 398                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 399                                                     0x000C0C06);
 400                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 401                                                     0x0F600a08);
 402                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 403                                                     0x00000000);
 404                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 405                                                     0x2001E920);
 406                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 407                                                     0x88888815);
 408                } else {
 409                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 410                                                     0x11100010);
 411                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 412                                                     0x000c0c06);
 413                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 414                                                     0x03000a08);
 415                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 416                                                     0x00000000);
 417                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 418                                                     0x200005c0);
 419                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 420                                                     0x88888815);
 421                }
 422                tmp = 1 << 10;
 423                break;
 424
 425        case BCMA_CHIP_ID_BCM4716:
 426        case BCMA_CHIP_ID_BCM4748:
 427        case BCMA_CHIP_ID_BCM47162:
 428                if (spuravoid == 1) {
 429                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 430                                                     0x11500060);
 431                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 432                                                     0x080C0C06);
 433                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 434                                                     0x0F600000);
 435                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 436                                                     0x00000000);
 437                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 438                                                     0x2001E924);
 439                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 440                                                     0x88888815);
 441                } else {
 442                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 443                                                     0x11100060);
 444                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 445                                                     0x080c0c06);
 446                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 447                                                     0x03000000);
 448                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 449                                                     0x00000000);
 450                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 451                                                     0x200005c0);
 452                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 453                                                     0x88888815);
 454                }
 455
 456                tmp = 3 << 9;
 457                break;
 458
 459        case BCMA_CHIP_ID_BCM43227:
 460        case BCMA_CHIP_ID_BCM43228:
 461        case BCMA_CHIP_ID_BCM43428:
 462                /* LCNXN */
 463                /* PLL Settings for spur avoidance on/off mode,
 464                   no on2 support for 43228A0 */
 465                if (spuravoid == 1) {
 466                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 467                                                     0x01100014);
 468                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 469                                                     0x040C0C06);
 470                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 471                                                     0x03140A08);
 472                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 473                                                     0x00333333);
 474                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 475                                                     0x202C2820);
 476                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 477                                                     0x88888815);
 478                } else {
 479                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 480                                                     0x11100014);
 481                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 482                                                     0x040c0c06);
 483                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 484                                                     0x03000a08);
 485                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 486                                                     0x00000000);
 487                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 488                                                     0x200005c0);
 489                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 490                                                     0x88888815);
 491                }
 492                tmp = 1 << 10;
 493                break;
 494        default:
 495                bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
 496                         bus->chipinfo.id);
 497                break;
 498        }
 499
 500        tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
 501        bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
 502}
 503EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
 504