linux/drivers/clk/mxs/clk-imx23.c
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   1/*
   2 * Copyright 2012 Freescale Semiconductor, Inc.
   3 *
   4 * The code contained herein is licensed under the GNU General Public
   5 * License. You may obtain a copy of the GNU General Public License
   6 * Version 2 or later at the following locations:
   7 *
   8 * http://www.opensource.org/licenses/gpl-license.html
   9 * http://www.gnu.org/copyleft/gpl.html
  10 */
  11
  12#include <linux/clk.h>
  13#include <linux/clkdev.h>
  14#include <linux/err.h>
  15#include <linux/init.h>
  16#include <linux/io.h>
  17#include <linux/of.h>
  18#include <mach/common.h>
  19#include <mach/mx23.h>
  20#include "clk.h"
  21
  22#define DIGCTRL                 MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
  23#define CLKCTRL                 MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
  24#define PLLCTRL0                (CLKCTRL + 0x0000)
  25#define CPU                     (CLKCTRL + 0x0020)
  26#define HBUS                    (CLKCTRL + 0x0030)
  27#define XBUS                    (CLKCTRL + 0x0040)
  28#define XTAL                    (CLKCTRL + 0x0050)
  29#define PIX                     (CLKCTRL + 0x0060)
  30#define SSP                     (CLKCTRL + 0x0070)
  31#define GPMI                    (CLKCTRL + 0x0080)
  32#define SPDIF                   (CLKCTRL + 0x0090)
  33#define EMI                     (CLKCTRL + 0x00a0)
  34#define SAIF                    (CLKCTRL + 0x00c0)
  35#define TV                      (CLKCTRL + 0x00d0)
  36#define ETM                     (CLKCTRL + 0x00e0)
  37#define FRAC                    (CLKCTRL + 0x00f0)
  38#define CLKSEQ                  (CLKCTRL + 0x0110)
  39
  40#define BP_CPU_INTERRUPT_WAIT   12
  41#define BP_CLKSEQ_BYPASS_SAIF   0
  42#define BP_CLKSEQ_BYPASS_SSP    5
  43#define BP_SAIF_DIV_FRAC_EN     16
  44#define BP_FRAC_IOFRAC          24
  45
  46static void __init clk_misc_init(void)
  47{
  48        u32 val;
  49
  50        /* Gate off cpu clock in WFI for power saving */
  51        __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU);
  52
  53        /* Clear BYPASS for SAIF */
  54        __mxs_clrl(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ);
  55
  56        /* SAIF has to use frac div for functional operation */
  57        val = readl_relaxed(SAIF);
  58        val |= 1 << BP_SAIF_DIV_FRAC_EN;
  59        writel_relaxed(val, SAIF);
  60
  61        /*
  62         * Source ssp clock from ref_io than ref_xtal,
  63         * as ref_xtal only provides 24 MHz as maximum.
  64         */
  65        __mxs_clrl(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ);
  66
  67        /*
  68         * 480 MHz seems too high to be ssp clock source directly,
  69         * so set frac to get a 288 MHz ref_io.
  70         */
  71        __mxs_clrl(0x3f << BP_FRAC_IOFRAC, FRAC);
  72        __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC);
  73}
  74
  75static const char *sel_pll[]  __initconst = { "pll", "ref_xtal", };
  76static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
  77static const char *sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
  78static const char *sel_io[]   __initconst = { "ref_io", "ref_xtal", };
  79static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
  80static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
  81
  82enum imx23_clk {
  83        ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel,
  84        lcdif_sel, gpmi_sel, ssp_sel, emi_sel, cpu, etm_sel, cpu_pll,
  85        cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll,
  86        emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div,
  87        clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif,
  88        lcdif, etm, usb, usb_pwr,
  89        clk_max
  90};
  91
  92static struct clk *clks[clk_max];
  93static struct clk_onecell_data clk_data;
  94
  95static enum imx23_clk clks_init_on[] __initdata = {
  96        cpu, hbus, xbus, emi, uart,
  97};
  98
  99int __init mx23_clocks_init(void)
 100{
 101        struct device_node *np;
 102        int i;
 103
 104        clk_misc_init();
 105
 106        clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
 107        clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000);
 108        clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0);
 109        clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1);
 110        clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2);
 111        clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3);
 112        clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll));
 113        clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix));
 114        clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io));
 115        clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io));
 116        clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels));
 117        clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
 118        clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
 119        clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
 120        clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
 121        clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29);
 122        clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
 123        clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29);
 124        clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29);
 125        clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
 126        clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
 127        clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
 128        clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29);
 129        clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29);
 130        clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
 131        clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
 132        clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16);
 133        clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4);
 134        clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
 135        clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28);
 136        clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
 137        clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30);
 138        clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
 139        clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31);
 140        clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
 141        clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
 142        clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
 143        clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);
 144        clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);
 145        clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
 146        clks[usb] = mxs_clk_gate("usb", "usb_pwr", DIGCTRL, 2);
 147        clks[usb_pwr] = clk_register_gate(NULL, "usb_pwr", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock);
 148
 149        for (i = 0; i < ARRAY_SIZE(clks); i++)
 150                if (IS_ERR(clks[i])) {
 151                        pr_err("i.MX23 clk %d: register failed with %ld\n",
 152                                i, PTR_ERR(clks[i]));
 153                        return PTR_ERR(clks[i]);
 154                }
 155
 156        np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
 157        if (np) {
 158                clk_data.clks = clks;
 159                clk_data.clk_num = ARRAY_SIZE(clks);
 160                of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 161        }
 162
 163        clk_register_clkdev(clks[clk32k], NULL, "timrot");
 164
 165        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 166                clk_prepare_enable(clks[clks_init_on[i]]);
 167
 168        mxs_timer_init();
 169
 170        return 0;
 171}
 172