1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17#ifndef __PSB_INTEL_REG_H__
18#define __PSB_INTEL_REG_H__
19
20
21
22
23#define GPIOA 0x5010
24#define GPIOB 0x5014
25#define GPIOC 0x5018
26#define GPIOD 0x501c
27#define GPIOE 0x5020
28#define GPIOF 0x5024
29#define GPIOG 0x5028
30#define GPIOH 0x502c
31# define GPIO_CLOCK_DIR_MASK (1 << 0)
32# define GPIO_CLOCK_DIR_IN (0 << 1)
33# define GPIO_CLOCK_DIR_OUT (1 << 1)
34# define GPIO_CLOCK_VAL_MASK (1 << 2)
35# define GPIO_CLOCK_VAL_OUT (1 << 3)
36# define GPIO_CLOCK_VAL_IN (1 << 4)
37# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
38# define GPIO_DATA_DIR_MASK (1 << 8)
39# define GPIO_DATA_DIR_IN (0 << 9)
40# define GPIO_DATA_DIR_OUT (1 << 9)
41# define GPIO_DATA_VAL_MASK (1 << 10)
42# define GPIO_DATA_VAL_OUT (1 << 11)
43# define GPIO_DATA_VAL_IN (1 << 12)
44# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
45
46#define GMBUS0 0x5100
47#define GMBUS_RATE_100KHZ (0<<8)
48#define GMBUS_RATE_50KHZ (1<<8)
49#define GMBUS_RATE_400KHZ (2<<8)
50#define GMBUS_RATE_1MHZ (3<<8)
51#define GMBUS_HOLD_EXT (1<<7)
52#define GMBUS_PORT_DISABLED 0
53#define GMBUS_PORT_SSC 1
54#define GMBUS_PORT_VGADDC 2
55#define GMBUS_PORT_PANEL 3
56#define GMBUS_PORT_DPC 4
57#define GMBUS_PORT_DPB 5
58
59#define GMBUS_PORT_DPD 7
60#define GMBUS_NUM_PORTS 8
61#define GMBUS1 0x5104
62#define GMBUS_SW_CLR_INT (1<<31)
63#define GMBUS_SW_RDY (1<<30)
64#define GMBUS_ENT (1<<29)
65#define GMBUS_CYCLE_NONE (0<<25)
66#define GMBUS_CYCLE_WAIT (1<<25)
67#define GMBUS_CYCLE_INDEX (2<<25)
68#define GMBUS_CYCLE_STOP (4<<25)
69#define GMBUS_BYTE_COUNT_SHIFT 16
70#define GMBUS_SLAVE_INDEX_SHIFT 8
71#define GMBUS_SLAVE_ADDR_SHIFT 1
72#define GMBUS_SLAVE_READ (1<<0)
73#define GMBUS_SLAVE_WRITE (0<<0)
74#define GMBUS2 0x5108
75#define GMBUS_INUSE (1<<15)
76#define GMBUS_HW_WAIT_PHASE (1<<14)
77#define GMBUS_STALL_TIMEOUT (1<<13)
78#define GMBUS_INT (1<<12)
79#define GMBUS_HW_RDY (1<<11)
80#define GMBUS_SATOER (1<<10)
81#define GMBUS_ACTIVE (1<<9)
82#define GMBUS3 0x510c
83#define GMBUS4 0x5110
84#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
85#define GMBUS_NAK_EN (1<<3)
86#define GMBUS_IDLE_EN (1<<2)
87#define GMBUS_HW_WAIT_EN (1<<1)
88#define GMBUS_HW_RDY_EN (1<<0)
89#define GMBUS5 0x5120
90#define GMBUS_2BYTE_INDEX_EN (1<<31)
91
92#define BLC_PWM_CTL 0x61254
93#define BLC_PWM_CTL2 0x61250
94#define PWM_ENABLE (1 << 31)
95#define PWM_LEGACY_MODE (1 << 30)
96#define PWM_PIPE_B (1 << 29)
97#define BLC_PWM_CTL_C 0x62254
98#define BLC_PWM_CTL2_C 0x62250
99#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
100
101
102
103
104
105
106#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
107#define BLM_LEGACY_MODE (1 << 16)
108
109
110
111
112
113
114
115#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
116#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
117
118#define I915_GCFGC 0xf0
119#define I915_LOW_FREQUENCY_ENABLE (1 << 7)
120#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
121#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
122#define I915_DISPLAY_CLOCK_MASK (7 << 4)
123
124#define I855_HPLLCC 0xc0
125#define I855_CLOCK_CONTROL_MASK (3 << 0)
126#define I855_CLOCK_133_200 (0 << 0)
127#define I855_CLOCK_100_200 (1 << 0)
128#define I855_CLOCK_100_133 (2 << 0)
129#define I855_CLOCK_166_250 (3 << 0)
130
131
132#define HTOTAL_A 0x60000
133#define HBLANK_A 0x60004
134#define HSYNC_A 0x60008
135#define VTOTAL_A 0x6000c
136#define VBLANK_A 0x60010
137#define VSYNC_A 0x60014
138#define PIPEASRC 0x6001c
139#define BCLRPAT_A 0x60020
140#define VSYNCSHIFT_A 0x60028
141
142#define HTOTAL_B 0x61000
143#define HBLANK_B 0x61004
144#define HSYNC_B 0x61008
145#define VTOTAL_B 0x6100c
146#define VBLANK_B 0x61010
147#define VSYNC_B 0x61014
148#define PIPEBSRC 0x6101c
149#define BCLRPAT_B 0x61020
150#define VSYNCSHIFT_B 0x61028
151
152#define HTOTAL_C 0x62000
153#define HBLANK_C 0x62004
154#define HSYNC_C 0x62008
155#define VTOTAL_C 0x6200c
156#define VBLANK_C 0x62010
157#define VSYNC_C 0x62014
158#define PIPECSRC 0x6201c
159#define BCLRPAT_C 0x62020
160#define VSYNCSHIFT_C 0x62028
161
162#define PP_STATUS 0x61200
163# define PP_ON (1 << 31)
164
165
166
167
168
169
170
171#define PP_READY (1 << 30)
172#define PP_SEQUENCE_NONE (0 << 28)
173#define PP_SEQUENCE_ON (1 << 28)
174#define PP_SEQUENCE_OFF (2 << 28)
175#define PP_SEQUENCE_MASK 0x30000000
176#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
177#define PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
178#define PP_SEQUENCE_STATE_MASK 0x0000000f
179
180#define PP_CONTROL 0x61204
181#define POWER_TARGET_ON (1 << 0)
182#define PANEL_UNLOCK_REGS (0xabcd << 16)
183#define PANEL_UNLOCK_MASK (0xffff << 16)
184#define EDP_FORCE_VDD (1 << 3)
185#define EDP_BLC_ENABLE (1 << 2)
186#define PANEL_POWER_RESET (1 << 1)
187#define PANEL_POWER_OFF (0 << 0)
188#define PANEL_POWER_ON (1 << 0)
189
190
191#define LVDSPP_ON 0x61208
192#define LVDSPP_OFF 0x6120c
193#define PP_CYCLE 0x61210
194
195
196#define PP_ON_DELAYS 0x61208
197#define PANEL_PORT_SELECT_MASK (3 << 30)
198#define PANEL_PORT_SELECT_LVDS (0 << 30)
199#define PANEL_PORT_SELECT_EDP (1 << 30)
200#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
201#define PANEL_POWER_UP_DELAY_SHIFT 16
202#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
203#define PANEL_LIGHT_ON_DELAY_SHIFT 0
204
205#define PP_OFF_DELAYS 0x6120c
206#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
207#define PANEL_POWER_DOWN_DELAY_SHIFT 16
208#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
209#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
210
211#define PP_DIVISOR 0x61210
212#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
213#define PP_REFERENCE_DIVIDER_SHIFT 8
214#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
215#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
216
217#define PFIT_CONTROL 0x61230
218#define PFIT_ENABLE (1 << 31)
219#define PFIT_PIPE_MASK (3 << 29)
220#define PFIT_PIPE_SHIFT 29
221#define PFIT_SCALING_MODE_PILLARBOX (1 << 27)
222#define PFIT_SCALING_MODE_LETTERBOX (3 << 26)
223#define VERT_INTERP_DISABLE (0 << 10)
224#define VERT_INTERP_BILINEAR (1 << 10)
225#define VERT_INTERP_MASK (3 << 10)
226#define VERT_AUTO_SCALE (1 << 9)
227#define HORIZ_INTERP_DISABLE (0 << 6)
228#define HORIZ_INTERP_BILINEAR (1 << 6)
229#define HORIZ_INTERP_MASK (3 << 6)
230#define HORIZ_AUTO_SCALE (1 << 5)
231#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
232
233#define PFIT_PGM_RATIOS 0x61234
234#define PFIT_VERT_SCALE_MASK 0xfff00000
235#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
236
237#define PFIT_AUTO_RATIOS 0x61238
238
239#define DPLL_A 0x06014
240#define DPLL_B 0x06018
241#define DPLL_VCO_ENABLE (1 << 31)
242#define DPLL_DVO_HIGH_SPEED (1 << 30)
243#define DPLL_SYNCLOCK_ENABLE (1 << 29)
244#define DPLL_VGA_MODE_DIS (1 << 28)
245#define DPLLB_MODE_DAC_SERIAL (1 << 26)
246#define DPLLB_MODE_LVDS (2 << 26)
247#define DPLL_MODE_MASK (3 << 26)
248#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24)
249#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24)
250#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24)
251#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24)
252#define DPLL_P2_CLOCK_DIV_MASK 0x03000000
253#define DPLL_FPA0h1_P1_POST_DIV_MASK 0x00ff0000
254#define DPLL_LOCK (1 << 15)
255
256
257
258
259
260# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
261
262
263
264
265#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
266#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
267#define PLL_P2_DIVIDE_BY_4 (1 << 23)
268
269# define PLL_P1_DIVIDE_BY_TWO (1 << 21)
270#define PLL_REF_INPUT_DREFCLK (0 << 13)
271#define PLL_REF_INPUT_TVCLKINA (1 << 13)
272#define PLL_REF_INPUT_TVCLKINBC (2 << 13)
273
274#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
275#define PLL_REF_INPUT_MASK (3 << 13)
276#define PLL_LOAD_PULSE_PHASE_SHIFT 9
277
278
279
280
281
282
283#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
284#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
285
286
287
288
289
290
291#define SDVO_MULTIPLIER_MASK 0x000000ff
292#define SDVO_MULTIPLIER_SHIFT_HIRES 4
293#define SDVO_MULTIPLIER_SHIFT_VGA 0
294
295
296
297
298
299#define DPLL_A_MD 0x0601c
300
301#define DPLL_B_MD 0x06020
302
303
304
305
306
307#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
308#define DPLL_MD_UDI_DIVIDER_SHIFT 24
309
310#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
311#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
330#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
331
332
333
334
335
336#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
337#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
338
339#define DPLL_TEST 0x606c
340#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
341#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
342#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
343#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
344#define DPLLB_TEST_N_BYPASS (1 << 19)
345#define DPLLB_TEST_M_BYPASS (1 << 18)
346#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
347#define DPLLA_TEST_N_BYPASS (1 << 3)
348#define DPLLA_TEST_M_BYPASS (1 << 2)
349#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
350
351#define ADPA 0x61100
352#define ADPA_DAC_ENABLE (1 << 31)
353#define ADPA_DAC_DISABLE 0
354#define ADPA_PIPE_SELECT_MASK (1 << 30)
355#define ADPA_PIPE_A_SELECT 0
356#define ADPA_PIPE_B_SELECT (1 << 30)
357#define ADPA_USE_VGA_HVPOLARITY (1 << 15)
358#define ADPA_SETS_HVPOLARITY 0
359#define ADPA_VSYNC_CNTL_DISABLE (1 << 11)
360#define ADPA_VSYNC_CNTL_ENABLE 0
361#define ADPA_HSYNC_CNTL_DISABLE (1 << 10)
362#define ADPA_HSYNC_CNTL_ENABLE 0
363#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
364#define ADPA_VSYNC_ACTIVE_LOW 0
365#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
366#define ADPA_HSYNC_ACTIVE_LOW 0
367
368#define FPA0 0x06040
369#define FPA1 0x06044
370#define FPB0 0x06048
371#define FPB1 0x0604c
372#define FP_N_DIV_MASK 0x003f0000
373#define FP_N_DIV_SHIFT 16
374#define FP_M1_DIV_MASK 0x00003f00
375#define FP_M1_DIV_SHIFT 8
376#define FP_M2_DIV_MASK 0x0000003f
377#define FP_M2_DIV_SHIFT 0
378
379#define PORT_HOTPLUG_EN 0x61110
380#define HDMIB_HOTPLUG_INT_EN (1 << 29)
381#define HDMIC_HOTPLUG_INT_EN (1 << 28)
382#define HDMID_HOTPLUG_INT_EN (1 << 27)
383#define SDVOB_HOTPLUG_INT_EN (1 << 26)
384#define SDVOC_HOTPLUG_INT_EN (1 << 25)
385#define TV_HOTPLUG_INT_EN (1 << 18)
386#define CRT_HOTPLUG_INT_EN (1 << 9)
387#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
388
389#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
390#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
391#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
392#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
393#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
394#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
395#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
396#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
397#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
398#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
399#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
400#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
401#define CRT_HOTPLUG_DETECT_MASK 0x000000F8
402
403#define PORT_HOTPLUG_STAT 0x61114
404#define CRT_HOTPLUG_INT_STATUS (1 << 11)
405#define TV_HOTPLUG_INT_STATUS (1 << 10)
406#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
407#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
408#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
409#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
410#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
411#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
412
413#define SDVOB 0x61140
414#define SDVOC 0x61160
415#define SDVO_ENABLE (1 << 31)
416#define SDVO_PIPE_B_SELECT (1 << 30)
417#define SDVO_STALL_SELECT (1 << 29)
418#define SDVO_INTERRUPT_ENABLE (1 << 26)
419#define SDVO_COLOR_RANGE_16_235 (1 << 8)
420#define SDVO_AUDIO_ENABLE (1 << 6)
421
422
423
424
425
426
427
428
429#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
430#define SDVO_PORT_MULTIPLY_SHIFT 23
431#define SDVO_PHASE_SELECT_MASK (15 << 19)
432#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
433#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
434#define SDVOC_GANG_MODE (1 << 16)
435#define SDVO_BORDER_ENABLE (1 << 7)
436#define SDVOB_PCIE_CONCURRENCY (1 << 3)
437#define SDVO_DETECTED (1 << 2)
438
439#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
440#define SDVOC_PRESERVE_MASK (1 << 17)
441
442
443
444
445
446
447
448#define LVDS 0x61180
449
450
451
452
453#define LVDS_PORT_EN (1 << 31)
454
455#define LVDS_PIPEB_SELECT (1 << 30)
456
457
458#define LVDS_BORDER_EN (1 << 15)
459
460
461
462
463
464#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
465#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
466#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
467
468
469
470
471
472#define LVDS_A3_POWER_MASK (3 << 6)
473#define LVDS_A3_POWER_DOWN (0 << 6)
474#define LVDS_A3_POWER_UP (3 << 6)
475
476
477
478
479#define LVDS_CLKB_POWER_MASK (3 << 4)
480#define LVDS_CLKB_POWER_DOWN (0 << 4)
481#define LVDS_CLKB_POWER_UP (3 << 4)
482
483
484
485
486
487#define LVDS_B0B3_POWER_MASK (3 << 2)
488#define LVDS_B0B3_POWER_DOWN (0 << 2)
489#define LVDS_B0B3_POWER_UP (3 << 2)
490
491#define PIPEACONF 0x70008
492#define PIPEACONF_ENABLE (1 << 31)
493#define PIPEACONF_DISABLE 0
494#define PIPEACONF_DOUBLE_WIDE (1 << 30)
495#define PIPECONF_ACTIVE (1 << 30)
496#define I965_PIPECONF_ACTIVE (1 << 30)
497#define PIPECONF_DSIPLL_LOCK (1 << 29)
498#define PIPEACONF_SINGLE_WIDE 0
499#define PIPEACONF_PIPE_UNLOCKED 0
500#define PIPEACONF_DSR (1 << 26)
501#define PIPEACONF_PIPE_LOCKED (1 << 25)
502#define PIPEACONF_PALETTE 0
503#define PIPECONF_FORCE_BORDER (1 << 25)
504#define PIPEACONF_GAMMA (1 << 24)
505#define PIPECONF_PROGRESSIVE (0 << 21)
506#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
507#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
508#define PIPECONF_PLANE_OFF (1 << 19)
509#define PIPECONF_CURSOR_OFF (1 << 18)
510
511#define PIPEBCONF 0x71008
512#define PIPEBCONF_ENABLE (1 << 31)
513#define PIPEBCONF_DISABLE 0
514#define PIPEBCONF_DOUBLE_WIDE (1 << 30)
515#define PIPEBCONF_DISABLE 0
516#define PIPEBCONF_GAMMA (1 << 24)
517#define PIPEBCONF_PALETTE 0
518
519#define PIPECCONF 0x72008
520
521#define PIPEBGCMAXRED 0x71010
522#define PIPEBGCMAXGREEN 0x71014
523#define PIPEBGCMAXBLUE 0x71018
524
525#define PIPEASTAT 0x70024
526#define PIPEBSTAT 0x71024
527#define PIPECSTAT 0x72024
528#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
529#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2)
530#define PIPE_VBLANK_CLEAR (1 << 1)
531#define PIPE_VBLANK_STATUS (1 << 1)
532#define PIPE_TE_STATUS (1UL << 6)
533#define PIPE_DPST_EVENT_STATUS (1UL << 7)
534#define PIPE_VSYNC_CLEAR (1UL << 9)
535#define PIPE_VSYNC_STATUS (1UL << 9)
536#define PIPE_HDMI_AUDIO_UNDERRUN_STATUS (1UL << 10)
537#define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL << 11)
538#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
539#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18)
540#define PIPE_TE_ENABLE (1UL << 22)
541#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
542#define PIPE_DPST_EVENT_ENABLE (1UL << 23)
543#define PIPE_VSYNC_ENABL (1UL << 25)
544#define PIPE_HDMI_AUDIO_UNDERRUN (1UL << 26)
545#define PIPE_HDMI_AUDIO_BUFFER_DONE (1UL << 27)
546#define PIPE_FIFO_UNDERRUN (1UL << 31)
547#define PIPE_HDMI_AUDIO_INT_MASK (PIPE_HDMI_AUDIO_UNDERRUN | \
548 PIPE_HDMI_AUDIO_BUFFER_DONE)
549#define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16))
550#define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17))
551#define HISTOGRAM_INT_CONTROL 0x61268
552#define HISTOGRAM_BIN_DATA 0X61264
553#define HISTOGRAM_LOGIC_CONTROL 0x61260
554#define PWM_CONTROL_LOGIC 0x61250
555#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
556#define HISTOGRAM_INTERRUPT_ENABLE (1UL << 31)
557#define HISTOGRAM_LOGIC_ENABLE (1UL << 31)
558#define PWM_LOGIC_ENABLE (1UL << 31)
559#define PWM_PHASEIN_ENABLE (1UL << 25)
560#define PWM_PHASEIN_INT_ENABLE (1UL << 24)
561#define PWM_PHASEIN_VB_COUNT 0x00001f00
562#define PWM_PHASEIN_INC 0x0000001f
563#define HISTOGRAM_INT_CTRL_CLEAR (1UL << 30)
564#define DPST_YUV_LUMA_MODE 0
565
566struct dpst_ie_histogram_control {
567 union {
568 uint32_t data;
569 struct {
570 uint32_t bin_reg_index:7;
571 uint32_t reserved:4;
572 uint32_t bin_reg_func_select:1;
573 uint32_t sync_to_phase_in:1;
574 uint32_t alt_enhancement_mode:2;
575 uint32_t reserved1:1;
576 uint32_t sync_to_phase_in_count:8;
577 uint32_t histogram_mode_select:1;
578 uint32_t reserved2:4;
579 uint32_t ie_pipe_assignment:1;
580 uint32_t ie_mode_table_enabled:1;
581 uint32_t ie_histogram_enable:1;
582 };
583 };
584};
585
586struct dpst_guardband {
587 union {
588 uint32_t data;
589 struct {
590 uint32_t guardband:22;
591 uint32_t guardband_interrupt_delay:8;
592 uint32_t interrupt_status:1;
593 uint32_t interrupt_enable:1;
594 };
595 };
596};
597
598#define PIPEAFRAMEHIGH 0x70040
599#define PIPEAFRAMEPIXEL 0x70044
600#define PIPEBFRAMEHIGH 0x71040
601#define PIPEBFRAMEPIXEL 0x71044
602#define PIPECFRAMEHIGH 0x72040
603#define PIPECFRAMEPIXEL 0x72044
604#define PIPE_FRAME_HIGH_MASK 0x0000ffff
605#define PIPE_FRAME_HIGH_SHIFT 0
606#define PIPE_FRAME_LOW_MASK 0xff000000
607#define PIPE_FRAME_LOW_SHIFT 24
608#define PIPE_PIXEL_MASK 0x00ffffff
609#define PIPE_PIXEL_SHIFT 0
610
611#define FW_BLC_SELF 0x20e0
612#define FW_BLC_SELF_EN (1<<15)
613
614#define DSPARB 0x70030
615#define DSPFW1 0x70034
616#define DSP_FIFO_SR_WM_MASK 0xFF800000
617#define DSP_FIFO_SR_WM_SHIFT 23
618#define CURSOR_B_FIFO_WM_MASK 0x003F0000
619#define CURSOR_B_FIFO_WM_SHIFT 16
620#define DSPFW2 0x70038
621#define CURSOR_A_FIFO_WM_MASK 0x3F00
622#define CURSOR_A_FIFO_WM_SHIFT 8
623#define DSP_PLANE_C_FIFO_WM_MASK 0x7F
624#define DSP_PLANE_C_FIFO_WM_SHIFT 0
625#define DSPFW3 0x7003c
626#define DSPFW4 0x70050
627#define DSPFW5 0x70054
628#define DSP_PLANE_B_FIFO_WM1_SHIFT 24
629#define DSP_PLANE_A_FIFO_WM1_SHIFT 16
630#define CURSOR_B_FIFO_WM1_SHIFT 8
631#define CURSOR_FIFO_SR_WM1_SHIFT 0
632#define DSPFW6 0x70058
633#define DSPCHICKENBIT 0x70400
634#define DSPACNTR 0x70180
635#define DSPBCNTR 0x71180
636#define DSPCCNTR 0x72180
637#define DISPLAY_PLANE_ENABLE (1 << 31)
638#define DISPLAY_PLANE_DISABLE 0
639#define DISPPLANE_GAMMA_ENABLE (1 << 30)
640#define DISPPLANE_GAMMA_DISABLE 0
641#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
642#define DISPPLANE_8BPP (0x2 << 26)
643#define DISPPLANE_15_16BPP (0x4 << 26)
644#define DISPPLANE_16BPP (0x5 << 26)
645#define DISPPLANE_32BPP_NO_ALPHA (0x6 << 26)
646#define DISPPLANE_32BPP (0x7 << 26)
647#define DISPPLANE_STEREO_ENABLE (1 << 25)
648#define DISPPLANE_STEREO_DISABLE 0
649#define DISPPLANE_SEL_PIPE_MASK (1 << 24)
650#define DISPPLANE_SEL_PIPE_POS 24
651#define DISPPLANE_SEL_PIPE_A 0
652#define DISPPLANE_SEL_PIPE_B (1 << 24)
653#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
654#define DISPPLANE_SRC_KEY_DISABLE 0
655#define DISPPLANE_LINE_DOUBLE (1 << 20)
656#define DISPPLANE_NO_LINE_DOUBLE 0
657#define DISPPLANE_STEREO_POLARITY_FIRST 0
658#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
659
660#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
661#define DISPPLANE_ALPHA_TRANS_DISABLE 0
662#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
663#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
664#define DISPPLANE_BOTTOM (4)
665
666#define DSPABASE 0x70184
667#define DSPALINOFF 0x70184
668#define DSPASTRIDE 0x70188
669
670#define DSPBBASE 0x71184
671#define DSPBLINOFF 0X71184
672#define DSPBADDR DSPBBASE
673#define DSPBSTRIDE 0x71188
674
675#define DSPCBASE 0x72184
676#define DSPCLINOFF 0x72184
677#define DSPCSTRIDE 0x72188
678
679#define DSPAKEYVAL 0x70194
680#define DSPAKEYMASK 0x70198
681
682#define DSPAPOS 0x7018C
683#define DSPASIZE 0x70190
684#define DSPBPOS 0x7118C
685#define DSPBSIZE 0x71190
686#define DSPCPOS 0x7218C
687#define DSPCSIZE 0x72190
688
689#define DSPASURF 0x7019C
690#define DSPATILEOFF 0x701A4
691
692#define DSPBSURF 0x7119C
693#define DSPBTILEOFF 0x711A4
694
695#define DSPCSURF 0x7219C
696#define DSPCTILEOFF 0x721A4
697#define DSPCKEYMAXVAL 0x721A0
698#define DSPCKEYMINVAL 0x72194
699#define DSPCKEYMSK 0x72198
700
701#define VGACNTRL 0x71400
702#define VGA_DISP_DISABLE (1 << 31)
703#define VGA_2X_MODE (1 << 30)
704#define VGA_PIPE_B_SELECT (1 << 29)
705
706
707
708
709#define OV_C_OFFSET 0x08000
710#define OV_OVADD 0x30000
711#define OV_DOVASTA 0x30008
712# define OV_PIPE_SELECT ((1 << 6)|(1 << 7))
713# define OV_PIPE_SELECT_POS 6
714# define OV_PIPE_A 0
715# define OV_PIPE_C 1
716#define OV_OGAMC5 0x30010
717#define OV_OGAMC4 0x30014
718#define OV_OGAMC3 0x30018
719#define OV_OGAMC2 0x3001C
720#define OV_OGAMC1 0x30020
721#define OV_OGAMC0 0x30024
722#define OVC_OVADD 0x38000
723#define OVC_DOVCSTA 0x38008
724#define OVC_OGAMC5 0x38010
725#define OVC_OGAMC4 0x38014
726#define OVC_OGAMC3 0x38018
727#define OVC_OGAMC2 0x3801C
728#define OVC_OGAMC1 0x38020
729#define OVC_OGAMC0 0x38024
730
731
732
733
734
735#define SWF0 0x71410
736#define SWF1 0x71414
737#define SWF2 0x71418
738#define SWF3 0x7141c
739#define SWF4 0x71420
740#define SWF5 0x71424
741#define SWF6 0x71428
742
743
744
745
746#define SWF00 0x70410
747#define SWF01 0x70414
748#define SWF02 0x70418
749#define SWF03 0x7041c
750#define SWF04 0x70420
751#define SWF05 0x70424
752#define SWF06 0x70428
753
754#define SWF10 SWF0
755#define SWF11 SWF1
756#define SWF12 SWF2
757#define SWF13 SWF3
758#define SWF14 SWF4
759#define SWF15 SWF5
760#define SWF16 SWF6
761
762#define SWF30 0x72414
763#define SWF31 0x72418
764#define SWF32 0x7241c
765
766
767
768
769
770#define PALETTE_A 0x0a000
771#define PALETTE_B 0x0a800
772#define PALETTE_C 0x0ac00
773
774
775#define CURACNTR 0x70080
776#define CURSOR_MODE_DISABLE 0x00
777#define CURSOR_MODE_64_32B_AX 0x07
778#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
779#define MCURSOR_GAMMA_ENABLE (1 << 26)
780#define CURABASE 0x70084
781#define CURAPOS 0x70088
782#define CURSOR_POS_MASK 0x007FF
783#define CURSOR_POS_SIGN 0x8000
784#define CURSOR_X_SHIFT 0
785#define CURSOR_Y_SHIFT 16
786#define CURBCNTR 0x700c0
787#define CURBBASE 0x700c4
788#define CURBPOS 0x700c8
789#define CURCCNTR 0x700e0
790#define CURCBASE 0x700e4
791#define CURCPOS 0x700e8
792
793
794
795
796#define IER 0x020a0
797#define IIR 0x020a4
798#define IMR 0x020a8
799#define ISR 0x020ac
800
801
802
803
804#define MRST_DPLL_A 0x0f014
805#define MDFLD_DPLL_B 0x0f018
806#define MDFLD_INPUT_REF_SEL (1 << 14)
807#define MDFLD_VCO_SEL (1 << 16)
808#define DPLLA_MODE_LVDS (2 << 26)
809#define MDFLD_PLL_LATCHEN (1 << 28)
810#define MDFLD_PWR_GATE_EN (1 << 30)
811#define MDFLD_P1_MASK (0x1FF << 17)
812#define MRST_FPA0 0x0f040
813#define MRST_FPA1 0x0f044
814#define MDFLD_DPLL_DIV0 0x0f048
815#define MDFLD_DPLL_DIV1 0x0f04c
816#define MRST_PERF_MODE 0x020f4
817
818
819
820
821#define HDMIPHYMISCCTL 0x61134
822#define HDMI_PHY_POWER_DOWN 0x7f
823#define HDMIB_CONTROL 0x61140
824#define HDMIB_PORT_EN (1 << 31)
825#define HDMIB_PIPE_B_SELECT (1 << 30)
826#define HDMIB_NULL_PACKET (1 << 9)
827#define HDMIB_HDCP_PORT (1 << 5)
828
829
830#define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25)
831#define MRST_PANEL_24_DOT_1_FORMAT (1 << 24)
832#define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6)
833
834#define MIPI 0x61190
835#define MIPI_C 0x62190
836#define MIPI_PORT_EN (1 << 31)
837
838#define SEL_FLOPPED_HSTX (1 << 23)
839#define PASS_FROM_SPHY_TO_AFE (1 << 16)
840#define MIPI_BORDER_EN (1 << 15)
841#define MIPIA_3LANE_MIPIC_1LANE 0x1
842#define MIPIA_2LANE_MIPIC_2LANE 0x2
843#define TE_TRIGGER_DSI_PROTOCOL (1 << 2)
844#define TE_TRIGGER_GPIO_PIN (1 << 3)
845#define MIPI_TE_COUNT 0x61194
846
847
848#define POWER_DOWN_ON_RESET (1 << 1)
849
850
851#define PFIT_PIPE_SELECT (3 << 29)
852#define PFIT_PIPE_SELECT_SHIFT (29)
853
854
855#define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16)
856#define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16)
857
858
859#define PIPEACONF_PIPE_STATE (1 << 30)
860
861
862#define MRST_DSPABASE 0x7019c
863#define MRST_DSPBBASE 0x7119c
864#define MDFLD_DSPCBASE 0x7219c
865
866
867
868
869
870
871
872
873#define MIPIC_REG_OFFSET 0x800
874
875#define DEVICE_READY_REG 0xb000
876#define LP_OUTPUT_HOLD (1 << 16)
877#define EXIT_ULPS_DEV_READY 0x3
878#define LP_OUTPUT_HOLD_RELEASE 0x810000
879# define ENTERING_ULPS (2 << 1)
880# define EXITING_ULPS (1 << 1)
881# define ULPS_MASK (3 << 1)
882# define BUS_POSSESSION (1 << 3)
883#define INTR_STAT_REG 0xb004
884#define RX_SOT_ERROR (1 << 0)
885#define RX_SOT_SYNC_ERROR (1 << 1)
886#define RX_ESCAPE_MODE_ENTRY_ERROR (1 << 3)
887#define RX_LP_TX_SYNC_ERROR (1 << 4)
888#define RX_HS_RECEIVE_TIMEOUT_ERROR (1 << 5)
889#define RX_FALSE_CONTROL_ERROR (1 << 6)
890#define RX_ECC_SINGLE_BIT_ERROR (1 << 7)
891#define RX_ECC_MULTI_BIT_ERROR (1 << 8)
892#define RX_CHECKSUM_ERROR (1 << 9)
893#define RX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 10)
894#define RX_DSI_VC_ID_INVALID (1 << 11)
895#define TX_FALSE_CONTROL_ERROR (1 << 12)
896#define TX_ECC_SINGLE_BIT_ERROR (1 << 13)
897#define TX_ECC_MULTI_BIT_ERROR (1 << 14)
898#define TX_CHECKSUM_ERROR (1 << 15)
899#define TX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 16)
900#define TX_DSI_VC_ID_INVALID (1 << 17)
901#define HIGH_CONTENTION (1 << 18)
902#define LOW_CONTENTION (1 << 19)
903#define DPI_FIFO_UNDER_RUN (1 << 20)
904#define HS_TX_TIMEOUT (1 << 21)
905#define LP_RX_TIMEOUT (1 << 22)
906#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
907#define ACK_WITH_NO_ERROR (1 << 24)
908#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
909#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
910#define SPL_PKT_SENT (1 << 30)
911#define INTR_EN_REG 0xb008
912#define DSI_FUNC_PRG_REG 0xb00c
913#define DPI_CHANNEL_NUMBER_POS 0x03
914#define DBI_CHANNEL_NUMBER_POS 0x05
915#define FMT_DPI_POS 0x07
916#define FMT_DBI_POS 0x0A
917#define DBI_DATA_WIDTH_POS 0x0D
918
919
920#define RGB_565_FMT 0x01
921#define RGB_666_FMT 0x02
922#define LRGB_666_FMT 0x03
923
924
925#define RGB_888_FMT 0x04
926#define VIRTUAL_CHANNEL_NUMBER_0 0x00
927#define VIRTUAL_CHANNEL_NUMBER_1 0x01
928#define VIRTUAL_CHANNEL_NUMBER_2 0x02
929#define VIRTUAL_CHANNEL_NUMBER_3 0x03
930
931#define DBI_NOT_SUPPORTED 0x00
932
933
934#define DBI_DATA_WIDTH_16BIT 0x01
935#define DBI_DATA_WIDTH_9BIT 0x02
936#define DBI_DATA_WIDTH_8BIT 0x03
937#define DBI_DATA_WIDTH_OPT1 0x04
938#define DBI_DATA_WIDTH_OPT2 0x05
939
940#define HS_TX_TIMEOUT_REG 0xb010
941#define LP_RX_TIMEOUT_REG 0xb014
942#define TURN_AROUND_TIMEOUT_REG 0xb018
943#define DEVICE_RESET_REG 0xb01C
944#define DPI_RESOLUTION_REG 0xb020
945#define RES_V_POS 0x10
946#define DBI_RESOLUTION_REG 0xb024
947#define HORIZ_SYNC_PAD_COUNT_REG 0xb028
948#define HORIZ_BACK_PORCH_COUNT_REG 0xb02C
949#define HORIZ_FRONT_PORCH_COUNT_REG 0xb030
950#define HORIZ_ACTIVE_AREA_COUNT_REG 0xb034
951#define VERT_SYNC_PAD_COUNT_REG 0xb038
952#define VERT_BACK_PORCH_COUNT_REG 0xb03c
953#define VERT_FRONT_PORCH_COUNT_REG 0xb040
954#define HIGH_LOW_SWITCH_COUNT_REG 0xb044
955#define DPI_CONTROL_REG 0xb048
956#define DPI_SHUT_DOWN (1 << 0)
957#define DPI_TURN_ON (1 << 1)
958#define DPI_COLOR_MODE_ON (1 << 2)
959#define DPI_COLOR_MODE_OFF (1 << 3)
960#define DPI_BACK_LIGHT_ON (1 << 4)
961#define DPI_BACK_LIGHT_OFF (1 << 5)
962#define DPI_LP (1 << 6)
963#define DPI_DATA_REG 0xb04c
964#define DPI_BACK_LIGHT_ON_DATA 0x07
965#define DPI_BACK_LIGHT_OFF_DATA 0x17
966#define INIT_COUNT_REG 0xb050
967#define MAX_RET_PAK_REG 0xb054
968#define VIDEO_FMT_REG 0xb058
969#define COMPLETE_LAST_PCKT (1 << 2)
970#define EOT_DISABLE_REG 0xb05c
971#define ENABLE_CLOCK_STOPPING (1 << 1)
972#define LP_BYTECLK_REG 0xb060
973#define LP_GEN_DATA_REG 0xb064
974#define HS_GEN_DATA_REG 0xb068
975#define LP_GEN_CTRL_REG 0xb06C
976#define HS_GEN_CTRL_REG 0xb070
977#define DCS_CHANNEL_NUMBER_POS 0x6
978#define MCS_COMMANDS_POS 0x8
979#define WORD_COUNTS_POS 0x8
980#define MCS_PARAMETER_POS 0x10
981#define GEN_FIFO_STAT_REG 0xb074
982#define HS_DATA_FIFO_FULL (1 << 0)
983#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
984#define HS_DATA_FIFO_EMPTY (1 << 2)
985#define LP_DATA_FIFO_FULL (1 << 8)
986#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
987#define LP_DATA_FIFO_EMPTY (1 << 10)
988#define HS_CTRL_FIFO_FULL (1 << 16)
989#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
990#define HS_CTRL_FIFO_EMPTY (1 << 18)
991#define LP_CTRL_FIFO_FULL (1 << 24)
992#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
993#define LP_CTRL_FIFO_EMPTY (1 << 26)
994#define DBI_FIFO_EMPTY (1 << 27)
995#define DPI_FIFO_EMPTY (1 << 28)
996#define HS_LS_DBI_ENABLE_REG 0xb078
997#define TXCLKESC_REG 0xb07c
998#define DPHY_PARAM_REG 0xb080
999#define DBI_BW_CTRL_REG 0xb084
1000#define CLK_LANE_SWT_REG 0xb088
1001
1002
1003
1004
1005#define MIPI_CONTROL_REG 0xb104
1006#define MIPI_2X_CLOCK_BITS ((1 << 0) | (1 << 1))
1007#define MIPI_DATA_ADDRESS_REG 0xb108
1008#define MIPI_DATA_LENGTH_REG 0xb10C
1009#define MIPI_COMMAND_ADDRESS_REG 0xb110
1010#define MIPI_COMMAND_LENGTH_REG 0xb114
1011#define MIPI_READ_DATA_RETURN_REG0 0xb118
1012#define MIPI_READ_DATA_RETURN_REG1 0xb11C
1013#define MIPI_READ_DATA_RETURN_REG2 0xb120
1014#define MIPI_READ_DATA_RETURN_REG3 0xb124
1015#define MIPI_READ_DATA_RETURN_REG4 0xb128
1016#define MIPI_READ_DATA_RETURN_REG5 0xb12C
1017#define MIPI_READ_DATA_RETURN_REG6 0xb130
1018#define MIPI_READ_DATA_RETURN_REG7 0xb134
1019#define MIPI_READ_DATA_VALID_REG 0xb138
1020
1021
1022#define soft_reset 0x01
1023
1024
1025
1026
1027#define get_power_mode 0x0a
1028
1029
1030
1031#define get_address_mode 0x0b
1032
1033
1034
1035#define get_pixel_format 0x0c
1036
1037
1038
1039
1040#define get_display_mode 0x0d
1041
1042
1043
1044#define get_signal_mode 0x0e
1045
1046
1047
1048#define get_diagnostic_result 0x0f
1049
1050
1051
1052
1053#define enter_sleep_mode 0x10
1054
1055
1056
1057
1058
1059
1060#define exit_sleep_mode 0x11
1061
1062
1063
1064
1065#define enter_partial_mode 0x12
1066
1067
1068
1069
1070
1071#define enter_normal_mode 0x13
1072
1073
1074
1075
1076#define exit_invert_mode 0x20
1077
1078
1079
1080
1081
1082#define enter_invert_mode 0x21
1083
1084
1085
1086
1087
1088#define set_gamma_curve 0x26
1089
1090
1091
1092
1093#define set_display_off 0x28
1094
1095
1096
1097
1098
1099#define set_display_on 0x29
1100
1101
1102
1103
1104
1105#define set_column_address 0x2a
1106
1107
1108
1109
1110
1111
1112#define set_page_addr 0x2b
1113
1114
1115
1116
1117
1118
1119#define write_mem_start 0x2c
1120
1121
1122
1123
1124
1125#define set_partial_area 0x30
1126
1127
1128
1129
1130
1131
1132#define set_scroll_area 0x33
1133
1134
1135
1136#define set_tear_off 0x34
1137
1138
1139
1140
1141#define set_tear_on 0x35
1142
1143
1144
1145
1146#define set_address_mode 0x36
1147
1148
1149
1150
1151
1152#define set_scroll_start 0x37
1153
1154
1155
1156
1157
1158
1159
1160
1161#define exit_idle_mode 0x38
1162
1163
1164
1165#define enter_idle_mode 0x39
1166
1167
1168
1169
1170
1171
1172#define set_pixel_format 0x3a
1173
1174
1175
1176
1177
1178
1179
1180#define DCS_PIXEL_FORMAT_3bpp 0x1
1181#define DCS_PIXEL_FORMAT_8bpp 0x2
1182#define DCS_PIXEL_FORMAT_12bpp 0x3
1183#define DCS_PIXEL_FORMAT_16bpp 0x5
1184#define DCS_PIXEL_FORMAT_18bpp 0x6
1185#define DCS_PIXEL_FORMAT_24bpp 0x7
1186
1187#define write_mem_cont 0x3c
1188
1189
1190
1191
1192
1193
1194
1195#define set_tear_scanline 0x44
1196
1197
1198
1199
1200#define get_scanline 0x45
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211#define GEN_SHORT_WRITE_0 0x03
1212#define GEN_SHORT_WRITE_1 0x13
1213#define GEN_SHORT_WRITE_2 0x23
1214#define GEN_READ_0 0x04
1215#define GEN_READ_1 0x14
1216#define GEN_READ_2 0x24
1217#define GEN_LONG_WRITE 0x29
1218#define MCS_SHORT_WRITE_0 0x05
1219#define MCS_SHORT_WRITE_1 0x15
1220#define MCS_READ 0x06
1221#define MCS_LONG_WRITE 0x39
1222
1223
1224#define write_display_profile 0x50
1225#define write_display_brightness 0x51
1226#define write_ctrl_display 0x53
1227#define write_ctrl_cabc 0x55
1228 #define UI_IMAGE 0x01
1229 #define STILL_IMAGE 0x02
1230 #define MOVING_IMAGE 0x03
1231#define write_hysteresis 0x57
1232#define write_gamma_setting 0x58
1233#define write_cabc_min_bright 0x5e
1234#define write_kbbc_profile 0x60
1235
1236#define tmd_write_display_brightness 0x8c
1237
1238
1239
1240
1241
1242#define BRIGHT_CNTL_BLOCK_ON (1 << 5)
1243#define AMBIENT_LIGHT_SENSE_ON (1 << 4)
1244#define DISPLAY_DIMMING_ON (1 << 3)
1245#define BACKLIGHT_ON (1 << 2)
1246#define DISPLAY_BRIGHTNESS_AUTO (1 << 1)
1247#define GAMMA_AUTO (1 << 0)
1248
1249
1250#define DCS_PIXEL_FORMAT_3BPP 0x1
1251#define DCS_PIXEL_FORMAT_8BPP 0x2
1252#define DCS_PIXEL_FORMAT_12BPP 0x3
1253#define DCS_PIXEL_FORMAT_16BPP 0x5
1254#define DCS_PIXEL_FORMAT_18BPP 0x6
1255#define DCS_PIXEL_FORMAT_24BPP 0x7
1256
1257#define addr_mode_data 0xfc
1258#define diag_res_data 0x00
1259#define disp_mode_data 0x23
1260#define pxl_fmt_data 0x77
1261#define pwr_mode_data 0x74
1262#define sig_mode_data 0x00
1263
1264#define scanline_data1 0xff
1265#define scanline_data2 0xff
1266#define NON_BURST_MODE_SYNC_PULSE 0x01
1267
1268
1269#define NON_BURST_MODE_SYNC_EVENTS 0x02
1270
1271
1272#define BURST_MODE 0x03
1273#define DBI_COMMAND_BUFFER_SIZE 0x240
1274
1275
1276
1277
1278#define DBI_DATA_BUFFER_SIZE 0x120
1279
1280
1281
1282#define DBI_CB_TIME_OUT 0xFFFF
1283
1284#define GEN_FB_TIME_OUT 2000
1285
1286#define SKU_83 0x01
1287#define SKU_100 0x02
1288#define SKU_100L 0x04
1289#define SKU_BYPASS 0x08
1290
1291
1292#define PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
1293#define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK)
1294#define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
1295
1296#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
1297
1298
1299
1300#define SB_PCKT 0x02100
1301# define SB_OPCODE_MASK PSB_MASK(31, 16)
1302# define SB_OPCODE_SHIFT 16
1303# define SB_OPCODE_READ 0
1304# define SB_OPCODE_WRITE 1
1305# define SB_DEST_MASK PSB_MASK(15, 8)
1306# define SB_DEST_SHIFT 8
1307# define SB_DEST_DPLL 0x88
1308# define SB_BYTE_ENABLE_MASK PSB_MASK(7, 4)
1309# define SB_BYTE_ENABLE_SHIFT 4
1310# define SB_BUSY (1 << 0)
1311
1312#define DSPCLK_GATE_D 0x6200
1313# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
1314# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1315# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6)
1316# define DPUNIT_PIPEB_GATE_DISABLE (1 << 30)
1317# define DPUNIT_PIPEA_GATE_DISABLE (1 << 25)
1318# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24)
1319# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13)
1320
1321#define RAMCLK_GATE_D 0x6210
1322
1323
1324#define SB_DATA 0x02104
1325
1326#define SB_ADDR 0x02108
1327#define DPIO_CFG 0x02110
1328# define DPIO_MODE_SELECT_1 (1 << 3)
1329# define DPIO_MODE_SELECT_0 (1 << 2)
1330# define DPIO_SFR_BYPASS (1 << 1)
1331
1332# define DPIO_CMN_RESET_N (1 << 0)
1333
1334
1335#define _SB_M_A 0x8008
1336#define _SB_M_B 0x8028
1337#define SB_M(pipe) _PIPE(pipe, _SB_M_A, _SB_M_B)
1338# define SB_M_DIVIDER_MASK (0xFF << 24)
1339# define SB_M_DIVIDER_SHIFT 24
1340
1341#define _SB_N_VCO_A 0x8014
1342#define _SB_N_VCO_B 0x8034
1343#define SB_N_VCO(pipe) _PIPE(pipe, _SB_N_VCO_A, _SB_N_VCO_B)
1344#define SB_N_VCO_SEL_MASK PSB_MASK(31, 30)
1345#define SB_N_VCO_SEL_SHIFT 30
1346#define SB_N_DIVIDER_MASK PSB_MASK(29, 26)
1347#define SB_N_DIVIDER_SHIFT 26
1348#define SB_N_CB_TUNE_MASK PSB_MASK(25, 24)
1349#define SB_N_CB_TUNE_SHIFT 24
1350
1351
1352#define SB_REF_DPLLA 0x8010
1353#define SB_REF_DPLLB 0x8030
1354#define REF_CLK_MASK (0x3 << 13)
1355#define REF_CLK_CORE (0 << 13)
1356#define REF_CLK_DPLL (1 << 13)
1357#define REF_CLK_DPLLA (2 << 13)
1358
1359
1360#define _SB_REF_A 0x8018
1361#define _SB_REF_B 0x8038
1362#define SB_REF_SFR(pipe) _PIPE(pipe, _SB_REF_A, _SB_REF_B)
1363
1364#define _SB_P_A 0x801c
1365#define _SB_P_B 0x803c
1366#define SB_P(pipe) _PIPE(pipe, _SB_P_A, _SB_P_B)
1367#define SB_P2_DIVIDER_MASK PSB_MASK(31, 30)
1368#define SB_P2_DIVIDER_SHIFT 30
1369#define SB_P2_10 0
1370#define SB_P2_5 1
1371#define SB_P2_14 2
1372#define SB_P2_7 3
1373#define SB_P1_DIVIDER_MASK PSB_MASK(15, 12)
1374#define SB_P1_DIVIDER_SHIFT 12
1375
1376#define PSB_LANE0 0x120
1377#define PSB_LANE1 0x220
1378#define PSB_LANE2 0x2320
1379#define PSB_LANE3 0x2420
1380
1381#define LANE_PLL_MASK (0x7 << 20)
1382#define LANE_PLL_ENABLE (0x3 << 20)
1383#define LANE_PLL_PIPE(p) (((p) == 0) ? (1 << 21) : (0 << 21))
1384
1385#define DP_B 0x64100
1386#define DP_C 0x64200
1387
1388#define DP_PORT_EN (1 << 31)
1389#define DP_PIPEB_SELECT (1 << 30)
1390#define DP_PIPE_MASK (1 << 30)
1391
1392
1393#define DP_LINK_TRAIN_PAT_1 (0 << 28)
1394#define DP_LINK_TRAIN_PAT_2 (1 << 28)
1395#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
1396#define DP_LINK_TRAIN_OFF (3 << 28)
1397#define DP_LINK_TRAIN_MASK (3 << 28)
1398#define DP_LINK_TRAIN_SHIFT 28
1399
1400
1401#define DP_VOLTAGE_0_4 (0 << 25)
1402#define DP_VOLTAGE_0_6 (1 << 25)
1403#define DP_VOLTAGE_0_8 (2 << 25)
1404#define DP_VOLTAGE_1_2 (3 << 25)
1405#define DP_VOLTAGE_MASK (7 << 25)
1406#define DP_VOLTAGE_SHIFT 25
1407
1408
1409
1410
1411#define DP_PRE_EMPHASIS_0 (0 << 22)
1412#define DP_PRE_EMPHASIS_3_5 (1 << 22)
1413#define DP_PRE_EMPHASIS_6 (2 << 22)
1414#define DP_PRE_EMPHASIS_9_5 (3 << 22)
1415#define DP_PRE_EMPHASIS_MASK (7 << 22)
1416#define DP_PRE_EMPHASIS_SHIFT 22
1417
1418
1419#define DP_PORT_WIDTH_1 (0 << 19)
1420#define DP_PORT_WIDTH_2 (1 << 19)
1421#define DP_PORT_WIDTH_4 (3 << 19)
1422#define DP_PORT_WIDTH_MASK (7 << 19)
1423
1424
1425#define DP_ENHANCED_FRAMING (1 << 18)
1426
1427
1428#define DP_PORT_REVERSAL (1 << 15)
1429
1430
1431#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1432
1433#define DP_SCRAMBLING_DISABLE (1 << 12)
1434#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
1435
1436
1437#define DP_COLOR_RANGE_16_235 (1 << 8)
1438
1439
1440#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
1441
1442
1443#define DP_SYNC_VS_HIGH (1 << 4)
1444#define DP_SYNC_HS_HIGH (1 << 3)
1445
1446
1447#define DP_DETECTED (1 << 2)
1448
1449
1450
1451
1452
1453
1454#define DPB_AUX_CH_CTL 0x64110
1455#define DPB_AUX_CH_DATA1 0x64114
1456#define DPB_AUX_CH_DATA2 0x64118
1457#define DPB_AUX_CH_DATA3 0x6411c
1458#define DPB_AUX_CH_DATA4 0x64120
1459#define DPB_AUX_CH_DATA5 0x64124
1460
1461#define DPC_AUX_CH_CTL 0x64210
1462#define DPC_AUX_CH_DATA1 0x64214
1463#define DPC_AUX_CH_DATA2 0x64218
1464#define DPC_AUX_CH_DATA3 0x6421c
1465#define DPC_AUX_CH_DATA4 0x64220
1466#define DPC_AUX_CH_DATA5 0x64224
1467
1468#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
1469#define DP_AUX_CH_CTL_DONE (1 << 30)
1470#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
1471#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
1472#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
1473#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
1474#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
1475#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
1476#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
1477#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
1478#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
1479#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
1480#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
1481#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
1482#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
1483#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
1484#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
1485#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
1486#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
1487#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
1488#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504#define _PIPEA_GMCH_DATA_M 0x70050
1505#define _PIPEB_GMCH_DATA_M 0x71050
1506
1507
1508#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
1509#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
1510
1511#define PIPE_GMCH_DATA_M_MASK (0xffffff)
1512
1513#define _PIPEA_GMCH_DATA_N 0x70054
1514#define _PIPEB_GMCH_DATA_N 0x71054
1515#define PIPE_GMCH_DATA_N_MASK (0xffffff)
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528#define _PIPEA_DP_LINK_M 0x70060
1529#define _PIPEB_DP_LINK_M 0x71060
1530#define PIPEA_DP_LINK_M_MASK (0xffffff)
1531
1532#define _PIPEA_DP_LINK_N 0x70064
1533#define _PIPEB_DP_LINK_N 0x71064
1534#define PIPEA_DP_LINK_N_MASK (0xffffff)
1535
1536#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
1537#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
1538#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
1539#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
1540
1541#define PIPE_BPC_MASK (7 << 5)
1542#define PIPE_8BPC (0 << 5)
1543#define PIPE_10BPC (1 << 5)
1544#define PIPE_6BPC (2 << 5)
1545
1546#endif
1547