LXR linux/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h

   1/*
   2 * Copyright 2010 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24
  25#ifndef __NVC0_GRAPH_H__
  26#define __NVC0_GRAPH_H__
  27
  28#include <core/client.h>
  29#include <core/handle.h>
  30#include <core/gpuobj.h>
  31#include <core/option.h>
  32
  33#include <subdev/fb.h>
  34#include <subdev/vm.h>
  35#include <subdev/bar.h>
  36#include <subdev/timer.h>
  37
  38#include <engine/fifo.h>
  39#include <engine/graph.h>
  40
  41#define GPC_MAX 4
  42#define TPC_MAX 32
  43
  44#define ROP_BCAST(r)      (0x408800 + (r))
  45#define ROP_UNIT(u, r)    (0x410000 + (u) * 0x400 + (r))
  46#define GPC_BCAST(r)      (0x418000 + (r))
  47#define GPC_UNIT(t, r)    (0x500000 + (t) * 0x8000 + (r))
  48#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
  49
  50struct nvc0_graph_data {
  51        u32 size;
  52        u32 align;
  53        u32 access;
  54};
  55
  56struct nvc0_graph_mmio {
  57        u32 addr;
  58        u32 data;
  59        u32 shift;
  60        u32 buffer;
  61};
  62
  63struct nvc0_graph_fuc {
  64        u32 *data;
  65        u32  size;
  66};
  67
  68struct nvc0_graph_priv {
  69        struct nouveau_graph base;
  70
  71        struct nvc0_graph_fuc fuc409c;
  72        struct nvc0_graph_fuc fuc409d;
  73        struct nvc0_graph_fuc fuc41ac;
  74        struct nvc0_graph_fuc fuc41ad;
  75        bool firmware;
  76
  77        u8 rop_nr;
  78        u8 gpc_nr;
  79        u8 tpc_nr[GPC_MAX];
  80        u8 tpc_total;
  81
  82        struct nouveau_gpuobj *unk4188b4;
  83        struct nouveau_gpuobj *unk4188b8;
  84
  85        struct nvc0_graph_data mmio_data[4];
  86        struct nvc0_graph_mmio mmio_list[4096/8];
  87        u32  size;
  88        u32 *data;
  89
  90        u8 magic_not_rop_nr;
  91};
  92
  93struct nvc0_graph_chan {
  94        struct nouveau_graph_chan base;
  95
  96        struct nouveau_gpuobj *mmio;
  97        struct nouveau_vma mmio_vma;
  98        int mmio_nr;
  99        struct {
 100                struct nouveau_gpuobj *mem;
 101                struct nouveau_vma vma;
 102        } data[4];
 103};
 104
 105static inline u32
 106nvc0_graph_class(void *obj)
 107{
 108        struct nouveau_device *device = nv_device(obj);
 109
 110        switch (device->chipset) {
 111        case 0xc0:
 112        case 0xc3:
 113        case 0xc4:
 114        case 0xce: /* guess, mmio trace shows only 0x9097 state */
 115        case 0xcf: /* guess, mmio trace shows only 0x9097 state */
 116                return 0x9097;
 117        case 0xc1:
 118                return 0x9197;
 119        case 0xc8:
 120        case 0xd9:
 121                return 0x9297;
 122        case 0xe4:
 123        case 0xe7:
 124                return 0xa097;
 125        default:
 126                return 0;
 127        }
 128}
 129
 130void nv_icmd(struct nvc0_graph_priv *priv, u32 icmd, u32 data);
 131
 132static inline void
 133nv_mthd(struct nvc0_graph_priv *priv, u32 class, u32 mthd, u32 data)
 134{
 135        nv_wr32(priv, 0x40448c, data);
 136        nv_wr32(priv, 0x404488, 0x80000000 | (mthd << 14) | class);
 137}
 138
 139struct nvc0_grctx {
 140        struct nvc0_graph_priv *priv;
 141        struct nvc0_graph_data *data;
 142        struct nvc0_graph_mmio *mmio;
 143        struct nouveau_gpuobj *chan;
 144        int buffer_nr;
 145        u64 buffer[4];
 146        u64 addr;
 147};
 148
 149int  nvc0_grctx_generate(struct nvc0_graph_priv *);
 150int  nvc0_grctx_init(struct nvc0_graph_priv *, struct nvc0_grctx *);
 151void nvc0_grctx_data(struct nvc0_grctx *, u32, u32, u32);
 152void nvc0_grctx_mmio(struct nvc0_grctx *, u32, u32, u32, u32);
 153int  nvc0_grctx_fini(struct nvc0_grctx *);
 154
 155int  nve0_grctx_generate(struct nvc0_graph_priv *);
 156
 157#define mmio_data(s,a,p) nvc0_grctx_data(&info, (s), (a), (p))
 158#define mmio_list(r,d,s,b) nvc0_grctx_mmio(&info, (r), (d), (s), (b))
 159
 160void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *);
 161int  nvc0_graph_ctor_fw(struct nvc0_graph_priv *, const char *,
 162                        struct nvc0_graph_fuc *);
 163void nvc0_graph_dtor(struct nouveau_object *);
 164void nvc0_graph_init_fw(struct nvc0_graph_priv *, u32 base,
 165                        struct nvc0_graph_fuc *, struct nvc0_graph_fuc *);
 166int  nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *,
 167                             struct nouveau_oclass *, void *, u32,
 168                             struct nouveau_object **);
 169void nvc0_graph_context_dtor(struct nouveau_object *);
 170
 171#endif
 172