1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27#include <subdev/fb.h>
28
29struct nv40_fb_priv {
30 struct nouveau_fb base;
31};
32
33static inline int
34nv44_graph_class(struct nouveau_device *device)
35{
36 if ((device->chipset & 0xf0) == 0x60)
37 return 1;
38
39 return !(0x0baf & (1 << (device->chipset & 0x0f)));
40}
41
42static void
43nv40_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
44{
45 nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
46 nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
47 nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
48}
49
50static void
51nv40_fb_init_gart(struct nv40_fb_priv *priv)
52{
53 nv_wr32(priv, 0x100800, 0x00000001);
54}
55
56static void
57nv44_fb_init_gart(struct nv40_fb_priv *priv)
58{
59 nv_wr32(priv, 0x100850, 0x80000000);
60 nv_wr32(priv, 0x100800, 0x00000001);
61}
62
63static int
64nv40_fb_init(struct nouveau_object *object)
65{
66 struct nv40_fb_priv *priv = (void *)object;
67 int ret;
68
69 ret = nouveau_fb_init(&priv->base);
70 if (ret)
71 return ret;
72
73 switch (nv_device(priv)->chipset) {
74 case 0x40:
75 case 0x45:
76 nv_mask(priv, 0x10033c, 0x00008000, 0x00000000);
77 break;
78 default:
79 if (nv44_graph_class(nv_device(priv)))
80 nv44_fb_init_gart(priv);
81 else
82 nv40_fb_init_gart(priv);
83 break;
84 }
85
86 return 0;
87}
88
89static int
90nv40_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
91 struct nouveau_oclass *oclass, void *data, u32 size,
92 struct nouveau_object **pobject)
93{
94 struct nouveau_device *device = nv_device(parent);
95 struct nv40_fb_priv *priv;
96 int ret;
97
98 ret = nouveau_fb_create(parent, engine, oclass, &priv);
99 *pobject = nv_object(priv);
100 if (ret)
101 return ret;
102
103
104
105
106
107
108
109 if (device->chipset == 0x40) {
110 u32 pbus1218 = nv_rd32(priv, 0x001218);
111 switch (pbus1218 & 0x00000300) {
112 case 0x00000000: priv->base.ram.type = NV_MEM_TYPE_SDRAM; break;
113 case 0x00000100: priv->base.ram.type = NV_MEM_TYPE_DDR1; break;
114 case 0x00000200: priv->base.ram.type = NV_MEM_TYPE_GDDR3; break;
115 case 0x00000300: priv->base.ram.type = NV_MEM_TYPE_DDR2; break;
116 }
117 } else
118 if (device->chipset == 0x49 || device->chipset == 0x4b) {
119 u32 pfb914 = nv_rd32(priv, 0x100914);
120 switch (pfb914 & 0x00000003) {
121 case 0x00000000: priv->base.ram.type = NV_MEM_TYPE_DDR1; break;
122 case 0x00000001: priv->base.ram.type = NV_MEM_TYPE_DDR2; break;
123 case 0x00000002: priv->base.ram.type = NV_MEM_TYPE_GDDR3; break;
124 case 0x00000003: break;
125 }
126 } else
127 if (device->chipset != 0x4e) {
128 u32 pfb474 = nv_rd32(priv, 0x100474);
129 if (pfb474 & 0x00000004)
130 priv->base.ram.type = NV_MEM_TYPE_GDDR3;
131 if (pfb474 & 0x00000002)
132 priv->base.ram.type = NV_MEM_TYPE_DDR2;
133 if (pfb474 & 0x00000001)
134 priv->base.ram.type = NV_MEM_TYPE_DDR1;
135 } else {
136 priv->base.ram.type = NV_MEM_TYPE_STOLEN;
137 }
138
139 priv->base.ram.size = nv_rd32(priv, 0x10020c) & 0xff000000;
140
141 priv->base.memtype_valid = nv04_fb_memtype_valid;
142 switch (device->chipset) {
143 case 0x40:
144 case 0x45:
145 priv->base.tile.regions = 8;
146 break;
147 case 0x46:
148 case 0x47:
149 case 0x49:
150 case 0x4b:
151 case 0x4c:
152 priv->base.tile.regions = 15;
153 break;
154 default:
155 priv->base.tile.regions = 12;
156 break;
157 }
158 priv->base.tile.init = nv30_fb_tile_init;
159 priv->base.tile.fini = nv30_fb_tile_fini;
160 if (device->chipset == 0x40)
161 priv->base.tile.prog = nv10_fb_tile_prog;
162 else
163 priv->base.tile.prog = nv40_fb_tile_prog;
164
165 return nouveau_fb_created(&priv->base);
166}
167
168
169struct nouveau_oclass
170nv40_fb_oclass = {
171 .handle = NV_SUBDEV(FB, 0x40),
172 .ofuncs = &(struct nouveau_ofuncs) {
173 .ctor = nv40_fb_ctor,
174 .dtor = _nouveau_fb_dtor,
175 .init = nv40_fb_init,
176 .fini = _nouveau_fb_fini,
177 },
178};
179