1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42#ifndef __EHCA_CLASSES_PSERIES_H__
43#define __EHCA_CLASSES_PSERIES_H__
44
45#include "hcp_phyp.h"
46#include "ipz_pt_fn.h"
47
48
49struct ehca_pfqp {
50 struct ipz_qpt sqpt;
51 struct ipz_qpt rqpt;
52};
53
54struct ehca_pfcq {
55 struct ipz_qpt qpt;
56 u32 cqnr;
57};
58
59struct ehca_pfeq {
60 struct ipz_qpt qpt;
61 struct h_galpa galpa;
62 u32 eqnr;
63};
64
65struct ipz_adapter_handle {
66 u64 handle;
67};
68
69struct ipz_cq_handle {
70 u64 handle;
71};
72
73struct ipz_eq_handle {
74 u64 handle;
75};
76
77struct ipz_qp_handle {
78 u64 handle;
79};
80struct ipz_mrmw_handle {
81 u64 handle;
82};
83
84struct ipz_pd {
85 u32 value;
86};
87
88struct hcp_modify_qp_control_block {
89 u32 qkey;
90 u32 rdd;
91 u32 send_psn;
92 u32 receive_psn;
93 u32 prim_phys_port;
94 u32 alt_phys_port;
95 u32 prim_p_key_idx;
96 u32 alt_p_key_idx;
97 u32 rdma_atomic_ctrl;
98 u32 qp_state;
99 u32 reserved_10;
100 u32 rdma_nr_atomic_resp_res;
101 u32 path_migration_state;
102 u32 rdma_atomic_outst_dest_qp;
103 u32 dest_qp_nr;
104 u32 min_rnr_nak_timer_field;
105 u32 service_level;
106 u32 send_grh_flag;
107 u32 retry_count;
108 u32 timeout;
109 u32 path_mtu;
110 u32 max_static_rate;
111 u32 dlid;
112 u32 rnr_retry_count;
113 u32 source_path_bits;
114 u32 traffic_class;
115 u32 hop_limit;
116 u32 source_gid_idx;
117 u32 flow_label;
118 u32 reserved_29;
119 union {
120 u64 dw[2];
121 u8 byte[16];
122 } dest_gid;
123 u32 service_level_al;
124 u32 send_grh_flag_al;
125 u32 retry_count_al;
126 u32 timeout_al;
127 u32 max_static_rate_al;
128 u32 dlid_al;
129 u32 rnr_retry_count_al;
130 u32 source_path_bits_al;
131 u32 traffic_class_al;
132 u32 hop_limit_al;
133 u32 source_gid_idx_al;
134 u32 flow_label_al;
135 u32 reserved_46;
136 u32 reserved_47;
137 union {
138 u64 dw[2];
139 u8 byte[16];
140 } dest_gid_al;
141 u32 max_nr_outst_send_wr;
142 u32 max_nr_outst_recv_wr;
143 u32 disable_ete_credit_check;
144 u32 qp_number;
145 u64 send_queue_handle;
146 u64 recv_queue_handle;
147 u32 actual_nr_sges_in_sq_wqe;
148 u32 actual_nr_sges_in_rq_wqe;
149 u32 qp_enable;
150 u32 curr_srq_limit;
151 u64 qp_aff_asyn_ev_log_reg;
152 u64 shared_rq_hndl;
153 u64 trigg_doorbell_qp_hndl;
154 u32 reserved_70_127[58];
155};
156
157#define MQPCB_MASK_QKEY EHCA_BMASK_IBM( 0, 0)
158#define MQPCB_MASK_SEND_PSN EHCA_BMASK_IBM( 2, 2)
159#define MQPCB_MASK_RECEIVE_PSN EHCA_BMASK_IBM( 3, 3)
160#define MQPCB_MASK_PRIM_PHYS_PORT EHCA_BMASK_IBM( 4, 4)
161#define MQPCB_PRIM_PHYS_PORT EHCA_BMASK_IBM(24, 31)
162#define MQPCB_MASK_ALT_PHYS_PORT EHCA_BMASK_IBM( 5, 5)
163#define MQPCB_MASK_PRIM_P_KEY_IDX EHCA_BMASK_IBM( 6, 6)
164#define MQPCB_PRIM_P_KEY_IDX EHCA_BMASK_IBM(24, 31)
165#define MQPCB_MASK_ALT_P_KEY_IDX EHCA_BMASK_IBM( 7, 7)
166#define MQPCB_MASK_RDMA_ATOMIC_CTRL EHCA_BMASK_IBM( 8, 8)
167#define MQPCB_MASK_QP_STATE EHCA_BMASK_IBM( 9, 9)
168#define MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES EHCA_BMASK_IBM(11, 11)
169#define MQPCB_MASK_PATH_MIGRATION_STATE EHCA_BMASK_IBM(12, 12)
170#define MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP EHCA_BMASK_IBM(13, 13)
171#define MQPCB_MASK_DEST_QP_NR EHCA_BMASK_IBM(14, 14)
172#define MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD EHCA_BMASK_IBM(15, 15)
173#define MQPCB_MASK_SERVICE_LEVEL EHCA_BMASK_IBM(16, 16)
174#define MQPCB_MASK_SEND_GRH_FLAG EHCA_BMASK_IBM(17, 17)
175#define MQPCB_MASK_RETRY_COUNT EHCA_BMASK_IBM(18, 18)
176#define MQPCB_MASK_TIMEOUT EHCA_BMASK_IBM(19, 19)
177#define MQPCB_MASK_PATH_MTU EHCA_BMASK_IBM(20, 20)
178#define MQPCB_MASK_MAX_STATIC_RATE EHCA_BMASK_IBM(21, 21)
179#define MQPCB_MASK_DLID EHCA_BMASK_IBM(22, 22)
180#define MQPCB_MASK_RNR_RETRY_COUNT EHCA_BMASK_IBM(23, 23)
181#define MQPCB_MASK_SOURCE_PATH_BITS EHCA_BMASK_IBM(24, 24)
182#define MQPCB_MASK_TRAFFIC_CLASS EHCA_BMASK_IBM(25, 25)
183#define MQPCB_MASK_HOP_LIMIT EHCA_BMASK_IBM(26, 26)
184#define MQPCB_MASK_SOURCE_GID_IDX EHCA_BMASK_IBM(27, 27)
185#define MQPCB_MASK_FLOW_LABEL EHCA_BMASK_IBM(28, 28)
186#define MQPCB_MASK_DEST_GID EHCA_BMASK_IBM(30, 30)
187#define MQPCB_MASK_SERVICE_LEVEL_AL EHCA_BMASK_IBM(31, 31)
188#define MQPCB_MASK_SEND_GRH_FLAG_AL EHCA_BMASK_IBM(32, 32)
189#define MQPCB_MASK_RETRY_COUNT_AL EHCA_BMASK_IBM(33, 33)
190#define MQPCB_MASK_TIMEOUT_AL EHCA_BMASK_IBM(34, 34)
191#define MQPCB_MASK_MAX_STATIC_RATE_AL EHCA_BMASK_IBM(35, 35)
192#define MQPCB_MASK_DLID_AL EHCA_BMASK_IBM(36, 36)
193#define MQPCB_MASK_RNR_RETRY_COUNT_AL EHCA_BMASK_IBM(37, 37)
194#define MQPCB_MASK_SOURCE_PATH_BITS_AL EHCA_BMASK_IBM(38, 38)
195#define MQPCB_MASK_TRAFFIC_CLASS_AL EHCA_BMASK_IBM(39, 39)
196#define MQPCB_MASK_HOP_LIMIT_AL EHCA_BMASK_IBM(40, 40)
197#define MQPCB_MASK_SOURCE_GID_IDX_AL EHCA_BMASK_IBM(41, 41)
198#define MQPCB_MASK_FLOW_LABEL_AL EHCA_BMASK_IBM(42, 42)
199#define MQPCB_MASK_DEST_GID_AL EHCA_BMASK_IBM(44, 44)
200#define MQPCB_MASK_MAX_NR_OUTST_SEND_WR EHCA_BMASK_IBM(45, 45)
201#define MQPCB_MASK_MAX_NR_OUTST_RECV_WR EHCA_BMASK_IBM(46, 46)
202#define MQPCB_MASK_DISABLE_ETE_CREDIT_CHECK EHCA_BMASK_IBM(47, 47)
203#define MQPCB_MASK_QP_ENABLE EHCA_BMASK_IBM(48, 48)
204#define MQPCB_MASK_CURR_SRQ_LIMIT EHCA_BMASK_IBM(49, 49)
205#define MQPCB_MASK_QP_AFF_ASYN_EV_LOG_REG EHCA_BMASK_IBM(50, 50)
206#define MQPCB_MASK_SHARED_RQ_HNDL EHCA_BMASK_IBM(51, 51)
207
208#endif
209