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26#include <linux/delay.h>
27#include <media/v4l2-common.h>
28#include <linux/v4l2-mediabus.h>
29#include <linux/mm.h>
30
31#include "isp.h"
32#include "ispreg.h"
33#include "ispcsi2.h"
34
35
36
37
38
39
40static void csi2_if_enable(struct isp_device *isp,
41 struct isp_csi2_device *csi2, u8 enable)
42{
43 struct isp_csi2_ctrl_cfg *currctrl = &csi2->ctrl;
44
45 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_CTRL, ISPCSI2_CTRL_IF_EN,
46 enable ? ISPCSI2_CTRL_IF_EN : 0);
47
48 currctrl->if_enable = enable;
49}
50
51
52
53
54
55
56static void csi2_recv_config(struct isp_device *isp,
57 struct isp_csi2_device *csi2,
58 struct isp_csi2_ctrl_cfg *currctrl)
59{
60 u32 reg;
61
62 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTRL);
63
64 if (currctrl->frame_mode)
65 reg |= ISPCSI2_CTRL_FRAME;
66 else
67 reg &= ~ISPCSI2_CTRL_FRAME;
68
69 if (currctrl->vp_clk_enable)
70 reg |= ISPCSI2_CTRL_VP_CLK_EN;
71 else
72 reg &= ~ISPCSI2_CTRL_VP_CLK_EN;
73
74 if (currctrl->vp_only_enable)
75 reg |= ISPCSI2_CTRL_VP_ONLY_EN;
76 else
77 reg &= ~ISPCSI2_CTRL_VP_ONLY_EN;
78
79 reg &= ~ISPCSI2_CTRL_VP_OUT_CTRL_MASK;
80 reg |= currctrl->vp_out_ctrl << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT;
81
82 if (currctrl->ecc_enable)
83 reg |= ISPCSI2_CTRL_ECC_EN;
84 else
85 reg &= ~ISPCSI2_CTRL_ECC_EN;
86
87 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTRL);
88}
89
90static const unsigned int csi2_input_fmts[] = {
91 V4L2_MBUS_FMT_SGRBG10_1X10,
92 V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8,
93 V4L2_MBUS_FMT_SRGGB10_1X10,
94 V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8,
95 V4L2_MBUS_FMT_SBGGR10_1X10,
96 V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8,
97 V4L2_MBUS_FMT_SGBRG10_1X10,
98 V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8,
99 V4L2_MBUS_FMT_YUYV8_2X8,
100};
101
102
103
104
105
106
107
108
109
110
111
112static const u16 __csi2_fmt_map[3][2][2][2] = {
113
114 {
115
116 {
117
118 { CSI2_PIX_FMT_RAW10_EXP16, CSI2_PIX_FMT_RAW10_EXP16 },
119
120 { 0, 0 },
121 },
122
123 {
124
125 { CSI2_PIX_FMT_RAW10_EXP16_VP,
126 CSI2_PIX_FMT_RAW10_EXP16_VP },
127
128 { 0, 0 },
129 },
130 },
131
132 {
133
134 {
135
136 { CSI2_PIX_FMT_RAW8, CSI2_USERDEF_8BIT_DATA1 },
137
138 { CSI2_PIX_FMT_RAW8_DPCM10_EXP16,
139 CSI2_USERDEF_8BIT_DATA1_DPCM10 },
140 },
141
142 {
143
144 { CSI2_PIX_FMT_RAW8_VP,
145 CSI2_PIX_FMT_RAW8_VP },
146
147 { CSI2_PIX_FMT_RAW8_DPCM10_VP,
148 CSI2_USERDEF_8BIT_DATA1_DPCM10_VP },
149 },
150 },
151
152 {
153
154 {
155
156 { CSI2_PIX_FMT_YUV422_8BIT,
157 CSI2_PIX_FMT_YUV422_8BIT },
158
159 { 0, 0 },
160 },
161
162 {
163
164 { CSI2_PIX_FMT_YUV422_8BIT_VP,
165 CSI2_PIX_FMT_YUV422_8BIT_VP },
166
167 { 0, 0 },
168 },
169 },
170};
171
172
173
174
175
176
177
178static u16 csi2_ctx_map_format(struct isp_csi2_device *csi2)
179{
180 const struct v4l2_mbus_framefmt *fmt = &csi2->formats[CSI2_PAD_SINK];
181 int fmtidx, destidx, is_3630;
182
183 switch (fmt->code) {
184 case V4L2_MBUS_FMT_SGRBG10_1X10:
185 case V4L2_MBUS_FMT_SRGGB10_1X10:
186 case V4L2_MBUS_FMT_SBGGR10_1X10:
187 case V4L2_MBUS_FMT_SGBRG10_1X10:
188 fmtidx = 0;
189 break;
190 case V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8:
191 case V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8:
192 case V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8:
193 case V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8:
194 fmtidx = 1;
195 break;
196 case V4L2_MBUS_FMT_YUYV8_2X8:
197 fmtidx = 2;
198 break;
199 default:
200 WARN(1, KERN_ERR "CSI2: pixel format %08x unsupported!\n",
201 fmt->code);
202 return 0;
203 }
204
205 if (!(csi2->output & CSI2_OUTPUT_CCDC) &&
206 !(csi2->output & CSI2_OUTPUT_MEMORY)) {
207
208 return CSI2_PIX_FMT_OTHERS;
209 }
210
211
212
213
214 destidx = csi2->frame_skip ? 0 : !!(csi2->output & CSI2_OUTPUT_CCDC);
215 is_3630 = csi2->isp->revision == ISP_REVISION_15_0;
216
217 return __csi2_fmt_map[fmtidx][destidx][csi2->dpcm_decompress][is_3630];
218}
219
220
221
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223
224
225
226
227
228
229
230static void csi2_set_outaddr(struct isp_csi2_device *csi2, u32 addr)
231{
232 struct isp_device *isp = csi2->isp;
233 struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[0];
234
235 ctx->ping_addr = addr;
236 ctx->pong_addr = addr;
237 isp_reg_writel(isp, ctx->ping_addr,
238 csi2->regs1, ISPCSI2_CTX_DAT_PING_ADDR(ctx->ctxnum));
239 isp_reg_writel(isp, ctx->pong_addr,
240 csi2->regs1, ISPCSI2_CTX_DAT_PONG_ADDR(ctx->ctxnum));
241}
242
243
244
245
246
247
248
249static inline int is_usr_def_mapping(u32 format_id)
250{
251 return (format_id & 0x40) ? 1 : 0;
252}
253
254
255
256
257
258
259
260static void csi2_ctx_enable(struct isp_device *isp,
261 struct isp_csi2_device *csi2, u8 ctxnum, u8 enable)
262{
263 struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum];
264 unsigned int skip = 0;
265 u32 reg;
266
267 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
268
269 if (enable) {
270 if (csi2->frame_skip)
271 skip = csi2->frame_skip;
272 else if (csi2->output & CSI2_OUTPUT_MEMORY)
273 skip = 1;
274
275 reg &= ~ISPCSI2_CTX_CTRL1_COUNT_MASK;
276 reg |= ISPCSI2_CTX_CTRL1_COUNT_UNLOCK
277 | (skip << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
278 | ISPCSI2_CTX_CTRL1_CTX_EN;
279 } else {
280 reg &= ~ISPCSI2_CTX_CTRL1_CTX_EN;
281 }
282
283 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
284 ctx->enabled = enable;
285}
286
287
288
289
290
291
292static void csi2_ctx_config(struct isp_device *isp,
293 struct isp_csi2_device *csi2,
294 struct isp_csi2_ctx_cfg *ctx)
295{
296 u32 reg;
297
298
299 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
300
301 if (ctx->eof_enabled)
302 reg |= ISPCSI2_CTX_CTRL1_EOF_EN;
303 else
304 reg &= ~ISPCSI2_CTX_CTRL1_EOF_EN;
305
306 if (ctx->eol_enabled)
307 reg |= ISPCSI2_CTX_CTRL1_EOL_EN;
308 else
309 reg &= ~ISPCSI2_CTX_CTRL1_EOL_EN;
310
311 if (ctx->checksum_enabled)
312 reg |= ISPCSI2_CTX_CTRL1_CS_EN;
313 else
314 reg &= ~ISPCSI2_CTX_CTRL1_CS_EN;
315
316 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
317
318
319 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
320
321 reg &= ~(ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK);
322 reg |= ctx->virtual_id << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
323
324 reg &= ~(ISPCSI2_CTX_CTRL2_FORMAT_MASK);
325 reg |= ctx->format_id << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT;
326
327 if (ctx->dpcm_decompress) {
328 if (ctx->dpcm_predictor)
329 reg |= ISPCSI2_CTX_CTRL2_DPCM_PRED;
330 else
331 reg &= ~ISPCSI2_CTX_CTRL2_DPCM_PRED;
332 }
333
334 if (is_usr_def_mapping(ctx->format_id)) {
335 reg &= ~ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK;
336 reg |= 2 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT;
337 }
338
339 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
340
341
342 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
343 reg &= ~(ISPCSI2_CTX_CTRL3_ALPHA_MASK);
344 reg |= (ctx->alpha << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT);
345
346 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
347
348
349 reg = isp_reg_readl(isp, csi2->regs1,
350 ISPCSI2_CTX_DAT_OFST(ctx->ctxnum));
351 reg &= ~ISPCSI2_CTX_DAT_OFST_OFST_MASK;
352 reg |= ctx->data_offset << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT;
353 isp_reg_writel(isp, reg, csi2->regs1,
354 ISPCSI2_CTX_DAT_OFST(ctx->ctxnum));
355
356 isp_reg_writel(isp, ctx->ping_addr,
357 csi2->regs1, ISPCSI2_CTX_DAT_PING_ADDR(ctx->ctxnum));
358
359 isp_reg_writel(isp, ctx->pong_addr,
360 csi2->regs1, ISPCSI2_CTX_DAT_PONG_ADDR(ctx->ctxnum));
361}
362
363
364
365
366
367static void csi2_timing_config(struct isp_device *isp,
368 struct isp_csi2_device *csi2,
369 struct isp_csi2_timing_cfg *timing)
370{
371 u32 reg;
372
373 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_TIMING);
374
375 if (timing->force_rx_mode)
376 reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
377 else
378 reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
379
380 if (timing->stop_state_16x)
381 reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
382 else
383 reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
384
385 if (timing->stop_state_4x)
386 reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
387 else
388 reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
389
390 reg &= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(timing->ionum);
391 reg |= timing->stop_state_counter <<
392 ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(timing->ionum);
393
394 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_TIMING);
395}
396
397
398
399
400
401static void csi2_irq_ctx_set(struct isp_device *isp,
402 struct isp_csi2_device *csi2, int enable)
403{
404 int i;
405
406 for (i = 0; i < 8; i++) {
407 isp_reg_writel(isp, ISPCSI2_CTX_IRQSTATUS_FE_IRQ, csi2->regs1,
408 ISPCSI2_CTX_IRQSTATUS(i));
409 if (enable)
410 isp_reg_set(isp, csi2->regs1, ISPCSI2_CTX_IRQENABLE(i),
411 ISPCSI2_CTX_IRQSTATUS_FE_IRQ);
412 else
413 isp_reg_clr(isp, csi2->regs1, ISPCSI2_CTX_IRQENABLE(i),
414 ISPCSI2_CTX_IRQSTATUS_FE_IRQ);
415 }
416}
417
418
419
420
421
422static void csi2_irq_complexio1_set(struct isp_device *isp,
423 struct isp_csi2_device *csi2, int enable)
424{
425 u32 reg;
426 reg = ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT |
427 ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER |
428 ISPCSI2_PHY_IRQENABLE_STATEULPM5 |
429 ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 |
430 ISPCSI2_PHY_IRQENABLE_ERRESC5 |
431 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 |
432 ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 |
433 ISPCSI2_PHY_IRQENABLE_STATEULPM4 |
434 ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 |
435 ISPCSI2_PHY_IRQENABLE_ERRESC4 |
436 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 |
437 ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 |
438 ISPCSI2_PHY_IRQENABLE_STATEULPM3 |
439 ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 |
440 ISPCSI2_PHY_IRQENABLE_ERRESC3 |
441 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 |
442 ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 |
443 ISPCSI2_PHY_IRQENABLE_STATEULPM2 |
444 ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 |
445 ISPCSI2_PHY_IRQENABLE_ERRESC2 |
446 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 |
447 ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 |
448 ISPCSI2_PHY_IRQENABLE_STATEULPM1 |
449 ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 |
450 ISPCSI2_PHY_IRQENABLE_ERRESC1 |
451 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 |
452 ISPCSI2_PHY_IRQENABLE_ERRSOTHS1;
453 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
454 if (enable)
455 reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
456 else
457 reg = 0;
458 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
459}
460
461
462
463
464
465static void csi2_irq_status_set(struct isp_device *isp,
466 struct isp_csi2_device *csi2, int enable)
467{
468 u32 reg;
469 reg = ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
470 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
471 ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ |
472 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
473 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
474 ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ |
475 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ |
476 ISPCSI2_IRQSTATUS_CONTEXT(0);
477 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQSTATUS);
478 if (enable)
479 reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQENABLE);
480 else
481 reg = 0;
482
483 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQENABLE);
484}
485
486
487
488
489
490
491
492
493int omap3isp_csi2_reset(struct isp_csi2_device *csi2)
494{
495 struct isp_device *isp = csi2->isp;
496 u8 soft_reset_retries = 0;
497 u32 reg;
498 int i;
499
500 if (!csi2->available)
501 return -ENODEV;
502
503 if (csi2->phy->phy_in_use)
504 return -EBUSY;
505
506 isp_reg_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
507 ISPCSI2_SYSCONFIG_SOFT_RESET);
508
509 do {
510 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_SYSSTATUS) &
511 ISPCSI2_SYSSTATUS_RESET_DONE;
512 if (reg == ISPCSI2_SYSSTATUS_RESET_DONE)
513 break;
514 soft_reset_retries++;
515 if (soft_reset_retries < 5)
516 udelay(100);
517 } while (soft_reset_retries < 5);
518
519 if (soft_reset_retries == 5) {
520 printk(KERN_ERR "CSI2: Soft reset try count exceeded!\n");
521 return -EBUSY;
522 }
523
524 if (isp->revision == ISP_REVISION_15_0)
525 isp_reg_set(isp, csi2->regs1, ISPCSI2_PHY_CFG,
526 ISPCSI2_PHY_CFG_RESET_CTRL);
527
528 i = 100;
529 do {
530 reg = isp_reg_readl(isp, csi2->phy->phy_regs, ISPCSIPHY_REG1)
531 & ISPCSIPHY_REG1_RESET_DONE_CTRLCLK;
532 if (reg == ISPCSIPHY_REG1_RESET_DONE_CTRLCLK)
533 break;
534 udelay(100);
535 } while (--i > 0);
536
537 if (i == 0) {
538 printk(KERN_ERR
539 "CSI2: Reset for CSI2_96M_FCLK domain Failed!\n");
540 return -EBUSY;
541 }
542
543 if (isp->autoidle)
544 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
545 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
546 ISPCSI2_SYSCONFIG_AUTO_IDLE,
547 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART |
548 ((isp->revision == ISP_REVISION_15_0) ?
549 ISPCSI2_SYSCONFIG_AUTO_IDLE : 0));
550 else
551 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
552 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
553 ISPCSI2_SYSCONFIG_AUTO_IDLE,
554 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO);
555
556 return 0;
557}
558
559static int csi2_configure(struct isp_csi2_device *csi2)
560{
561 const struct isp_v4l2_subdevs_group *pdata;
562 struct isp_device *isp = csi2->isp;
563 struct isp_csi2_timing_cfg *timing = &csi2->timing[0];
564 struct v4l2_subdev *sensor;
565 struct media_pad *pad;
566
567
568
569
570
571
572
573 if (csi2->contexts[0].enabled || csi2->ctrl.if_enable)
574 return -EBUSY;
575
576 pad = media_entity_remote_source(&csi2->pads[CSI2_PAD_SINK]);
577 sensor = media_entity_to_v4l2_subdev(pad->entity);
578 pdata = sensor->host_priv;
579
580 csi2->frame_skip = 0;
581 v4l2_subdev_call(sensor, sensor, g_skip_frames, &csi2->frame_skip);
582
583 csi2->ctrl.vp_out_ctrl = pdata->bus.csi2.vpclk_div;
584 csi2->ctrl.frame_mode = ISP_CSI2_FRAME_IMMEDIATE;
585 csi2->ctrl.ecc_enable = pdata->bus.csi2.crc;
586
587 timing->ionum = 1;
588 timing->force_rx_mode = 1;
589 timing->stop_state_16x = 1;
590 timing->stop_state_4x = 1;
591 timing->stop_state_counter = 0x1FF;
592
593
594
595
596
597
598 if (csi2->formats[CSI2_PAD_SINK].code !=
599 csi2->formats[CSI2_PAD_SOURCE].code)
600 csi2->dpcm_decompress = true;
601 else
602 csi2->dpcm_decompress = false;
603
604 csi2->contexts[0].format_id = csi2_ctx_map_format(csi2);
605
606 if (csi2->video_out.bpl_padding == 0)
607 csi2->contexts[0].data_offset = 0;
608 else
609 csi2->contexts[0].data_offset = csi2->video_out.bpl_value;
610
611
612
613
614
615
616
617
618 csi2->contexts[0].eof_enabled = 1;
619 csi2->contexts[0].eol_enabled = 1;
620
621 csi2_irq_complexio1_set(isp, csi2, 1);
622 csi2_irq_ctx_set(isp, csi2, 1);
623 csi2_irq_status_set(isp, csi2, 1);
624
625
626 csi2_timing_config(isp, csi2, timing);
627 csi2_recv_config(isp, csi2, &csi2->ctrl);
628 csi2_ctx_config(isp, csi2, &csi2->contexts[0]);
629
630 return 0;
631}
632
633
634
635
636#define CSI2_PRINT_REGISTER(isp, regs, name)\
637 dev_dbg(isp->dev, "###CSI2 " #name "=0x%08x\n", \
638 isp_reg_readl(isp, regs, ISPCSI2_##name))
639
640static void csi2_print_status(struct isp_csi2_device *csi2)
641{
642 struct isp_device *isp = csi2->isp;
643
644 if (!csi2->available)
645 return;
646
647 dev_dbg(isp->dev, "-------------CSI2 Register dump-------------\n");
648
649 CSI2_PRINT_REGISTER(isp, csi2->regs1, SYSCONFIG);
650 CSI2_PRINT_REGISTER(isp, csi2->regs1, SYSSTATUS);
651 CSI2_PRINT_REGISTER(isp, csi2->regs1, IRQENABLE);
652 CSI2_PRINT_REGISTER(isp, csi2->regs1, IRQSTATUS);
653 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTRL);
654 CSI2_PRINT_REGISTER(isp, csi2->regs1, DBG_H);
655 CSI2_PRINT_REGISTER(isp, csi2->regs1, GNQ);
656 CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_CFG);
657 CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_IRQSTATUS);
658 CSI2_PRINT_REGISTER(isp, csi2->regs1, SHORT_PACKET);
659 CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_IRQENABLE);
660 CSI2_PRINT_REGISTER(isp, csi2->regs1, DBG_P);
661 CSI2_PRINT_REGISTER(isp, csi2->regs1, TIMING);
662 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL1(0));
663 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL2(0));
664 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_OFST(0));
665 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_PING_ADDR(0));
666 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_PONG_ADDR(0));
667 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_IRQENABLE(0));
668 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_IRQSTATUS(0));
669 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL3(0));
670
671 dev_dbg(isp->dev, "--------------------------------------------\n");
672}
673
674
675
676
677
678
679
680
681
682static void csi2_isr_buffer(struct isp_csi2_device *csi2)
683{
684 struct isp_device *isp = csi2->isp;
685 struct isp_buffer *buffer;
686
687 csi2_ctx_enable(isp, csi2, 0, 0);
688
689 buffer = omap3isp_video_buffer_next(&csi2->video_out);
690
691
692
693
694
695 if (buffer == NULL)
696 return;
697
698 csi2_set_outaddr(csi2, buffer->isp_addr);
699 csi2_ctx_enable(isp, csi2, 0, 1);
700}
701
702static void csi2_isr_ctx(struct isp_csi2_device *csi2,
703 struct isp_csi2_ctx_cfg *ctx)
704{
705 struct isp_device *isp = csi2->isp;
706 unsigned int n = ctx->ctxnum;
707 u32 status;
708
709 status = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_IRQSTATUS(n));
710 isp_reg_writel(isp, status, csi2->regs1, ISPCSI2_CTX_IRQSTATUS(n));
711
712 if (!(status & ISPCSI2_CTX_IRQSTATUS_FE_IRQ))
713 return;
714
715
716
717
718
719
720
721
722
723
724
725 if (csi2->frame_skip) {
726 csi2->frame_skip--;
727 if (csi2->frame_skip == 0) {
728 ctx->format_id = csi2_ctx_map_format(csi2);
729 csi2_ctx_config(isp, csi2, ctx);
730 csi2_ctx_enable(isp, csi2, n, 1);
731 }
732 return;
733 }
734
735 if (csi2->output & CSI2_OUTPUT_MEMORY)
736 csi2_isr_buffer(csi2);
737}
738
739
740
741
742void omap3isp_csi2_isr(struct isp_csi2_device *csi2)
743{
744 struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity);
745 u32 csi2_irqstatus, cpxio1_irqstatus;
746 struct isp_device *isp = csi2->isp;
747
748 if (!csi2->available)
749 return;
750
751 csi2_irqstatus = isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQSTATUS);
752 isp_reg_writel(isp, csi2_irqstatus, csi2->regs1, ISPCSI2_IRQSTATUS);
753
754
755 if (csi2_irqstatus & ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ) {
756 cpxio1_irqstatus = isp_reg_readl(isp, csi2->regs1,
757 ISPCSI2_PHY_IRQSTATUS);
758 isp_reg_writel(isp, cpxio1_irqstatus,
759 csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
760 dev_dbg(isp->dev, "CSI2: ComplexIO Error IRQ "
761 "%x\n", cpxio1_irqstatus);
762 pipe->error = true;
763 }
764
765 if (csi2_irqstatus & (ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
766 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
767 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
768 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
769 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ)) {
770 dev_dbg(isp->dev, "CSI2 Err:"
771 " OCP:%d,"
772 " Short_pack:%d,"
773 " ECC:%d,"
774 " CPXIO2:%d,"
775 " FIFO_OVF:%d,"
776 "\n",
777 (csi2_irqstatus &
778 ISPCSI2_IRQSTATUS_OCP_ERR_IRQ) ? 1 : 0,
779 (csi2_irqstatus &
780 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ) ? 1 : 0,
781 (csi2_irqstatus &
782 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ) ? 1 : 0,
783 (csi2_irqstatus &
784 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ) ? 1 : 0,
785 (csi2_irqstatus &
786 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ) ? 1 : 0);
787 pipe->error = true;
788 }
789
790 if (omap3isp_module_sync_is_stopping(&csi2->wait, &csi2->stopping))
791 return;
792
793
794 if (csi2_irqstatus & ISPCSI2_IRQSTATUS_CONTEXT(0))
795 csi2_isr_ctx(csi2, &csi2->contexts[0]);
796
797 if (csi2_irqstatus & ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ)
798 dev_dbg(isp->dev, "CSI2: ECC correction done\n");
799}
800
801
802
803
804
805
806
807
808
809
810static int csi2_queue(struct isp_video *video, struct isp_buffer *buffer)
811{
812 struct isp_device *isp = video->isp;
813 struct isp_csi2_device *csi2 = &isp->isp_csi2a;
814
815 csi2_set_outaddr(csi2, buffer->isp_addr);
816
817
818
819
820
821
822
823 if (csi2->video_out.dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
824
825 csi2_if_enable(isp, csi2, 1);
826 csi2_ctx_enable(isp, csi2, 0, 1);
827 isp_video_dmaqueue_flags_clr(&csi2->video_out);
828 }
829
830 return 0;
831}
832
833static const struct isp_video_operations csi2_ispvideo_ops = {
834 .queue = csi2_queue,
835};
836
837
838
839
840
841static struct v4l2_mbus_framefmt *
842__csi2_get_format(struct isp_csi2_device *csi2, struct v4l2_subdev_fh *fh,
843 unsigned int pad, enum v4l2_subdev_format_whence which)
844{
845 if (which == V4L2_SUBDEV_FORMAT_TRY)
846 return v4l2_subdev_get_try_format(fh, pad);
847 else
848 return &csi2->formats[pad];
849}
850
851static void
852csi2_try_format(struct isp_csi2_device *csi2, struct v4l2_subdev_fh *fh,
853 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
854 enum v4l2_subdev_format_whence which)
855{
856 enum v4l2_mbus_pixelcode pixelcode;
857 struct v4l2_mbus_framefmt *format;
858 const struct isp_format_info *info;
859 unsigned int i;
860
861 switch (pad) {
862 case CSI2_PAD_SINK:
863
864 for (i = 0; i < ARRAY_SIZE(csi2_input_fmts); i++) {
865 if (fmt->code == csi2_input_fmts[i])
866 break;
867 }
868
869
870 if (i >= ARRAY_SIZE(csi2_input_fmts))
871 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
872
873 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
874 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
875 break;
876
877 case CSI2_PAD_SOURCE:
878
879
880
881 pixelcode = fmt->code;
882 format = __csi2_get_format(csi2, fh, CSI2_PAD_SINK, which);
883 memcpy(fmt, format, sizeof(*fmt));
884
885
886
887
888
889 info = omap3isp_video_format_info(fmt->code);
890 if (info->uncompressed == pixelcode)
891 fmt->code = pixelcode;
892 break;
893 }
894
895
896 fmt->colorspace = V4L2_COLORSPACE_SRGB;
897 fmt->field = V4L2_FIELD_NONE;
898}
899
900
901
902
903
904
905
906
907static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
908 struct v4l2_subdev_fh *fh,
909 struct v4l2_subdev_mbus_code_enum *code)
910{
911 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
912 struct v4l2_mbus_framefmt *format;
913 const struct isp_format_info *info;
914
915 if (code->pad == CSI2_PAD_SINK) {
916 if (code->index >= ARRAY_SIZE(csi2_input_fmts))
917 return -EINVAL;
918
919 code->code = csi2_input_fmts[code->index];
920 } else {
921 format = __csi2_get_format(csi2, fh, CSI2_PAD_SINK,
922 V4L2_SUBDEV_FORMAT_TRY);
923 switch (code->index) {
924 case 0:
925
926 code->code = format->code;
927 break;
928 case 1:
929
930 info = omap3isp_video_format_info(format->code);
931 if (info->uncompressed == format->code)
932 return -EINVAL;
933
934 code->code = info->uncompressed;
935 break;
936 default:
937 return -EINVAL;
938 }
939 }
940
941 return 0;
942}
943
944static int csi2_enum_frame_size(struct v4l2_subdev *sd,
945 struct v4l2_subdev_fh *fh,
946 struct v4l2_subdev_frame_size_enum *fse)
947{
948 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
949 struct v4l2_mbus_framefmt format;
950
951 if (fse->index != 0)
952 return -EINVAL;
953
954 format.code = fse->code;
955 format.width = 1;
956 format.height = 1;
957 csi2_try_format(csi2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
958 fse->min_width = format.width;
959 fse->min_height = format.height;
960
961 if (format.code != fse->code)
962 return -EINVAL;
963
964 format.code = fse->code;
965 format.width = -1;
966 format.height = -1;
967 csi2_try_format(csi2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
968 fse->max_width = format.width;
969 fse->max_height = format.height;
970
971 return 0;
972}
973
974
975
976
977
978
979
980
981static int csi2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
982 struct v4l2_subdev_format *fmt)
983{
984 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
985 struct v4l2_mbus_framefmt *format;
986
987 format = __csi2_get_format(csi2, fh, fmt->pad, fmt->which);
988 if (format == NULL)
989 return -EINVAL;
990
991 fmt->format = *format;
992 return 0;
993}
994
995
996
997
998
999
1000
1001
1002static int csi2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1003 struct v4l2_subdev_format *fmt)
1004{
1005 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1006 struct v4l2_mbus_framefmt *format;
1007
1008 format = __csi2_get_format(csi2, fh, fmt->pad, fmt->which);
1009 if (format == NULL)
1010 return -EINVAL;
1011
1012 csi2_try_format(csi2, fh, fmt->pad, &fmt->format, fmt->which);
1013 *format = fmt->format;
1014
1015
1016 if (fmt->pad == CSI2_PAD_SINK) {
1017 format = __csi2_get_format(csi2, fh, CSI2_PAD_SOURCE,
1018 fmt->which);
1019 *format = fmt->format;
1020 csi2_try_format(csi2, fh, CSI2_PAD_SOURCE, format, fmt->which);
1021 }
1022
1023 return 0;
1024}
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035static int csi2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1036{
1037 struct v4l2_subdev_format format;
1038
1039 memset(&format, 0, sizeof(format));
1040 format.pad = CSI2_PAD_SINK;
1041 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
1042 format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
1043 format.format.width = 4096;
1044 format.format.height = 4096;
1045 csi2_set_format(sd, fh, &format);
1046
1047 return 0;
1048}
1049
1050
1051
1052
1053
1054
1055
1056
1057static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
1058{
1059 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1060 struct isp_device *isp = csi2->isp;
1061 struct isp_video *video_out = &csi2->video_out;
1062
1063 switch (enable) {
1064 case ISP_PIPELINE_STREAM_CONTINUOUS:
1065 if (omap3isp_csiphy_acquire(csi2->phy) < 0)
1066 return -ENODEV;
1067 if (csi2->output & CSI2_OUTPUT_MEMORY)
1068 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI2A_WRITE);
1069 csi2_configure(csi2);
1070 csi2_print_status(csi2);
1071
1072
1073
1074
1075
1076
1077
1078 if (csi2->output & CSI2_OUTPUT_MEMORY &&
1079 !(video_out->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED))
1080 break;
1081
1082 atomic_set(&csi2->stopping, 0);
1083 csi2_ctx_enable(isp, csi2, 0, 1);
1084 csi2_if_enable(isp, csi2, 1);
1085 isp_video_dmaqueue_flags_clr(video_out);
1086 break;
1087
1088 case ISP_PIPELINE_STREAM_STOPPED:
1089 if (csi2->state == ISP_PIPELINE_STREAM_STOPPED)
1090 return 0;
1091 if (omap3isp_module_sync_idle(&sd->entity, &csi2->wait,
1092 &csi2->stopping))
1093 dev_dbg(isp->dev, "%s: module stop timeout.\n",
1094 sd->name);
1095 csi2_ctx_enable(isp, csi2, 0, 0);
1096 csi2_if_enable(isp, csi2, 0);
1097 csi2_irq_ctx_set(isp, csi2, 0);
1098 omap3isp_csiphy_release(csi2->phy);
1099 isp_video_dmaqueue_flags_clr(video_out);
1100 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI2A_WRITE);
1101 break;
1102 }
1103
1104 csi2->state = enable;
1105 return 0;
1106}
1107
1108
1109static const struct v4l2_subdev_video_ops csi2_video_ops = {
1110 .s_stream = csi2_set_stream,
1111};
1112
1113
1114static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
1115 .enum_mbus_code = csi2_enum_mbus_code,
1116 .enum_frame_size = csi2_enum_frame_size,
1117 .get_fmt = csi2_get_format,
1118 .set_fmt = csi2_set_format,
1119};
1120
1121
1122static const struct v4l2_subdev_ops csi2_ops = {
1123 .video = &csi2_video_ops,
1124 .pad = &csi2_pad_ops,
1125};
1126
1127
1128static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
1129 .open = csi2_init_formats,
1130};
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144static int csi2_link_setup(struct media_entity *entity,
1145 const struct media_pad *local,
1146 const struct media_pad *remote, u32 flags)
1147{
1148 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1149 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1150 struct isp_csi2_ctrl_cfg *ctrl = &csi2->ctrl;
1151
1152
1153
1154
1155
1156
1157 switch (local->index | media_entity_type(remote->entity)) {
1158 case CSI2_PAD_SOURCE | MEDIA_ENT_T_DEVNODE:
1159 if (flags & MEDIA_LNK_FL_ENABLED) {
1160 if (csi2->output & ~CSI2_OUTPUT_MEMORY)
1161 return -EBUSY;
1162 csi2->output |= CSI2_OUTPUT_MEMORY;
1163 } else {
1164 csi2->output &= ~CSI2_OUTPUT_MEMORY;
1165 }
1166 break;
1167
1168 case CSI2_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
1169 if (flags & MEDIA_LNK_FL_ENABLED) {
1170 if (csi2->output & ~CSI2_OUTPUT_CCDC)
1171 return -EBUSY;
1172 csi2->output |= CSI2_OUTPUT_CCDC;
1173 } else {
1174 csi2->output &= ~CSI2_OUTPUT_CCDC;
1175 }
1176 break;
1177
1178 default:
1179
1180 return -EINVAL;
1181 }
1182
1183 ctrl->vp_only_enable =
1184 (csi2->output & CSI2_OUTPUT_MEMORY) ? false : true;
1185 ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_CCDC);
1186
1187 return 0;
1188}
1189
1190
1191static const struct media_entity_operations csi2_media_ops = {
1192 .link_setup = csi2_link_setup,
1193 .link_validate = v4l2_subdev_link_validate,
1194};
1195
1196void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2)
1197{
1198 v4l2_device_unregister_subdev(&csi2->subdev);
1199 omap3isp_video_unregister(&csi2->video_out);
1200}
1201
1202int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,
1203 struct v4l2_device *vdev)
1204{
1205 int ret;
1206
1207
1208 ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
1209 if (ret < 0)
1210 goto error;
1211
1212 ret = omap3isp_video_register(&csi2->video_out, vdev);
1213 if (ret < 0)
1214 goto error;
1215
1216 return 0;
1217
1218error:
1219 omap3isp_csi2_unregister_entities(csi2);
1220 return ret;
1221}
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232static int csi2_init_entities(struct isp_csi2_device *csi2)
1233{
1234 struct v4l2_subdev *sd = &csi2->subdev;
1235 struct media_pad *pads = csi2->pads;
1236 struct media_entity *me = &sd->entity;
1237 int ret;
1238
1239 v4l2_subdev_init(sd, &csi2_ops);
1240 sd->internal_ops = &csi2_internal_ops;
1241 strlcpy(sd->name, "OMAP3 ISP CSI2a", sizeof(sd->name));
1242
1243 sd->grp_id = 1 << 16;
1244 v4l2_set_subdevdata(sd, csi2);
1245 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1246
1247 pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1248 pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1249
1250 me->ops = &csi2_media_ops;
1251 ret = media_entity_init(me, CSI2_PADS_NUM, pads, 0);
1252 if (ret < 0)
1253 return ret;
1254
1255 csi2_init_formats(sd, NULL);
1256
1257
1258 csi2->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1259 csi2->video_out.ops = &csi2_ispvideo_ops;
1260 csi2->video_out.bpl_alignment = 32;
1261 csi2->video_out.bpl_zero_padding = 1;
1262 csi2->video_out.bpl_max = 0x1ffe0;
1263 csi2->video_out.isp = csi2->isp;
1264 csi2->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1265
1266 ret = omap3isp_video_init(&csi2->video_out, "CSI2a");
1267 if (ret < 0)
1268 goto error_video;
1269
1270
1271 ret = media_entity_create_link(&csi2->subdev.entity, CSI2_PAD_SOURCE,
1272 &csi2->video_out.video.entity, 0, 0);
1273 if (ret < 0)
1274 goto error_link;
1275
1276 return 0;
1277
1278error_link:
1279 omap3isp_video_cleanup(&csi2->video_out);
1280error_video:
1281 media_entity_cleanup(&csi2->subdev.entity);
1282 return ret;
1283}
1284
1285
1286
1287
1288int omap3isp_csi2_init(struct isp_device *isp)
1289{
1290 struct isp_csi2_device *csi2a = &isp->isp_csi2a;
1291 struct isp_csi2_device *csi2c = &isp->isp_csi2c;
1292 int ret;
1293
1294 csi2a->isp = isp;
1295 csi2a->available = 1;
1296 csi2a->regs1 = OMAP3_ISP_IOMEM_CSI2A_REGS1;
1297 csi2a->regs2 = OMAP3_ISP_IOMEM_CSI2A_REGS2;
1298 csi2a->phy = &isp->isp_csiphy2;
1299 csi2a->state = ISP_PIPELINE_STREAM_STOPPED;
1300 init_waitqueue_head(&csi2a->wait);
1301
1302 ret = csi2_init_entities(csi2a);
1303 if (ret < 0)
1304 return ret;
1305
1306 if (isp->revision == ISP_REVISION_15_0) {
1307 csi2c->isp = isp;
1308 csi2c->available = 1;
1309 csi2c->regs1 = OMAP3_ISP_IOMEM_CSI2C_REGS1;
1310 csi2c->regs2 = OMAP3_ISP_IOMEM_CSI2C_REGS2;
1311 csi2c->phy = &isp->isp_csiphy1;
1312 csi2c->state = ISP_PIPELINE_STREAM_STOPPED;
1313 init_waitqueue_head(&csi2c->wait);
1314 }
1315
1316 return 0;
1317}
1318
1319
1320
1321
1322void omap3isp_csi2_cleanup(struct isp_device *isp)
1323{
1324 struct isp_csi2_device *csi2a = &isp->isp_csi2a;
1325
1326 omap3isp_video_cleanup(&csi2a->video_out);
1327 media_entity_cleanup(&csi2a->subdev.entity);
1328}
1329