LXR linux/drivers/mmc/host/atmel-mci-regs.h

   1/*
   2 * Atmel MultiMedia Card Interface driver
   3 *
   4 * Copyright (C) 2004-2006 Atmel Corporation
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10
  11/*
  12 * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
  13 * Registers and bitfields marked with [2] are only available in MCI2
  14 */
  15
  16#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
  17#define __DRIVERS_MMC_ATMEL_MCI_H__
  18
  19/* MCI Register Definitions */
  20#define ATMCI_CR                        0x0000  /* Control */
  21# define ATMCI_CR_MCIEN                 (  1 <<  0)     /* MCI Enable */
  22# define ATMCI_CR_MCIDIS                (  1 <<  1)     /* MCI Disable */
  23# define ATMCI_CR_PWSEN                 (  1 <<  2)     /* Power Save Enable */
  24# define ATMCI_CR_PWSDIS                (  1 <<  3)     /* Power Save Disable */
  25# define ATMCI_CR_SWRST                 (  1 <<  7)     /* Software Reset */
  26#define ATMCI_MR                        0x0004  /* Mode */
  27# define ATMCI_MR_CLKDIV(x)             ((x) <<  0)     /* Clock Divider */
  28# define ATMCI_MR_PWSDIV(x)             ((x) <<  8)     /* Power Saving Divider */
  29# define ATMCI_MR_RDPROOF               (  1 << 11)     /* Read Proof */
  30# define ATMCI_MR_WRPROOF               (  1 << 12)     /* Write Proof */
  31# define ATMCI_MR_PDCFBYTE              (  1 << 13)     /* Force Byte Transfer */
  32# define ATMCI_MR_PDCPADV               (  1 << 14)     /* Padding Value */
  33# define ATMCI_MR_PDCMODE               (  1 << 15)     /* PDC-oriented Mode */
  34# define ATMCI_MR_CLKODD(x)             ((x) << 16)     /* LSB of Clock Divider */
  35#define ATMCI_DTOR                      0x0008  /* Data Timeout */
  36# define ATMCI_DTOCYC(x)                ((x) <<  0)     /* Data Timeout Cycles */
  37# define ATMCI_DTOMUL(x)                ((x) <<  4)     /* Data Timeout Multiplier */
  38#define ATMCI_SDCR                      0x000c  /* SD Card / SDIO */
  39# define ATMCI_SDCSEL_SLOT_A            (  0 <<  0)     /* Select SD slot A */
  40# define ATMCI_SDCSEL_SLOT_B            (  1 <<  0)     /* Select SD slot A */
  41# define ATMCI_SDCSEL_MASK              (  3 <<  0)
  42# define ATMCI_SDCBUS_1BIT              (  0 <<  6)     /* 1-bit data bus */
  43# define ATMCI_SDCBUS_4BIT              (  2 <<  6)     /* 4-bit data bus */
  44# define ATMCI_SDCBUS_8BIT              (  3 <<  6)     /* 8-bit data bus[2] */
  45# define ATMCI_SDCBUS_MASK              (  3 <<  6)
  46#define ATMCI_ARGR                      0x0010  /* Command Argument */
  47#define ATMCI_CMDR                      0x0014  /* Command */
  48# define ATMCI_CMDR_CMDNB(x)            ((x) <<  0)     /* Command Opcode */
  49# define ATMCI_CMDR_RSPTYP_NONE         (  0 <<  6)     /* No response */
  50# define ATMCI_CMDR_RSPTYP_48BIT        (  1 <<  6)     /* 48-bit response */
  51# define ATMCI_CMDR_RSPTYP_136BIT       (  2 <<  6)     /* 136-bit response */
  52# define ATMCI_CMDR_SPCMD_INIT          (  1 <<  8)     /* Initialization command */
  53# define ATMCI_CMDR_SPCMD_SYNC          (  2 <<  8)     /* Synchronized command */
  54# define ATMCI_CMDR_SPCMD_INT           (  4 <<  8)     /* Interrupt command */
  55# define ATMCI_CMDR_SPCMD_INTRESP       (  5 <<  8)     /* Interrupt response */
  56# define ATMCI_CMDR_OPDCMD              (  1 << 11)     /* Open Drain */
  57# define ATMCI_CMDR_MAXLAT_5CYC         (  0 << 12)     /* Max latency 5 cycles */
  58# define ATMCI_CMDR_MAXLAT_64CYC        (  1 << 12)     /* Max latency 64 cycles */
  59# define ATMCI_CMDR_START_XFER          (  1 << 16)     /* Start data transfer */
  60# define ATMCI_CMDR_STOP_XFER           (  2 << 16)     /* Stop data transfer */
  61# define ATMCI_CMDR_TRDIR_WRITE         (  0 << 18)     /* Write data */
  62# define ATMCI_CMDR_TRDIR_READ          (  1 << 18)     /* Read data */
  63# define ATMCI_CMDR_BLOCK               (  0 << 19)     /* Single-block transfer */
  64# define ATMCI_CMDR_MULTI_BLOCK         (  1 << 19)     /* Multi-block transfer */
  65# define ATMCI_CMDR_STREAM              (  2 << 19)     /* MMC Stream transfer */
  66# define ATMCI_CMDR_SDIO_BYTE           (  4 << 19)     /* SDIO Byte transfer */
  67# define ATMCI_CMDR_SDIO_BLOCK          (  5 << 19)     /* SDIO Block transfer */
  68# define ATMCI_CMDR_SDIO_SUSPEND        (  1 << 24)     /* SDIO Suspend Command */
  69# define ATMCI_CMDR_SDIO_RESUME         (  2 << 24)     /* SDIO Resume Command */
  70#define ATMCI_BLKR                      0x0018  /* Block */
  71# define ATMCI_BCNT(x)                  ((x) <<  0)     /* Data Block Count */
  72# define ATMCI_BLKLEN(x)                ((x) << 16)     /* Data Block Length */
  73#define ATMCI_CSTOR                     0x001c  /* Completion Signal Timeout[2] */
  74# define ATMCI_CSTOCYC(x)               ((x) <<  0)     /* CST cycles */
  75# define ATMCI_CSTOMUL(x)               ((x) <<  4)     /* CST multiplier */
  76#define ATMCI_RSPR                      0x0020  /* Response 0 */
  77#define ATMCI_RSPR1                     0x0024  /* Response 1 */
  78#define ATMCI_RSPR2                     0x0028  /* Response 2 */
  79#define ATMCI_RSPR3                     0x002c  /* Response 3 */
  80#define ATMCI_RDR                       0x0030  /* Receive Data */
  81#define ATMCI_TDR                       0x0034  /* Transmit Data */
  82#define ATMCI_SR                        0x0040  /* Status */
  83#define ATMCI_IER                       0x0044  /* Interrupt Enable */
  84#define ATMCI_IDR                       0x0048  /* Interrupt Disable */
  85#define ATMCI_IMR                       0x004c  /* Interrupt Mask */
  86# define ATMCI_CMDRDY                   (  1 <<   0)    /* Command Ready */
  87# define ATMCI_RXRDY                    (  1 <<   1)    /* Receiver Ready */
  88# define ATMCI_TXRDY                    (  1 <<   2)    /* Transmitter Ready */
  89# define ATMCI_BLKE                     (  1 <<   3)    /* Data Block Ended */
  90# define ATMCI_DTIP                     (  1 <<   4)    /* Data Transfer In Progress */
  91# define ATMCI_NOTBUSY                  (  1 <<   5)    /* Data Not Busy */
  92# define ATMCI_ENDRX                    (  1 <<   6)    /* End of RX Buffer */
  93# define ATMCI_ENDTX                    (  1 <<   7)    /* End of TX Buffer */
  94# define ATMCI_SDIOIRQA                 (  1 <<   8)    /* SDIO IRQ in slot A */
  95# define ATMCI_SDIOIRQB                 (  1 <<   9)    /* SDIO IRQ in slot B */
  96# define ATMCI_SDIOWAIT                 (  1 <<  12)    /* SDIO Read Wait Operation Status */
  97# define ATMCI_CSRCV                    (  1 <<  13)    /* CE-ATA Completion Signal Received */
  98# define ATMCI_RXBUFF                   (  1 <<  14)    /* RX Buffer Full */
  99# define ATMCI_TXBUFE                   (  1 <<  15)    /* TX Buffer Empty */
 100# define ATMCI_RINDE                    (  1 <<  16)    /* Response Index Error */
 101# define ATMCI_RDIRE                    (  1 <<  17)    /* Response Direction Error */
 102# define ATMCI_RCRCE                    (  1 <<  18)    /* Response CRC Error */
 103# define ATMCI_RENDE                    (  1 <<  19)    /* Response End Bit Error */
 104# define ATMCI_RTOE                     (  1 <<  20)    /* Response Time-Out Error */
 105# define ATMCI_DCRCE                    (  1 <<  21)    /* Data CRC Error */
 106# define ATMCI_DTOE                     (  1 <<  22)    /* Data Time-Out Error */
 107# define ATMCI_CSTOE                    (  1 <<  23)    /* Completion Signal Time-out Error */
 108# define ATMCI_BLKOVRE                  (  1 <<  24)    /* DMA Block Overrun Error */
 109# define ATMCI_DMADONE                  (  1 <<  25)    /* DMA Transfer Done */
 110# define ATMCI_FIFOEMPTY                (  1 <<  26)    /* FIFO Empty Flag */
 111# define ATMCI_XFRDONE                  (  1 <<  27)    /* Transfer Done Flag */
 112# define ATMCI_ACKRCV                   (  1 <<  28)    /* Boot Operation Acknowledge Received */
 113# define ATMCI_ACKRCVE                  (  1 <<  29)    /* Boot Operation Acknowledge Error */
 114# define ATMCI_OVRE                     (  1 <<  30)    /* RX Overrun Error */
 115# define ATMCI_UNRE                     (  1 <<  31)    /* TX Underrun Error */
 116#define ATMCI_DMA                       0x0050  /* DMA Configuration[2] */
 117# define ATMCI_DMA_OFFSET(x)            ((x) <<  0)     /* DMA Write Buffer Offset */
 118# define ATMCI_DMA_CHKSIZE(x)           ((x) <<  4)     /* DMA Channel Read and Write Chunk Size */
 119# define ATMCI_DMAEN                    (  1 <<  8)     /* DMA Hardware Handshaking Enable */
 120#define ATMCI_CFG                       0x0054  /* Configuration[2] */
 121# define ATMCI_CFG_FIFOMODE_1DATA       (  1 <<  0)     /* MCI Internal FIFO control mode */
 122# define ATMCI_CFG_FERRCTRL_COR         (  1 <<  4)     /* Flow Error flag reset control mode */
 123# define ATMCI_CFG_HSMODE               (  1 <<  8)     /* High Speed Mode */
 124# define ATMCI_CFG_LSYNC                (  1 << 12)     /* Synchronize on the last block */
 125#define ATMCI_WPMR                      0x00e4  /* Write Protection Mode[2] */
 126# define ATMCI_WP_EN                    (  1 <<  0)     /* WP Enable */
 127# define ATMCI_WP_KEY                   (0x4d4349 << 8) /* WP Key */
 128#define ATMCI_WPSR                      0x00e8  /* Write Protection Status[2] */
 129# define ATMCI_GET_WP_VS(x)             ((x) & 0x0f)
 130# define ATMCI_GET_WP_VSRC(x)           (((x) >> 8) & 0xffff)
 131#define ATMCI_VERSION                   0x00FC  /* Version */
 132#define ATMCI_FIFO_APERTURE             0x0200  /* FIFO Aperture[2] */
 133
 134/* This is not including the FIFO Aperture on MCI2 */
 135#define ATMCI_REGS_SIZE         0x100
 136
 137/* Register access macros */
 138#define atmci_readl(port,reg)                           \
 139        __raw_readl((port)->regs + reg)
 140#define atmci_writel(port,reg,value)                    \
 141        __raw_writel((value), (port)->regs + reg)
 142
 143/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
 144#ifdef CONFIG_AVR32
 145#       define ATMCI_PDC_CONNECTED      0
 146#else
 147#       define ATMCI_PDC_CONNECTED      1
 148#endif
 149
 150/*
 151 * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
 152 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 153 *
 154 * This can be done by finding most significant bit set.
 155 */
 156static inline unsigned int atmci_convert_chksize(unsigned int maxburst)
 157{
 158        if (maxburst > 1)
 159                return fls(maxburst) - 2;
 160        else
 161                return 0;
 162}
 163
 164#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
 165