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13#ifndef __DL2K_H__
14#define __DL2K_H__
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/string.h>
19#include <linux/timer.h>
20#include <linux/errno.h>
21#include <linux/ioport.h>
22#include <linux/slab.h>
23#include <linux/interrupt.h>
24#include <linux/pci.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/init.h>
29#include <linux/crc32.h>
30#include <linux/ethtool.h>
31#include <linux/mii.h>
32#include <linux/bitops.h>
33#include <asm/processor.h>
34#include <asm/io.h>
35#include <asm/uaccess.h>
36#include <linux/delay.h>
37#include <linux/spinlock.h>
38#include <linux/time.h>
39#define TX_RING_SIZE 256
40#define TX_QUEUE_LEN (TX_RING_SIZE - 1)
41#define RX_RING_SIZE 256
42#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
43#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
44
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51
52
53enum dl2x_offsets {
54
55 DMACtrl = 0x00,
56 RxDMAStatus = 0x08,
57 TFDListPtr0 = 0x10,
58 TFDListPtr1 = 0x14,
59 TxDMABurstThresh = 0x18,
60 TxDMAUrgentThresh = 0x19,
61 TxDMAPollPeriod = 0x1a,
62 RFDListPtr0 = 0x1c,
63 RFDListPtr1 = 0x20,
64 RxDMABurstThresh = 0x24,
65 RxDMAUrgentThresh = 0x25,
66 RxDMAPollPeriod = 0x26,
67 RxDMAIntCtrl = 0x28,
68 DebugCtrl = 0x2c,
69 ASICCtrl = 0x30,
70 FifoCtrl = 0x38,
71 RxEarlyThresh = 0x3a,
72 FlowOffThresh = 0x3c,
73 FlowOnThresh = 0x3e,
74 TxStartThresh = 0x44,
75 EepromData = 0x48,
76 EepromCtrl = 0x4a,
77 ExpromAddr = 0x4c,
78 Exprodata = 0x50,
79 WakeEvent = 0x51,
80 CountDown = 0x54,
81 IntStatusAck = 0x5a,
82 IntEnable = 0x5c,
83 IntStatus = 0x5e,
84 TxStatus = 0x60,
85 MACCtrl = 0x6c,
86 VLANTag = 0x70,
87 PhyCtrl = 0x76,
88 StationAddr0 = 0x78,
89 StationAddr1 = 0x7a,
90 StationAddr2 = 0x7c,
91 VLANId = 0x80,
92 MaxFrameSize = 0x86,
93 ReceiveMode = 0x88,
94 HashTable0 = 0x8c,
95 HashTable1 = 0x90,
96 RmonStatMask = 0x98,
97 StatMask = 0x9c,
98 RxJumboFrames = 0xbc,
99 TCPCheckSumErrors = 0xc0,
100 IPCheckSumErrors = 0xc2,
101 UDPCheckSumErrors = 0xc4,
102 TxJumboFrames = 0xf4,
103
104 OctetRcvOk = 0xa8,
105 McstOctetRcvOk = 0xac,
106 BcstOctetRcvOk = 0xb0,
107 FramesRcvOk = 0xb4,
108 McstFramesRcvdOk = 0xb8,
109 BcstFramesRcvdOk = 0xbe,
110 MacControlFramesRcvd = 0xc6,
111 FrameTooLongErrors = 0xc8,
112 InRangeLengthErrors = 0xca,
113 FramesCheckSeqErrors = 0xcc,
114 FramesLostRxErrors = 0xce,
115 OctetXmtOk = 0xd0,
116 McstOctetXmtOk = 0xd4,
117 BcstOctetXmtOk = 0xd8,
118 FramesXmtOk = 0xdc,
119 McstFramesXmtdOk = 0xe0,
120 FramesWDeferredXmt = 0xe4,
121 LateCollisions = 0xe8,
122 MultiColFrames = 0xec,
123 SingleColFrames = 0xf0,
124 BcstFramesXmtdOk = 0xf6,
125 CarrierSenseErrors = 0xf8,
126 MacControlFramesXmtd = 0xfa,
127 FramesAbortXSColls = 0xfc,
128 FramesWEXDeferal = 0xfe,
129
130 EtherStatsCollisions = 0x100,
131 EtherStatsOctetsTransmit = 0x104,
132 EtherStatsPktsTransmit = 0x108,
133 EtherStatsPkts64OctetTransmit = 0x10c,
134 EtherStats65to127OctetsTransmit = 0x110,
135 EtherStatsPkts128to255OctetsTransmit = 0x114,
136 EtherStatsPkts256to511OctetsTransmit = 0x118,
137 EtherStatsPkts512to1023OctetsTransmit = 0x11c,
138 EtherStatsPkts1024to1518OctetsTransmit = 0x120,
139 EtherStatsCRCAlignErrors = 0x124,
140 EtherStatsUndersizePkts = 0x128,
141 EtherStatsFragments = 0x12c,
142 EtherStatsJabbers = 0x130,
143 EtherStatsOctets = 0x134,
144 EtherStatsPkts = 0x138,
145 EtherStats64Octets = 0x13c,
146 EtherStatsPkts65to127Octets = 0x140,
147 EtherStatsPkts128to255Octets = 0x144,
148 EtherStatsPkts256to511Octets = 0x148,
149 EtherStatsPkts512to1023Octets = 0x14c,
150 EtherStatsPkts1024to1518Octets = 0x150,
151};
152
153
154enum IntStatus_bits {
155 InterruptStatus = 0x0001,
156 HostError = 0x0002,
157 MACCtrlFrame = 0x0008,
158 TxComplete = 0x0004,
159 RxComplete = 0x0010,
160 RxEarly = 0x0020,
161 IntRequested = 0x0040,
162 UpdateStats = 0x0080,
163 LinkEvent = 0x0100,
164 TxDMAComplete = 0x0200,
165 RxDMAComplete = 0x0400,
166 RFDListEnd = 0x0800,
167 RxDMAPriority = 0x1000,
168};
169
170
171enum ReceiveMode_bits {
172 ReceiveUnicast = 0x0001,
173 ReceiveMulticast = 0x0002,
174 ReceiveBroadcast = 0x0004,
175 ReceiveAllFrames = 0x0008,
176 ReceiveMulticastHash = 0x0010,
177 ReceiveIPMulticast = 0x0020,
178 ReceiveVLANMatch = 0x0100,
179 ReceiveVLANHash = 0x0200,
180};
181
182enum MACCtrl_bits {
183 DuplexSelect = 0x20,
184 TxFlowControlEnable = 0x80,
185 RxFlowControlEnable = 0x0100,
186 RcvFCS = 0x200,
187 AutoVLANtagging = 0x1000,
188 AutoVLANuntagging = 0x2000,
189 StatsEnable = 0x00200000,
190 StatsDisable = 0x00400000,
191 StatsEnabled = 0x00800000,
192 TxEnable = 0x01000000,
193 TxDisable = 0x02000000,
194 TxEnabled = 0x04000000,
195 RxEnable = 0x08000000,
196 RxDisable = 0x10000000,
197 RxEnabled = 0x20000000,
198};
199
200enum ASICCtrl_LoWord_bits {
201 PhyMedia = 0x0080,
202};
203
204enum ASICCtrl_HiWord_bits {
205 GlobalReset = 0x0001,
206 RxReset = 0x0002,
207 TxReset = 0x0004,
208 DMAReset = 0x0008,
209 FIFOReset = 0x0010,
210 NetworkReset = 0x0020,
211 HostReset = 0x0040,
212 ResetBusy = 0x0400,
213};
214
215
216enum TFC_bits {
217 DwordAlign = 0x00000000,
218 WordAlignDisable = 0x00030000,
219 WordAlign = 0x00020000,
220 TCPChecksumEnable = 0x00040000,
221 UDPChecksumEnable = 0x00080000,
222 IPChecksumEnable = 0x00100000,
223 FCSAppendDisable = 0x00200000,
224 TxIndicate = 0x00400000,
225 TxDMAIndicate = 0x00800000,
226 FragCountShift = 24,
227 VLANTagInsert = 0x0000000010000000,
228 TFDDone = 0x80000000,
229 VIDShift = 32,
230 UsePriorityShift = 48,
231};
232
233
234enum RFS_bits {
235 RxFIFOOverrun = 0x00010000,
236 RxRuntFrame = 0x00020000,
237 RxAlignmentError = 0x00040000,
238 RxFCSError = 0x00080000,
239 RxOverSizedFrame = 0x00100000,
240 RxLengthError = 0x00200000,
241 VLANDetected = 0x00400000,
242 TCPDetected = 0x00800000,
243 TCPError = 0x01000000,
244 UDPDetected = 0x02000000,
245 UDPError = 0x04000000,
246 IPDetected = 0x08000000,
247 IPError = 0x10000000,
248 FrameStart = 0x20000000,
249 FrameEnd = 0x40000000,
250 RFDDone = 0x80000000,
251 TCIShift = 32,
252 RFS_Errors = 0x003f0000,
253};
254
255#define MII_RESET_TIME_OUT 10000
256
257enum _mii_reg {
258 MII_PHY_SCR = 16,
259};
260
261
262enum _pcs_reg {
263 PCS_BMCR = 0,
264 PCS_BMSR = 1,
265 PCS_ANAR = 4,
266 PCS_ANLPAR = 5,
267 PCS_ANER = 6,
268 PCS_ANNPT = 7,
269 PCS_ANLPRNP = 8,
270 PCS_ESR = 15,
271};
272
273
274enum _mii_esr {
275 MII_ESR_1000BX_FD = 0x8000,
276 MII_ESR_1000BX_HD = 0x4000,
277 MII_ESR_1000BT_FD = 0x2000,
278 MII_ESR_1000BT_HD = 0x1000,
279};
280
281#if 0
282typedef union t_MII_PHY_SCR {
283 u16 image;
284 struct {
285 u16 disable_jabber:1;
286 u16 polarity_reversal:1;
287 u16 SEQ_test:1;
288 u16 _bit_3:1;
289 u16 disable_CLK125:1;
290 u16 mdi_crossover_mode:2;
291 u16 enable_ext_dist:1;
292 u16 _bit_8_9:2;
293 u16 force_link:1;
294 u16 assert_CRS:1;
295 u16 rcv_fifo_depth:2;
296 u16 xmit_fifo_depth:2;
297 } bits;
298} PHY_SCR_t, *PPHY_SCR_t;
299#endif
300
301typedef enum t_MII_ADMIN_STATUS {
302 adm_reset,
303 adm_operational,
304 adm_loopback,
305 adm_power_down,
306 adm_isolate
307} MII_ADMIN_t, *PMII_ADMIN_t;
308
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311
312
313enum _pcs_anar {
314 PCS_ANAR_NEXT_PAGE = 0x8000,
315 PCS_ANAR_REMOTE_FAULT = 0x3000,
316 PCS_ANAR_ASYMMETRIC = 0x0100,
317 PCS_ANAR_PAUSE = 0x0080,
318 PCS_ANAR_HALF_DUPLEX = 0x0040,
319 PCS_ANAR_FULL_DUPLEX = 0x0020,
320};
321
322enum _pcs_anlpar {
323 PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE,
324 PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT,
325 PCS_ANLPAR_ASYMMETRIC = PCS_ANAR_ASYMMETRIC,
326 PCS_ANLPAR_PAUSE = PCS_ANAR_PAUSE,
327 PCS_ANLPAR_HALF_DUPLEX = PCS_ANAR_HALF_DUPLEX,
328 PCS_ANLPAR_FULL_DUPLEX = PCS_ANAR_FULL_DUPLEX,
329};
330
331typedef struct t_SROM {
332 u16 config_param;
333 u16 asic_ctrl;
334 u16 sub_vendor_id;
335 u16 sub_system_id;
336 u16 reserved1[12];
337 u8 mac_addr[6];
338 u8 reserved2[10];
339 u8 sib[204];
340 u32 crc;
341} SROM_t, *PSROM_t;
342
343
344struct ioctl_data {
345 char signature[10];
346 int cmd;
347 int len;
348 char *data;
349};
350
351
352struct netdev_desc {
353 __le64 next_desc;
354 __le64 status;
355 __le64 fraginfo;
356};
357
358#define PRIV_ALIGN 15
359
360
361struct netdev_private {
362
363 struct netdev_desc *rx_ring;
364 struct netdev_desc *tx_ring;
365 struct sk_buff *rx_skbuff[RX_RING_SIZE];
366 struct sk_buff *tx_skbuff[TX_RING_SIZE];
367 dma_addr_t tx_ring_dma;
368 dma_addr_t rx_ring_dma;
369 struct pci_dev *pdev;
370 void __iomem *ioaddr;
371 void __iomem *eeprom_addr;
372 spinlock_t tx_lock;
373 spinlock_t rx_lock;
374 struct net_device_stats stats;
375 unsigned int rx_buf_sz;
376 unsigned int speed;
377 unsigned int vlan;
378 unsigned int chip_id;
379 unsigned int rx_coalesce;
380 unsigned int rx_timeout;
381 unsigned int tx_coalesce;
382 unsigned int full_duplex:1;
383 unsigned int an_enable:2;
384 unsigned int jumbo:1;
385 unsigned int coalesce:1;
386 unsigned int tx_flow:1;
387 unsigned int rx_flow:1;
388 unsigned int phy_media:1;
389 unsigned int link_status:1;
390 struct netdev_desc *last_tx;
391 unsigned long cur_rx, old_rx;
392 unsigned long cur_tx, old_tx;
393 struct timer_list timer;
394 int wake_polarity;
395 char name[256];
396 u8 duplex_polarity;
397 u16 mcast_filter[4];
398 u16 advertising;
399 u16 negotiate;
400 int phy_addr;
401};
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411
412static DEFINE_PCI_DEVICE_TABLE(rio_pci_tbl) = {
413 {0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, },
414 {0x13f0, 0x1021, PCI_ANY_ID, PCI_ANY_ID, },
415 { }
416};
417MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
418#define TX_TIMEOUT (4*HZ)
419#define PACKET_SIZE 1536
420#define MAX_JUMBO 8000
421#define RIO_IO_SIZE 340
422#define DEFAULT_RXC 5
423#define DEFAULT_RXT 750
424#define DEFAULT_TXC 1
425#define MAX_TXC 8
426#endif
427