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34#ifndef _MLX4_EN_H_
35#define _MLX4_EN_H_
36
37#include <linux/bitops.h>
38#include <linux/compiler.h>
39#include <linux/list.h>
40#include <linux/mutex.h>
41#include <linux/netdevice.h>
42#include <linux/if_vlan.h>
43#ifdef CONFIG_MLX4_EN_DCB
44#include <linux/dcbnl.h>
45#endif
46#include <linux/cpu_rmap.h>
47
48#include <linux/mlx4/device.h>
49#include <linux/mlx4/qp.h>
50#include <linux/mlx4/cq.h>
51#include <linux/mlx4/srq.h>
52#include <linux/mlx4/doorbell.h>
53#include <linux/mlx4/cmd.h>
54
55#include "en_port.h"
56
57#define DRV_NAME "mlx4_en"
58#define DRV_VERSION "2.0"
59#define DRV_RELDATE "Dec 2011"
60
61#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
62
63
64
65
66
67
68#define MLX4_EN_PAGE_SHIFT 12
69#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
70#define MAX_RX_RINGS 16
71#define MIN_RX_RINGS 4
72#define TXBB_SIZE 64
73#define HEADROOM (2048 / TXBB_SIZE + 1)
74#define STAMP_STRIDE 64
75#define STAMP_DWORDS (STAMP_STRIDE / 4)
76#define STAMP_SHIFT 31
77#define STAMP_VAL 0x7fffffff
78#define STATS_DELAY (HZ / 4)
79#define MAX_NUM_OF_FS_RULES 256
80
81#define MLX4_EN_FILTER_HASH_SHIFT 4
82#define MLX4_EN_FILTER_EXPIRY_QUOTA 60
83
84
85#define MAX_DESC_SIZE 512
86#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
87
88
89
90
91
92#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
93
94
95#define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
96#define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE)
97
98#define MLX4_EN_MAX_LRO_DESCRIPTORS 32
99
100
101
102enum {
103 FRAG_SZ0 = 512 - NET_IP_ALIGN,
104 FRAG_SZ1 = 1024,
105 FRAG_SZ2 = 4096,
106 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
107};
108#define MLX4_EN_MAX_RX_FRAGS 4
109
110
111#define MLX4_EN_MAX_TX_SIZE 8192
112#define MLX4_EN_MAX_RX_SIZE 8192
113
114
115#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
116#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
117
118#define MLX4_EN_SMALL_PKT_SIZE 64
119#define MLX4_EN_MAX_TX_RING_P_UP 32
120#define MLX4_EN_NUM_UP 8
121#define MLX4_EN_DEF_TX_RING_SIZE 512
122#define MLX4_EN_DEF_RX_RING_SIZE 1024
123
124
125#define MLX4_EN_RX_COAL_TARGET 44
126#define MLX4_EN_RX_COAL_TIME 0x10
127
128#define MLX4_EN_TX_COAL_PKTS 16
129#define MLX4_EN_TX_COAL_TIME 0x80
130
131#define MLX4_EN_RX_RATE_LOW 400000
132#define MLX4_EN_RX_COAL_TIME_LOW 0
133#define MLX4_EN_RX_RATE_HIGH 450000
134#define MLX4_EN_RX_COAL_TIME_HIGH 128
135#define MLX4_EN_RX_SIZE_THRESH 1024
136#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
137#define MLX4_EN_SAMPLE_INTERVAL 0
138#define MLX4_EN_AVG_PKT_SMALL 256
139
140#define MLX4_EN_AUTO_CONF 0xffff
141
142#define MLX4_EN_DEF_RX_PAUSE 1
143#define MLX4_EN_DEF_TX_PAUSE 1
144
145
146
147#define MLX4_EN_TX_POLL_MODER 16
148#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
149
150#define ETH_LLC_SNAP_SIZE 8
151
152#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
153#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
154#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
155
156#define MLX4_EN_MIN_MTU 46
157#define ETH_BCAST 0xffffffffffffULL
158
159#define MLX4_EN_LOOPBACK_RETRIES 5
160#define MLX4_EN_LOOPBACK_TIMEOUT 100
161
162#ifdef MLX4_EN_PERF_STAT
163
164#define AVG_SIZE 128
165#define AVG_FACTOR 1024
166#define NUM_PERF_STATS NUM_PERF_COUNTERS
167
168#define INC_PERF_COUNTER(cnt) (++(cnt))
169#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
170#define AVG_PERF_COUNTER(cnt, sample) \
171 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
172#define GET_PERF_COUNTER(cnt) (cnt)
173#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
174
175#else
176
177#define NUM_PERF_STATS 0
178#define INC_PERF_COUNTER(cnt) do {} while (0)
179#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
180#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
181#define GET_PERF_COUNTER(cnt) (0)
182#define GET_AVG_PERF_COUNTER(cnt) (0)
183#endif
184
185
186
187
188
189enum cq_type {
190 RX = 0,
191 TX = 1,
192};
193
194
195
196
197
198#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
199#define XNOR(x, y) (!(x) == !(y))
200#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
201
202
203struct mlx4_en_tx_info {
204 struct sk_buff *skb;
205 u32 nr_txbb;
206 u32 nr_bytes;
207 u8 linear;
208 u8 data_offset;
209 u8 inl;
210};
211
212
213#define MLX4_EN_BIT_DESC_OWN 0x80000000
214#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
215#define MLX4_EN_MEMTYPE_PAD 0x100
216#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
217
218
219struct mlx4_en_tx_desc {
220 struct mlx4_wqe_ctrl_seg ctrl;
221 union {
222 struct mlx4_wqe_data_seg data;
223 struct mlx4_wqe_lso_seg lso;
224 struct mlx4_wqe_inline_seg inl;
225 };
226};
227
228#define MLX4_EN_USE_SRQ 0x01000000
229
230#define MLX4_EN_CX3_LOW_ID 0x1000
231#define MLX4_EN_CX3_HIGH_ID 0x1005
232
233struct mlx4_en_rx_alloc {
234 struct page *page;
235 dma_addr_t dma;
236 u16 offset;
237};
238
239struct mlx4_en_tx_ring {
240 struct mlx4_hwq_resources wqres;
241 u32 size ;
242 u32 size_mask;
243 u16 stride;
244 u16 cqn;
245 u32 prod;
246 u32 cons;
247 u32 buf_size;
248 u32 doorbell_qpn;
249 void *buf;
250 u16 poll_cnt;
251 struct mlx4_en_tx_info *tx_info;
252 u8 *bounce_buf;
253 u32 last_nr_txbb;
254 struct mlx4_qp qp;
255 struct mlx4_qp_context context;
256 int qpn;
257 enum mlx4_qp_state qp_state;
258 struct mlx4_srq dummy;
259 unsigned long bytes;
260 unsigned long packets;
261 unsigned long tx_csum;
262 struct mlx4_bf bf;
263 bool bf_enabled;
264 struct netdev_queue *tx_queue;
265};
266
267struct mlx4_en_rx_desc {
268
269 struct mlx4_wqe_data_seg data[0];
270};
271
272struct mlx4_en_rx_ring {
273 struct mlx4_hwq_resources wqres;
274 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
275 u32 size ;
276 u32 actual_size;
277 u32 size_mask;
278 u16 stride;
279 u16 log_stride;
280 u16 cqn;
281 u32 prod;
282 u32 cons;
283 u32 buf_size;
284 u8 fcs_del;
285 void *buf;
286 void *rx_info;
287 unsigned long bytes;
288 unsigned long packets;
289 unsigned long csum_ok;
290 unsigned long csum_none;
291};
292
293
294static inline int mlx4_en_can_lro(__be16 status)
295{
296 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
297 MLX4_CQE_STATUS_IPV4F |
298 MLX4_CQE_STATUS_IPV6 |
299 MLX4_CQE_STATUS_IPV4OPT |
300 MLX4_CQE_STATUS_TCP |
301 MLX4_CQE_STATUS_UDP |
302 MLX4_CQE_STATUS_IPOK)) ==
303 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
304 MLX4_CQE_STATUS_IPOK |
305 MLX4_CQE_STATUS_TCP);
306}
307
308struct mlx4_en_cq {
309 struct mlx4_cq mcq;
310 struct mlx4_hwq_resources wqres;
311 int ring;
312 spinlock_t lock;
313 struct net_device *dev;
314 struct napi_struct napi;
315 int size;
316 int buf_size;
317 unsigned vector;
318 enum cq_type is_tx;
319 u16 moder_time;
320 u16 moder_cnt;
321 struct mlx4_cqe *buf;
322#define MLX4_EN_OPCODE_ERROR 0x1e
323};
324
325struct mlx4_en_port_profile {
326 u32 flags;
327 u32 tx_ring_num;
328 u32 rx_ring_num;
329 u32 tx_ring_size;
330 u32 rx_ring_size;
331 u8 rx_pause;
332 u8 rx_ppp;
333 u8 tx_pause;
334 u8 tx_ppp;
335 int rss_rings;
336};
337
338struct mlx4_en_profile {
339 int rss_xor;
340 int udp_rss;
341 u8 rss_mask;
342 u32 active_ports;
343 u32 small_pkt_int;
344 u8 no_reset;
345 u8 num_tx_rings_p_up;
346 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
347};
348
349struct mlx4_en_dev {
350 struct mlx4_dev *dev;
351 struct pci_dev *pdev;
352 struct mutex state_lock;
353 struct net_device *pndev[MLX4_MAX_PORTS + 1];
354 u32 port_cnt;
355 bool device_up;
356 struct mlx4_en_profile profile;
357 u32 LSO_support;
358 struct workqueue_struct *workqueue;
359 struct device *dma_device;
360 void __iomem *uar_map;
361 struct mlx4_uar priv_uar;
362 struct mlx4_mr mr;
363 u32 priv_pdn;
364 spinlock_t uar_lock;
365 u8 mac_removed[MLX4_MAX_PORTS + 1];
366};
367
368
369struct mlx4_en_rss_map {
370 int base_qpn;
371 struct mlx4_qp qps[MAX_RX_RINGS];
372 enum mlx4_qp_state state[MAX_RX_RINGS];
373 struct mlx4_qp indir_qp;
374 enum mlx4_qp_state indir_state;
375};
376
377struct mlx4_en_port_state {
378 int link_state;
379 int link_speed;
380 int transciver;
381};
382
383struct mlx4_en_pkt_stats {
384 unsigned long broadcast;
385 unsigned long rx_prio[8];
386 unsigned long tx_prio[8];
387#define NUM_PKT_STATS 17
388};
389
390struct mlx4_en_port_stats {
391 unsigned long tso_packets;
392 unsigned long queue_stopped;
393 unsigned long wake_queue;
394 unsigned long tx_timeout;
395 unsigned long rx_alloc_failed;
396 unsigned long rx_chksum_good;
397 unsigned long rx_chksum_none;
398 unsigned long tx_chksum_offload;
399#define NUM_PORT_STATS 8
400};
401
402struct mlx4_en_perf_stats {
403 u32 tx_poll;
404 u64 tx_pktsz_avg;
405 u32 inflight_avg;
406 u16 tx_coal_avg;
407 u16 rx_coal_avg;
408 u32 napi_quota;
409#define NUM_PERF_COUNTERS 6
410};
411
412enum mlx4_en_mclist_act {
413 MCLIST_NONE,
414 MCLIST_REM,
415 MCLIST_ADD,
416};
417
418struct mlx4_en_mc_list {
419 struct list_head list;
420 enum mlx4_en_mclist_act action;
421 u8 addr[ETH_ALEN];
422 u64 reg_id;
423};
424
425struct mlx4_en_frag_info {
426 u16 frag_size;
427 u16 frag_prefix_size;
428 u16 frag_stride;
429 u16 frag_align;
430 u16 last_offset;
431
432};
433
434#ifdef CONFIG_MLX4_EN_DCB
435
436#define MLX4_EN_BW_MIN 1
437#define MLX4_EN_BW_MAX 100
438
439#define MLX4_EN_TC_ETS 7
440
441#endif
442
443struct ethtool_flow_id {
444 struct ethtool_rx_flow_spec flow_spec;
445 u64 id;
446};
447
448struct mlx4_en_priv {
449 struct mlx4_en_dev *mdev;
450 struct mlx4_en_port_profile *prof;
451 struct net_device *dev;
452 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
453 struct net_device_stats stats;
454 struct net_device_stats ret_stats;
455 struct mlx4_en_port_state port_state;
456 spinlock_t stats_lock;
457 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
458
459 unsigned long last_moder_packets[MAX_RX_RINGS];
460 unsigned long last_moder_tx_packets;
461 unsigned long last_moder_bytes[MAX_RX_RINGS];
462 unsigned long last_moder_jiffies;
463 int last_moder_time[MAX_RX_RINGS];
464 u16 rx_usecs;
465 u16 rx_frames;
466 u16 tx_usecs;
467 u16 tx_frames;
468 u32 pkt_rate_low;
469 u16 rx_usecs_low;
470 u32 pkt_rate_high;
471 u16 rx_usecs_high;
472 u16 sample_interval;
473 u16 adaptive_rx_coal;
474 u32 msg_enable;
475 u32 loopback_ok;
476 u32 validate_loopback;
477
478 struct mlx4_hwq_resources res;
479 int link_state;
480 int last_link_state;
481 bool port_up;
482 int port;
483 int registered;
484 int allocated;
485 int stride;
486 u64 mac;
487 int mac_index;
488 unsigned max_mtu;
489 int base_qpn;
490
491 struct mlx4_en_rss_map rss_map;
492 __be32 ctrl_flags;
493 u32 flags;
494#define MLX4_EN_FLAG_PROMISC 0x1
495#define MLX4_EN_FLAG_MC_PROMISC 0x2
496 u32 tx_ring_num;
497 u32 rx_ring_num;
498 u32 rx_skb_size;
499 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
500 u16 num_frags;
501 u16 log_rx_info;
502
503 struct mlx4_en_tx_ring *tx_ring;
504 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
505 struct mlx4_en_cq *tx_cq;
506 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
507 struct mlx4_qp drop_qp;
508 struct work_struct mcast_task;
509 struct work_struct mac_task;
510 struct work_struct watchdog_task;
511 struct work_struct linkstate_task;
512 struct delayed_work stats_task;
513 struct mlx4_en_perf_stats pstats;
514 struct mlx4_en_pkt_stats pkstats;
515 struct mlx4_en_port_stats port_stats;
516 u64 stats_bitmap;
517 struct list_head mc_list;
518 struct list_head curr_list;
519 u64 broadcast_id;
520 struct mlx4_en_stat_out_mbox hw_stats;
521 int vids[128];
522 bool wol;
523 struct device *ddev;
524 int base_tx_qpn;
525
526#ifdef CONFIG_MLX4_EN_DCB
527 struct ieee_ets ets;
528 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
529#endif
530#ifdef CONFIG_RFS_ACCEL
531 spinlock_t filters_lock;
532 int last_filter_id;
533 struct list_head filters;
534 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
535#endif
536
537};
538
539enum mlx4_en_wol {
540 MLX4_EN_WOL_MAGIC = (1ULL << 61),
541 MLX4_EN_WOL_ENABLED = (1ULL << 62),
542};
543
544#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
545
546void mlx4_en_destroy_netdev(struct net_device *dev);
547int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
548 struct mlx4_en_port_profile *prof);
549
550int mlx4_en_start_port(struct net_device *dev);
551void mlx4_en_stop_port(struct net_device *dev);
552
553void mlx4_en_free_resources(struct mlx4_en_priv *priv);
554int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
555
556int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
557 int entries, int ring, enum cq_type mode);
558void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
559int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
560 int cq_idx);
561void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
562int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
563int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
564
565void mlx4_en_tx_irq(struct mlx4_cq *mcq);
566u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
567netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
568
569int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
570 int qpn, u32 size, u16 stride);
571void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
572int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
573 struct mlx4_en_tx_ring *ring,
574 int cq, int user_prio);
575void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
576 struct mlx4_en_tx_ring *ring);
577
578int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
579 struct mlx4_en_rx_ring *ring,
580 u32 size, u16 stride);
581void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
582 struct mlx4_en_rx_ring *ring,
583 u32 size, u16 stride);
584int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
585void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
586 struct mlx4_en_rx_ring *ring);
587int mlx4_en_process_rx_cq(struct net_device *dev,
588 struct mlx4_en_cq *cq,
589 int budget);
590int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
591void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
592 int is_tx, int rss, int qpn, int cqn, int user_prio,
593 struct mlx4_qp_context *context);
594void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
595int mlx4_en_map_buffer(struct mlx4_buf *buf);
596void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
597
598void mlx4_en_calc_rx_buf(struct net_device *dev);
599int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
600void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
601int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
602void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
603int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
604void mlx4_en_rx_irq(struct mlx4_cq *mcq);
605
606int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
607int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
608
609int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
610int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
611
612#ifdef CONFIG_MLX4_EN_DCB
613extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
614#endif
615
616#ifdef CONFIG_RFS_ACCEL
617void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
618 struct mlx4_en_rx_ring *rx_ring);
619#endif
620
621#define MLX4_EN_NUM_SELF_TEST 5
622void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
623u64 mlx4_en_mac_to_u64(u8 *addr);
624
625
626
627
628extern const struct ethtool_ops mlx4_en_ethtool_ops;
629
630
631
632
633
634
635
636__printf(3, 4)
637int en_print(const char *level, const struct mlx4_en_priv *priv,
638 const char *format, ...);
639
640#define en_dbg(mlevel, priv, format, arg...) \
641do { \
642 if (NETIF_MSG_##mlevel & priv->msg_enable) \
643 en_print(KERN_DEBUG, priv, format, ##arg); \
644} while (0)
645#define en_warn(priv, format, arg...) \
646 en_print(KERN_WARNING, priv, format, ##arg)
647#define en_err(priv, format, arg...) \
648 en_print(KERN_ERR, priv, format, ##arg)
649#define en_info(priv, format, arg...) \
650 en_print(KERN_INFO, priv, format, ## arg)
651
652#define mlx4_err(mdev, format, arg...) \
653 pr_err("%s %s: " format, DRV_NAME, \
654 dev_name(&mdev->pdev->dev), ##arg)
655#define mlx4_info(mdev, format, arg...) \
656 pr_info("%s %s: " format, DRV_NAME, \
657 dev_name(&mdev->pdev->dev), ##arg)
658#define mlx4_warn(mdev, format, arg...) \
659 pr_warning("%s %s: " format, DRV_NAME, \
660 dev_name(&mdev->pdev->dev), ##arg)
661
662#endif
663
