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17#ifndef MAC_H
18#define MAC_H
19
20#define set11nTries(_series, _index) \
21 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
22
23#define set11nRate(_series, _index) \
24 (SM((_series)[_index].Rate, AR_XmitRate##_index))
25
26#define set11nPktDurRTSCTS(_series, _index) \
27 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
28 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
29 AR_RTSCTSQual##_index : 0))
30
31#define set11nRateFlags(_series, _index) \
32 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
33 AR_2040_##_index : 0) \
34 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
35 AR_GI##_index : 0) \
36 |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \
37 AR_STBC##_index : 0) \
38 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
39
40#define CCK_SIFS_TIME 10
41#define CCK_PREAMBLE_BITS 144
42#define CCK_PLCP_BITS 48
43
44#define OFDM_SIFS_TIME 16
45#define OFDM_PREAMBLE_TIME 20
46#define OFDM_PLCP_BITS 22
47#define OFDM_SYMBOL_TIME 4
48
49#define OFDM_SIFS_TIME_HALF 32
50#define OFDM_PREAMBLE_TIME_HALF 40
51#define OFDM_PLCP_BITS_HALF 22
52#define OFDM_SYMBOL_TIME_HALF 8
53
54#define OFDM_SIFS_TIME_QUARTER 64
55#define OFDM_PREAMBLE_TIME_QUARTER 80
56#define OFDM_PLCP_BITS_QUARTER 22
57#define OFDM_SYMBOL_TIME_QUARTER 16
58
59#define INIT_AIFS 2
60#define INIT_CWMIN 15
61#define INIT_CWMIN_11B 31
62#define INIT_CWMAX 1023
63#define INIT_SH_RETRY 10
64#define INIT_LG_RETRY 10
65#define INIT_SSH_RETRY 32
66#define INIT_SLG_RETRY 32
67
68#define ATH9K_SLOT_TIME_6 6
69#define ATH9K_SLOT_TIME_9 9
70#define ATH9K_SLOT_TIME_20 20
71
72#define ATH9K_TXERR_XRETRY 0x01
73#define ATH9K_TXERR_FILT 0x02
74#define ATH9K_TXERR_FIFO 0x04
75#define ATH9K_TXERR_XTXOP 0x08
76#define ATH9K_TXERR_TIMER_EXPIRED 0x10
77#define ATH9K_TX_ACKED 0x20
78#define ATH9K_TX_FLUSH 0x40
79#define ATH9K_TXERR_MASK \
80 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \
81 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED | ATH9K_TX_FLUSH)
82
83#define ATH9K_TX_BA 0x01
84#define ATH9K_TX_PWRMGMT 0x02
85#define ATH9K_TX_DESC_CFG_ERR 0x04
86#define ATH9K_TX_DATA_UNDERRUN 0x08
87#define ATH9K_TX_DELIM_UNDERRUN 0x10
88#define ATH9K_TX_SW_FILTERED 0x80
89
90
91#define MIN_TX_FIFO_THRESHOLD 0x1
92
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97
98#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
99
100struct ath_tx_status {
101 u32 ts_tstamp;
102 u16 ts_seqnum;
103 u8 ts_status;
104 u8 ts_rateindex;
105 int8_t ts_rssi;
106 u8 ts_shortretry;
107 u8 ts_longretry;
108 u8 ts_virtcol;
109 u8 ts_flags;
110 int8_t ts_rssi_ctl0;
111 int8_t ts_rssi_ctl1;
112 int8_t ts_rssi_ctl2;
113 int8_t ts_rssi_ext0;
114 int8_t ts_rssi_ext1;
115 int8_t ts_rssi_ext2;
116 u8 qid;
117 u16 desc_id;
118 u8 tid;
119 u32 ba_low;
120 u32 ba_high;
121 u32 evm0;
122 u32 evm1;
123 u32 evm2;
124};
125
126struct ath_rx_status {
127 u32 rs_tstamp;
128 u16 rs_datalen;
129 u8 rs_status;
130 u8 rs_phyerr;
131 int8_t rs_rssi;
132 u8 rs_keyix;
133 u8 rs_rate;
134 u8 rs_antenna;
135 u8 rs_more;
136 int8_t rs_rssi_ctl0;
137 int8_t rs_rssi_ctl1;
138 int8_t rs_rssi_ctl2;
139 int8_t rs_rssi_ext0;
140 int8_t rs_rssi_ext1;
141 int8_t rs_rssi_ext2;
142 u8 rs_isaggr;
143 u8 rs_moreaggr;
144 u8 rs_num_delims;
145 u8 rs_flags;
146 bool is_mybeacon;
147 u32 evm0;
148 u32 evm1;
149 u32 evm2;
150 u32 evm3;
151 u32 evm4;
152};
153
154struct ath_htc_rx_status {
155 __be64 rs_tstamp;
156 __be16 rs_datalen;
157 u8 rs_status;
158 u8 rs_phyerr;
159 int8_t rs_rssi;
160 int8_t rs_rssi_ctl0;
161 int8_t rs_rssi_ctl1;
162 int8_t rs_rssi_ctl2;
163 int8_t rs_rssi_ext0;
164 int8_t rs_rssi_ext1;
165 int8_t rs_rssi_ext2;
166 u8 rs_keyix;
167 u8 rs_rate;
168 u8 rs_antenna;
169 u8 rs_more;
170 u8 rs_isaggr;
171 u8 rs_moreaggr;
172 u8 rs_num_delims;
173 u8 rs_flags;
174 u8 rs_dummy;
175 __be32 evm0;
176 __be32 evm1;
177 __be32 evm2;
178};
179
180#define ATH9K_RXERR_CRC 0x01
181#define ATH9K_RXERR_PHY 0x02
182#define ATH9K_RXERR_FIFO 0x04
183#define ATH9K_RXERR_DECRYPT 0x08
184#define ATH9K_RXERR_MIC 0x10
185#define ATH9K_RXERR_KEYMISS 0x20
186
187#define ATH9K_RX_MORE 0x01
188#define ATH9K_RX_MORE_AGGR 0x02
189#define ATH9K_RX_GI 0x04
190#define ATH9K_RX_2040 0x08
191#define ATH9K_RX_DELIM_CRC_PRE 0x10
192#define ATH9K_RX_DELIM_CRC_POST 0x20
193#define ATH9K_RX_DECRYPT_BUSY 0x40
194
195#define ATH9K_RXKEYIX_INVALID ((u8)-1)
196#define ATH9K_TXKEYIX_INVALID ((u8)-1)
197
198enum ath9k_phyerr {
199 ATH9K_PHYERR_UNDERRUN = 0,
200 ATH9K_PHYERR_TIMING = 1,
201 ATH9K_PHYERR_PARITY = 2,
202 ATH9K_PHYERR_RATE = 3,
203 ATH9K_PHYERR_LENGTH = 4,
204 ATH9K_PHYERR_RADAR = 5,
205 ATH9K_PHYERR_SERVICE = 6,
206 ATH9K_PHYERR_TOR = 7,
207
208 ATH9K_PHYERR_OFDM_TIMING = 17,
209 ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18,
210 ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19,
211 ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20,
212 ATH9K_PHYERR_OFDM_POWER_DROP = 21,
213 ATH9K_PHYERR_OFDM_SERVICE = 22,
214 ATH9K_PHYERR_OFDM_RESTART = 23,
215 ATH9K_PHYERR_FALSE_RADAR_EXT = 24,
216
217 ATH9K_PHYERR_CCK_TIMING = 25,
218 ATH9K_PHYERR_CCK_HEADER_CRC = 26,
219 ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27,
220 ATH9K_PHYERR_CCK_SERVICE = 30,
221 ATH9K_PHYERR_CCK_RESTART = 31,
222 ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 32,
223 ATH9K_PHYERR_CCK_POWER_DROP = 33,
224
225 ATH9K_PHYERR_HT_CRC_ERROR = 34,
226 ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 35,
227 ATH9K_PHYERR_HT_RATE_ILLEGAL = 36,
228
229 ATH9K_PHYERR_MAX = 37,
230};
231
232struct ath_desc {
233 u32 ds_link;
234 u32 ds_data;
235 u32 ds_ctl0;
236 u32 ds_ctl1;
237 u32 ds_hw[20];
238 void *ds_vdata;
239} __packed __aligned(4);
240
241#define ATH9K_TXDESC_NOACK 0x0002
242#define ATH9K_TXDESC_RTSENA 0x0004
243#define ATH9K_TXDESC_CTSENA 0x0008
244
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256
257#define ATH9K_TXDESC_INTREQ 0x0010
258#define ATH9K_TXDESC_VEOL 0x0020
259#define ATH9K_TXDESC_EXT_ONLY 0x0040
260#define ATH9K_TXDESC_EXT_AND_CTL 0x0080
261#define ATH9K_TXDESC_VMF 0x0100
262#define ATH9K_TXDESC_FRAG_IS_ON 0x0200
263#define ATH9K_TXDESC_LOWRXCHAIN 0x0400
264#define ATH9K_TXDESC_LDPC 0x0800
265#define ATH9K_TXDESC_CLRDMASK 0x1000
266
267#define ATH9K_TXDESC_PAPRD 0x70000
268#define ATH9K_TXDESC_PAPRD_S 16
269
270#define ATH9K_RXDESC_INTREQ 0x0020
271
272struct ar5416_desc {
273 u32 ds_link;
274 u32 ds_data;
275 u32 ds_ctl0;
276 u32 ds_ctl1;
277 union {
278 struct {
279 u32 ctl2;
280 u32 ctl3;
281 u32 ctl4;
282 u32 ctl5;
283 u32 ctl6;
284 u32 ctl7;
285 u32 ctl8;
286 u32 ctl9;
287 u32 ctl10;
288 u32 ctl11;
289 u32 status0;
290 u32 status1;
291 u32 status2;
292 u32 status3;
293 u32 status4;
294 u32 status5;
295 u32 status6;
296 u32 status7;
297 u32 status8;
298 u32 status9;
299 } tx;
300 struct {
301 u32 status0;
302 u32 status1;
303 u32 status2;
304 u32 status3;
305 u32 status4;
306 u32 status5;
307 u32 status6;
308 u32 status7;
309 u32 status8;
310 } rx;
311 } u;
312} __packed __aligned(4);
313
314#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
315#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
316
317#define ds_ctl2 u.tx.ctl2
318#define ds_ctl3 u.tx.ctl3
319#define ds_ctl4 u.tx.ctl4
320#define ds_ctl5 u.tx.ctl5
321#define ds_ctl6 u.tx.ctl6
322#define ds_ctl7 u.tx.ctl7
323#define ds_ctl8 u.tx.ctl8
324#define ds_ctl9 u.tx.ctl9
325#define ds_ctl10 u.tx.ctl10
326#define ds_ctl11 u.tx.ctl11
327
328#define ds_txstatus0 u.tx.status0
329#define ds_txstatus1 u.tx.status1
330#define ds_txstatus2 u.tx.status2
331#define ds_txstatus3 u.tx.status3
332#define ds_txstatus4 u.tx.status4
333#define ds_txstatus5 u.tx.status5
334#define ds_txstatus6 u.tx.status6
335#define ds_txstatus7 u.tx.status7
336#define ds_txstatus8 u.tx.status8
337#define ds_txstatus9 u.tx.status9
338
339#define ds_rxstatus0 u.rx.status0
340#define ds_rxstatus1 u.rx.status1
341#define ds_rxstatus2 u.rx.status2
342#define ds_rxstatus3 u.rx.status3
343#define ds_rxstatus4 u.rx.status4
344#define ds_rxstatus5 u.rx.status5
345#define ds_rxstatus6 u.rx.status6
346#define ds_rxstatus7 u.rx.status7
347#define ds_rxstatus8 u.rx.status8
348
349#define AR_FrameLen 0x00000fff
350#define AR_VirtMoreFrag 0x00001000
351#define AR_TxCtlRsvd00 0x0000e000
352#define AR_XmitPower 0x003f0000
353#define AR_XmitPower_S 16
354#define AR_RTSEnable 0x00400000
355#define AR_VEOL 0x00800000
356#define AR_ClrDestMask 0x01000000
357#define AR_TxCtlRsvd01 0x1e000000
358#define AR_TxIntrReq 0x20000000
359#define AR_DestIdxValid 0x40000000
360#define AR_CTSEnable 0x80000000
361
362#define AR_TxMore 0x00001000
363#define AR_DestIdx 0x000fe000
364#define AR_DestIdx_S 13
365#define AR_FrameType 0x00f00000
366#define AR_FrameType_S 20
367#define AR_NoAck 0x01000000
368#define AR_InsertTS 0x02000000
369#define AR_CorruptFCS 0x04000000
370#define AR_ExtOnly 0x08000000
371#define AR_ExtAndCtl 0x10000000
372#define AR_MoreAggr 0x20000000
373#define AR_IsAggr 0x40000000
374
375#define AR_BurstDur 0x00007fff
376#define AR_BurstDur_S 0
377#define AR_DurUpdateEna 0x00008000
378#define AR_XmitDataTries0 0x000f0000
379#define AR_XmitDataTries0_S 16
380#define AR_XmitDataTries1 0x00f00000
381#define AR_XmitDataTries1_S 20
382#define AR_XmitDataTries2 0x0f000000
383#define AR_XmitDataTries2_S 24
384#define AR_XmitDataTries3 0xf0000000
385#define AR_XmitDataTries3_S 28
386
387#define AR_XmitRate0 0x000000ff
388#define AR_XmitRate0_S 0
389#define AR_XmitRate1 0x0000ff00
390#define AR_XmitRate1_S 8
391#define AR_XmitRate2 0x00ff0000
392#define AR_XmitRate2_S 16
393#define AR_XmitRate3 0xff000000
394#define AR_XmitRate3_S 24
395
396#define AR_PacketDur0 0x00007fff
397#define AR_PacketDur0_S 0
398#define AR_RTSCTSQual0 0x00008000
399#define AR_PacketDur1 0x7fff0000
400#define AR_PacketDur1_S 16
401#define AR_RTSCTSQual1 0x80000000
402
403#define AR_PacketDur2 0x00007fff
404#define AR_PacketDur2_S 0
405#define AR_RTSCTSQual2 0x00008000
406#define AR_PacketDur3 0x7fff0000
407#define AR_PacketDur3_S 16
408#define AR_RTSCTSQual3 0x80000000
409
410#define AR_AggrLen 0x0000ffff
411#define AR_AggrLen_S 0
412#define AR_TxCtlRsvd60 0x00030000
413#define AR_PadDelim 0x03fc0000
414#define AR_PadDelim_S 18
415#define AR_EncrType 0x0c000000
416#define AR_EncrType_S 26
417#define AR_TxCtlRsvd61 0xf0000000
418#define AR_LDPC 0x80000000
419
420#define AR_2040_0 0x00000001
421#define AR_GI0 0x00000002
422#define AR_ChainSel0 0x0000001c
423#define AR_ChainSel0_S 2
424#define AR_2040_1 0x00000020
425#define AR_GI1 0x00000040
426#define AR_ChainSel1 0x00000380
427#define AR_ChainSel1_S 7
428#define AR_2040_2 0x00000400
429#define AR_GI2 0x00000800
430#define AR_ChainSel2 0x00007000
431#define AR_ChainSel2_S 12
432#define AR_2040_3 0x00008000
433#define AR_GI3 0x00010000
434#define AR_ChainSel3 0x000e0000
435#define AR_ChainSel3_S 17
436#define AR_RTSCTSRate 0x0ff00000
437#define AR_RTSCTSRate_S 20
438#define AR_STBC0 0x10000000
439#define AR_STBC1 0x20000000
440#define AR_STBC2 0x40000000
441#define AR_STBC3 0x80000000
442
443#define AR_TxRSSIAnt00 0x000000ff
444#define AR_TxRSSIAnt00_S 0
445#define AR_TxRSSIAnt01 0x0000ff00
446#define AR_TxRSSIAnt01_S 8
447#define AR_TxRSSIAnt02 0x00ff0000
448#define AR_TxRSSIAnt02_S 16
449#define AR_TxStatusRsvd00 0x3f000000
450#define AR_TxBaStatus 0x40000000
451#define AR_TxStatusRsvd01 0x80000000
452
453
454
455
456
457
458#define AR_FrmXmitOK 0x00000001
459#define AR_ExcessiveRetries 0x00000002
460#define AR_FIFOUnderrun 0x00000004
461#define AR_Filtered 0x00000008
462#define AR_RTSFailCnt 0x000000f0
463#define AR_RTSFailCnt_S 4
464#define AR_DataFailCnt 0x00000f00
465#define AR_DataFailCnt_S 8
466#define AR_VirtRetryCnt 0x0000f000
467#define AR_VirtRetryCnt_S 12
468#define AR_TxDelimUnderrun 0x00010000
469#define AR_TxDataUnderrun 0x00020000
470#define AR_DescCfgErr 0x00040000
471#define AR_TxTimerExpired 0x00080000
472#define AR_TxStatusRsvd10 0xfff00000
473
474#define AR_SendTimestamp ds_txstatus2
475#define AR_BaBitmapLow ds_txstatus3
476#define AR_BaBitmapHigh ds_txstatus4
477
478#define AR_TxRSSIAnt10 0x000000ff
479#define AR_TxRSSIAnt10_S 0
480#define AR_TxRSSIAnt11 0x0000ff00
481#define AR_TxRSSIAnt11_S 8
482#define AR_TxRSSIAnt12 0x00ff0000
483#define AR_TxRSSIAnt12_S 16
484#define AR_TxRSSICombined 0xff000000
485#define AR_TxRSSICombined_S 24
486
487#define AR_TxTid 0xf0000000
488#define AR_TxTid_S 28
489
490#define AR_TxEVM0 ds_txstatus5
491#define AR_TxEVM1 ds_txstatus6
492#define AR_TxEVM2 ds_txstatus7
493
494#define AR_TxDone 0x00000001
495#define AR_SeqNum 0x00001ffe
496#define AR_SeqNum_S 1
497#define AR_TxStatusRsvd80 0x0001e000
498#define AR_TxOpExceeded 0x00020000
499#define AR_TxStatusRsvd81 0x001c0000
500#define AR_FinalTxIdx 0x00600000
501#define AR_FinalTxIdx_S 21
502#define AR_TxStatusRsvd82 0x01800000
503#define AR_PowerMgmt 0x02000000
504#define AR_TxStatusRsvd83 0xfc000000
505
506#define AR_RxCTLRsvd00 0xffffffff
507
508#define AR_RxCtlRsvd00 0x00001000
509#define AR_RxIntrReq 0x00002000
510#define AR_RxCtlRsvd01 0xffffc000
511
512#define AR_RxRSSIAnt00 0x000000ff
513#define AR_RxRSSIAnt00_S 0
514#define AR_RxRSSIAnt01 0x0000ff00
515#define AR_RxRSSIAnt01_S 8
516#define AR_RxRSSIAnt02 0x00ff0000
517#define AR_RxRSSIAnt02_S 16
518#define AR_RxRate 0xff000000
519#define AR_RxRate_S 24
520#define AR_RxStatusRsvd00 0xff000000
521
522#define AR_DataLen 0x00000fff
523#define AR_RxMore 0x00001000
524#define AR_NumDelim 0x003fc000
525#define AR_NumDelim_S 14
526#define AR_RxStatusRsvd10 0xff800000
527
528#define AR_RcvTimestamp ds_rxstatus2
529
530#define AR_GI 0x00000001
531#define AR_2040 0x00000002
532#define AR_Parallel40 0x00000004
533#define AR_Parallel40_S 2
534#define AR_RxStatusRsvd30 0x000000f8
535#define AR_RxAntenna 0xffffff00
536#define AR_RxAntenna_S 8
537
538#define AR_RxRSSIAnt10 0x000000ff
539#define AR_RxRSSIAnt10_S 0
540#define AR_RxRSSIAnt11 0x0000ff00
541#define AR_RxRSSIAnt11_S 8
542#define AR_RxRSSIAnt12 0x00ff0000
543#define AR_RxRSSIAnt12_S 16
544#define AR_RxRSSICombined 0xff000000
545#define AR_RxRSSICombined_S 24
546
547#define AR_RxEVM0 ds_rxstatus4
548#define AR_RxEVM1 ds_rxstatus5
549#define AR_RxEVM2 ds_rxstatus6
550
551#define AR_RxDone 0x00000001
552#define AR_RxFrameOK 0x00000002
553#define AR_CRCErr 0x00000004
554#define AR_DecryptCRCErr 0x00000008
555#define AR_PHYErr 0x00000010
556#define AR_MichaelErr 0x00000020
557#define AR_PreDelimCRCErr 0x00000040
558#define AR_RxStatusRsvd70 0x00000080
559#define AR_RxKeyIdxValid 0x00000100
560#define AR_KeyIdx 0x0000fe00
561#define AR_KeyIdx_S 9
562#define AR_PHYErrCode 0x0000ff00
563#define AR_PHYErrCode_S 8
564#define AR_RxMoreAggr 0x00010000
565#define AR_RxAggr 0x00020000
566#define AR_PostDelimCRCErr 0x00040000
567#define AR_RxStatusRsvd71 0x3ff80000
568#define AR_DecryptBusyErr 0x40000000
569#define AR_KeyMiss 0x80000000
570
571enum ath9k_tx_queue {
572 ATH9K_TX_QUEUE_INACTIVE = 0,
573 ATH9K_TX_QUEUE_DATA,
574 ATH9K_TX_QUEUE_BEACON,
575 ATH9K_TX_QUEUE_CAB,
576 ATH9K_TX_QUEUE_UAPSD,
577 ATH9K_TX_QUEUE_PSPOLL
578};
579
580#define ATH9K_NUM_TX_QUEUES 10
581
582
583#define ATH9K_WME_UPSD 4
584
585enum ath9k_tx_queue_flags {
586 TXQ_FLAG_TXINT_ENABLE = 0x0001,
587 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
588 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
589 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
590 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
591 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
592 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
593 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
594};
595
596#define ATH9K_TXQ_USEDEFAULT ((u32) -1)
597#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
598
599#define ATH9K_DECOMP_MASK_SIZE 128
600#define ATH9K_READY_TIME_LO_BOUND 50
601#define ATH9K_READY_TIME_HI_BOUND 96
602
603enum ath9k_pkt_type {
604 ATH9K_PKT_TYPE_NORMAL = 0,
605 ATH9K_PKT_TYPE_ATIM,
606 ATH9K_PKT_TYPE_PSPOLL,
607 ATH9K_PKT_TYPE_BEACON,
608 ATH9K_PKT_TYPE_PROBE_RESP,
609 ATH9K_PKT_TYPE_CHIRP,
610 ATH9K_PKT_TYPE_GRP_POLL,
611};
612
613struct ath9k_tx_queue_info {
614 u32 tqi_ver;
615 enum ath9k_tx_queue tqi_type;
616 int tqi_subtype;
617 enum ath9k_tx_queue_flags tqi_qflags;
618 u32 tqi_priority;
619 u32 tqi_aifs;
620 u32 tqi_cwmin;
621 u32 tqi_cwmax;
622 u16 tqi_shretry;
623 u16 tqi_lgretry;
624 u32 tqi_cbrPeriod;
625 u32 tqi_cbrOverflowLimit;
626 u32 tqi_burstTime;
627 u32 tqi_readyTime;
628 u32 tqi_physCompBuf;
629 u32 tqi_intFlags;
630};
631
632enum ath9k_rx_filter {
633 ATH9K_RX_FILTER_UCAST = 0x00000001,
634 ATH9K_RX_FILTER_MCAST = 0x00000002,
635 ATH9K_RX_FILTER_BCAST = 0x00000004,
636 ATH9K_RX_FILTER_CONTROL = 0x00000008,
637 ATH9K_RX_FILTER_BEACON = 0x00000010,
638 ATH9K_RX_FILTER_PROM = 0x00000020,
639 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
640 ATH9K_RX_FILTER_PHYERR = 0x00000100,
641 ATH9K_RX_FILTER_MYBEACON = 0x00000200,
642 ATH9K_RX_FILTER_COMP_BAR = 0x00000400,
643 ATH9K_RX_FILTER_COMP_BA = 0x00000800,
644 ATH9K_RX_FILTER_UNCOMP_BA_BAR = 0x00001000,
645 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
646 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
647 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
648 ATH9K_RX_FILTER_CONTROL_WRAPPER = 0x00080000,
649 ATH9K_RX_FILTER_4ADDRESS = 0x00100000,
650};
651
652#define ATH9K_RATESERIES_RTS_CTS 0x0001
653#define ATH9K_RATESERIES_2040 0x0002
654#define ATH9K_RATESERIES_HALFGI 0x0004
655#define ATH9K_RATESERIES_STBC 0x0008
656
657struct ath9k_11n_rate_series {
658 u32 Tries;
659 u32 Rate;
660 u32 PktDuration;
661 u32 ChSel;
662 u32 RateFlags;
663};
664
665enum aggr_type {
666 AGGR_BUF_NONE,
667 AGGR_BUF_FIRST,
668 AGGR_BUF_MIDDLE,
669 AGGR_BUF_LAST,
670};
671
672enum ath9k_key_type {
673 ATH9K_KEY_TYPE_CLEAR,
674 ATH9K_KEY_TYPE_WEP,
675 ATH9K_KEY_TYPE_AES,
676 ATH9K_KEY_TYPE_TKIP,
677};
678
679struct ath_tx_info {
680 u8 qcu;
681
682 bool is_first;
683 bool is_last;
684
685 enum aggr_type aggr;
686 u8 ndelim;
687 u16 aggr_len;
688
689 dma_addr_t link;
690 int pkt_len;
691 u32 flags;
692
693 dma_addr_t buf_addr[4];
694 int buf_len[4];
695
696 struct ath9k_11n_rate_series rates[4];
697 u8 rtscts_rate;
698 bool dur_update;
699
700 enum ath9k_pkt_type type;
701 enum ath9k_key_type keytype;
702 u8 keyix;
703 u8 txpower;
704};
705
706struct ath_hw;
707struct ath9k_channel;
708enum ath9k_int;
709
710u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
711void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
712void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
713u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
714bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
715bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);
716void ath9k_hw_abort_tx_dma(struct ath_hw *ah);
717bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
718 const struct ath9k_tx_queue_info *qinfo);
719bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
720 struct ath9k_tx_queue_info *qinfo);
721int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
722 const struct ath9k_tx_queue_info *qinfo);
723bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q);
724bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q);
725int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
726 struct ath_rx_status *rs);
727void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
728 u32 size, u32 flags);
729bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
730void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
731void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning);
732void ath9k_hw_abortpcurecv(struct ath_hw *ah);
733bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset);
734int ath9k_hw_beaconq_setup(struct ath_hw *ah);
735
736
737bool ath9k_hw_intrpend(struct ath_hw *ah);
738void ath9k_hw_set_interrupts(struct ath_hw *ah);
739void ath9k_hw_enable_interrupts(struct ath_hw *ah);
740void ath9k_hw_disable_interrupts(struct ath_hw *ah);
741void ath9k_hw_kill_interrupts(struct ath_hw *ah);
742
743void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
744
745#endif
746