1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
28#include <linux/ioport.h>
29#include <linux/errno.h>
30#include <linux/interrupt.h>
31#include <linux/spi/spi.h>
32#include <linux/delay.h>
33#include <linux/clk.h>
34#include <linux/err.h>
35#include <linux/amba/bus.h>
36#include <linux/amba/pl022.h>
37#include <linux/io.h>
38#include <linux/slab.h>
39#include <linux/dmaengine.h>
40#include <linux/dma-mapping.h>
41#include <linux/scatterlist.h>
42#include <linux/pm_runtime.h>
43#include <linux/gpio.h>
44#include <linux/of_gpio.h>
45#include <linux/pinctrl/consumer.h>
46
47
48
49
50
51
52#define SSP_WRITE_BITS(reg, val, mask, sb) \
53 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
54
55
56
57
58
59
60#define GEN_MASK_BITS(val, mask, sb) \
61 (((val)<<(sb)) & (mask))
62
63#define DRIVE_TX 0
64#define DO_NOT_DRIVE_TX 1
65
66#define DO_NOT_QUEUE_DMA 0
67#define QUEUE_DMA 1
68
69#define RX_TRANSFER 1
70#define TX_TRANSFER 2
71
72
73
74
75#define SSP_CR0(r) (r + 0x000)
76#define SSP_CR1(r) (r + 0x004)
77#define SSP_DR(r) (r + 0x008)
78#define SSP_SR(r) (r + 0x00C)
79#define SSP_CPSR(r) (r + 0x010)
80#define SSP_IMSC(r) (r + 0x014)
81#define SSP_RIS(r) (r + 0x018)
82#define SSP_MIS(r) (r + 0x01C)
83#define SSP_ICR(r) (r + 0x020)
84#define SSP_DMACR(r) (r + 0x024)
85#define SSP_ITCR(r) (r + 0x080)
86#define SSP_ITIP(r) (r + 0x084)
87#define SSP_ITOP(r) (r + 0x088)
88#define SSP_TDR(r) (r + 0x08C)
89
90#define SSP_PID0(r) (r + 0xFE0)
91#define SSP_PID1(r) (r + 0xFE4)
92#define SSP_PID2(r) (r + 0xFE8)
93#define SSP_PID3(r) (r + 0xFEC)
94
95#define SSP_CID0(r) (r + 0xFF0)
96#define SSP_CID1(r) (r + 0xFF4)
97#define SSP_CID2(r) (r + 0xFF8)
98#define SSP_CID3(r) (r + 0xFFC)
99
100
101
102
103#define SSP_CR0_MASK_DSS (0x0FUL << 0)
104#define SSP_CR0_MASK_FRF (0x3UL << 4)
105#define SSP_CR0_MASK_SPO (0x1UL << 6)
106#define SSP_CR0_MASK_SPH (0x1UL << 7)
107#define SSP_CR0_MASK_SCR (0xFFUL << 8)
108
109
110
111
112
113#define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
114#define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
115#define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
116#define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
117
118
119
120
121#define SSP_CR1_MASK_LBM (0x1UL << 0)
122#define SSP_CR1_MASK_SSE (0x1UL << 1)
123#define SSP_CR1_MASK_MS (0x1UL << 2)
124#define SSP_CR1_MASK_SOD (0x1UL << 3)
125
126
127
128
129
130#define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
131#define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
132#define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
133#define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
134#define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
135
136#define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
137
138
139
140
141#define SSP_SR_MASK_TFE (0x1UL << 0)
142#define SSP_SR_MASK_TNF (0x1UL << 1)
143#define SSP_SR_MASK_RNE (0x1UL << 2)
144#define SSP_SR_MASK_RFF (0x1UL << 3)
145#define SSP_SR_MASK_BSY (0x1UL << 4)
146
147
148
149
150#define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
151
152
153
154
155#define SSP_IMSC_MASK_RORIM (0x1UL << 0)
156#define SSP_IMSC_MASK_RTIM (0x1UL << 1)
157#define SSP_IMSC_MASK_RXIM (0x1UL << 2)
158#define SSP_IMSC_MASK_TXIM (0x1UL << 3)
159
160
161
162
163
164#define SSP_RIS_MASK_RORRIS (0x1UL << 0)
165
166#define SSP_RIS_MASK_RTRIS (0x1UL << 1)
167
168#define SSP_RIS_MASK_RXRIS (0x1UL << 2)
169
170#define SSP_RIS_MASK_TXRIS (0x1UL << 3)
171
172
173
174
175
176#define SSP_MIS_MASK_RORMIS (0x1UL << 0)
177
178#define SSP_MIS_MASK_RTMIS (0x1UL << 1)
179
180#define SSP_MIS_MASK_RXMIS (0x1UL << 2)
181
182#define SSP_MIS_MASK_TXMIS (0x1UL << 3)
183
184
185
186
187
188#define SSP_ICR_MASK_RORIC (0x1UL << 0)
189
190#define SSP_ICR_MASK_RTIC (0x1UL << 1)
191
192
193
194
195
196#define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
197
198#define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
199
200
201
202
203#define SSP_ITCR_MASK_ITEN (0x1UL << 0)
204#define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
205
206
207
208
209#define ITIP_MASK_SSPRXD (0x1UL << 0)
210#define ITIP_MASK_SSPFSSIN (0x1UL << 1)
211#define ITIP_MASK_SSPCLKIN (0x1UL << 2)
212#define ITIP_MASK_RXDMAC (0x1UL << 3)
213#define ITIP_MASK_TXDMAC (0x1UL << 4)
214#define ITIP_MASK_SSPTXDIN (0x1UL << 5)
215
216
217
218
219#define ITOP_MASK_SSPTXD (0x1UL << 0)
220#define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
221#define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
222#define ITOP_MASK_SSPOEn (0x1UL << 3)
223#define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
224#define ITOP_MASK_RORINTR (0x1UL << 5)
225#define ITOP_MASK_RTINTR (0x1UL << 6)
226#define ITOP_MASK_RXINTR (0x1UL << 7)
227#define ITOP_MASK_TXINTR (0x1UL << 8)
228#define ITOP_MASK_INTR (0x1UL << 9)
229#define ITOP_MASK_RXDMABREQ (0x1UL << 10)
230#define ITOP_MASK_RXDMASREQ (0x1UL << 11)
231#define ITOP_MASK_TXDMABREQ (0x1UL << 12)
232#define ITOP_MASK_TXDMASREQ (0x1UL << 13)
233
234
235
236
237#define TDR_MASK_TESTDATA (0xFFFFFFFF)
238
239
240
241
242
243
244
245#define STATE_START ((void *) 0)
246#define STATE_RUNNING ((void *) 1)
247#define STATE_DONE ((void *) 2)
248#define STATE_ERROR ((void *) -1)
249
250
251
252
253#define SSP_DISABLED (0)
254#define SSP_ENABLED (1)
255
256
257
258
259#define SSP_DMA_DISABLED (0)
260#define SSP_DMA_ENABLED (1)
261
262
263
264
265#define SSP_DEFAULT_CLKRATE 0x2
266#define SSP_DEFAULT_PRESCALE 0x40
267
268
269
270
271#define CPSDVR_MIN 0x02
272#define CPSDVR_MAX 0xFE
273#define SCR_MIN 0x00
274#define SCR_MAX 0xFF
275
276
277
278
279#define DEFAULT_SSP_REG_IMSC 0x0UL
280#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
281#define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
282
283#define CLEAR_ALL_INTERRUPTS 0x3
284
285#define SPI_POLLING_TIMEOUT 1000
286
287
288
289
290enum ssp_reading {
291 READING_NULL,
292 READING_U8,
293 READING_U16,
294 READING_U32
295};
296
297
298
299
300enum ssp_writing {
301 WRITING_NULL,
302 WRITING_U8,
303 WRITING_U16,
304 WRITING_U32
305};
306
307
308
309
310
311
312
313
314
315
316
317struct vendor_data {
318 int fifodepth;
319 int max_bpw;
320 bool unidir;
321 bool extended_cr;
322 bool pl023;
323 bool loopback;
324};
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365struct pl022 {
366 struct amba_device *adev;
367 struct vendor_data *vendor;
368 resource_size_t phybase;
369 void __iomem *virtbase;
370 struct clk *clk;
371
372 struct pinctrl *pinctrl;
373 struct pinctrl_state *pins_default;
374 struct pinctrl_state *pins_sleep;
375 struct spi_master *master;
376 struct pl022_ssp_controller *master_info;
377
378 struct tasklet_struct pump_transfers;
379 struct spi_message *cur_msg;
380 struct spi_transfer *cur_transfer;
381 struct chip_data *cur_chip;
382 bool next_msg_cs_active;
383 void *tx;
384 void *tx_end;
385 void *rx;
386 void *rx_end;
387 enum ssp_reading read;
388 enum ssp_writing write;
389 u32 exp_fifo_level;
390 enum ssp_rx_level_trig rx_lev_trig;
391 enum ssp_tx_level_trig tx_lev_trig;
392
393#ifdef CONFIG_DMA_ENGINE
394 struct dma_chan *dma_rx_channel;
395 struct dma_chan *dma_tx_channel;
396 struct sg_table sgt_rx;
397 struct sg_table sgt_tx;
398 char *dummypage;
399 bool dma_running;
400#endif
401 int cur_cs;
402 int *chipselects;
403};
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422struct chip_data {
423 u32 cr0;
424 u16 cr1;
425 u16 dmacr;
426 u16 cpsr;
427 u8 n_bytes;
428 bool enable_dma;
429 enum ssp_reading read;
430 enum ssp_writing write;
431 void (*cs_control) (u32 command);
432 int xfer_type;
433};
434
435
436
437
438
439
440
441
442static void null_cs_control(u32 command)
443{
444 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
445}
446
447static void pl022_cs_control(struct pl022 *pl022, u32 command)
448{
449 if (gpio_is_valid(pl022->cur_cs))
450 gpio_set_value(pl022->cur_cs, command);
451 else
452 pl022->cur_chip->cs_control(command);
453}
454
455
456
457
458
459
460
461static void giveback(struct pl022 *pl022)
462{
463 struct spi_transfer *last_transfer;
464 pl022->next_msg_cs_active = false;
465
466 last_transfer = list_entry(pl022->cur_msg->transfers.prev,
467 struct spi_transfer,
468 transfer_list);
469
470
471 if (last_transfer->delay_usecs)
472
473
474
475
476 udelay(last_transfer->delay_usecs);
477
478 if (!last_transfer->cs_change) {
479 struct spi_message *next_msg;
480
481
482
483
484
485
486
487
488
489
490
491
492 next_msg = spi_get_next_queued_message(pl022->master);
493
494
495
496
497
498 if (next_msg && next_msg->spi != pl022->cur_msg->spi)
499 next_msg = NULL;
500 if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
501 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
502 else
503 pl022->next_msg_cs_active = true;
504
505 }
506
507 pl022->cur_msg = NULL;
508 pl022->cur_transfer = NULL;
509 pl022->cur_chip = NULL;
510 spi_finalize_current_message(pl022->master);
511
512
513 writew((readw(SSP_CR1(pl022->virtbase)) &
514 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
515
516}
517
518
519
520
521
522static int flush(struct pl022 *pl022)
523{
524 unsigned long limit = loops_per_jiffy << 1;
525
526 dev_dbg(&pl022->adev->dev, "flush\n");
527 do {
528 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
529 readw(SSP_DR(pl022->virtbase));
530 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
531
532 pl022->exp_fifo_level = 0;
533
534 return limit;
535}
536
537
538
539
540
541static void restore_state(struct pl022 *pl022)
542{
543 struct chip_data *chip = pl022->cur_chip;
544
545 if (pl022->vendor->extended_cr)
546 writel(chip->cr0, SSP_CR0(pl022->virtbase));
547 else
548 writew(chip->cr0, SSP_CR0(pl022->virtbase));
549 writew(chip->cr1, SSP_CR1(pl022->virtbase));
550 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
551 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
552 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
553 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
554}
555
556
557
558
559#define DEFAULT_SSP_REG_CR0 ( \
560 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
561 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
562 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
563 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
564 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
565)
566
567
568#define DEFAULT_SSP_REG_CR0_ST ( \
569 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
570 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
571 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
572 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
573 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
574 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
575 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
576)
577
578
579#define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
580 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
581 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
582 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
583 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
584)
585
586#define DEFAULT_SSP_REG_CR1 ( \
587 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
588 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
589 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
590 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
591)
592
593
594#define DEFAULT_SSP_REG_CR1_ST ( \
595 DEFAULT_SSP_REG_CR1 | \
596 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
597 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
598 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
599 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
600 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
601)
602
603
604
605
606
607#define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
608 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
609 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
610 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
611 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
612 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
613 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
614 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
615 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
616)
617
618#define DEFAULT_SSP_REG_CPSR ( \
619 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
620)
621
622#define DEFAULT_SSP_REG_DMACR (\
623 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
624 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
625)
626
627
628
629
630
631static void load_ssp_default_config(struct pl022 *pl022)
632{
633 if (pl022->vendor->pl023) {
634 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
635 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
636 } else if (pl022->vendor->extended_cr) {
637 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
638 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
639 } else {
640 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
641 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
642 }
643 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
644 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
645 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
646 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
647}
648
649
650
651
652
653static void readwriter(struct pl022 *pl022)
654{
655
656
657
658
659
660
661
662
663
664
665
666 dev_dbg(&pl022->adev->dev,
667 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
668 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
669
670
671 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
672 && (pl022->rx < pl022->rx_end)) {
673 switch (pl022->read) {
674 case READING_NULL:
675 readw(SSP_DR(pl022->virtbase));
676 break;
677 case READING_U8:
678 *(u8 *) (pl022->rx) =
679 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
680 break;
681 case READING_U16:
682 *(u16 *) (pl022->rx) =
683 (u16) readw(SSP_DR(pl022->virtbase));
684 break;
685 case READING_U32:
686 *(u32 *) (pl022->rx) =
687 readl(SSP_DR(pl022->virtbase));
688 break;
689 }
690 pl022->rx += (pl022->cur_chip->n_bytes);
691 pl022->exp_fifo_level--;
692 }
693
694
695
696 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
697 && (pl022->tx < pl022->tx_end)) {
698 switch (pl022->write) {
699 case WRITING_NULL:
700 writew(0x0, SSP_DR(pl022->virtbase));
701 break;
702 case WRITING_U8:
703 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
704 break;
705 case WRITING_U16:
706 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
707 break;
708 case WRITING_U32:
709 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
710 break;
711 }
712 pl022->tx += (pl022->cur_chip->n_bytes);
713 pl022->exp_fifo_level++;
714
715
716
717
718
719
720 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
721 && (pl022->rx < pl022->rx_end)) {
722 switch (pl022->read) {
723 case READING_NULL:
724 readw(SSP_DR(pl022->virtbase));
725 break;
726 case READING_U8:
727 *(u8 *) (pl022->rx) =
728 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
729 break;
730 case READING_U16:
731 *(u16 *) (pl022->rx) =
732 (u16) readw(SSP_DR(pl022->virtbase));
733 break;
734 case READING_U32:
735 *(u32 *) (pl022->rx) =
736 readl(SSP_DR(pl022->virtbase));
737 break;
738 }
739 pl022->rx += (pl022->cur_chip->n_bytes);
740 pl022->exp_fifo_level--;
741 }
742 }
743
744
745
746
747}
748
749
750
751
752
753
754
755
756
757
758static void *next_transfer(struct pl022 *pl022)
759{
760 struct spi_message *msg = pl022->cur_msg;
761 struct spi_transfer *trans = pl022->cur_transfer;
762
763
764 if (trans->transfer_list.next != &msg->transfers) {
765 pl022->cur_transfer =
766 list_entry(trans->transfer_list.next,
767 struct spi_transfer, transfer_list);
768 return STATE_RUNNING;
769 }
770 return STATE_DONE;
771}
772
773
774
775
776
777#ifdef CONFIG_DMA_ENGINE
778static void unmap_free_dma_scatter(struct pl022 *pl022)
779{
780
781 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
782 pl022->sgt_tx.nents, DMA_TO_DEVICE);
783 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
784 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
785 sg_free_table(&pl022->sgt_rx);
786 sg_free_table(&pl022->sgt_tx);
787}
788
789static void dma_callback(void *data)
790{
791 struct pl022 *pl022 = data;
792 struct spi_message *msg = pl022->cur_msg;
793
794 BUG_ON(!pl022->sgt_rx.sgl);
795
796#ifdef VERBOSE_DEBUG
797
798
799
800
801
802
803 {
804 struct scatterlist *sg;
805 unsigned int i;
806
807 dma_sync_sg_for_cpu(&pl022->adev->dev,
808 pl022->sgt_rx.sgl,
809 pl022->sgt_rx.nents,
810 DMA_FROM_DEVICE);
811
812 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
813 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
814 print_hex_dump(KERN_ERR, "SPI RX: ",
815 DUMP_PREFIX_OFFSET,
816 16,
817 1,
818 sg_virt(sg),
819 sg_dma_len(sg),
820 1);
821 }
822 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
823 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
824 print_hex_dump(KERN_ERR, "SPI TX: ",
825 DUMP_PREFIX_OFFSET,
826 16,
827 1,
828 sg_virt(sg),
829 sg_dma_len(sg),
830 1);
831 }
832 }
833#endif
834
835 unmap_free_dma_scatter(pl022);
836
837
838 msg->actual_length += pl022->cur_transfer->len;
839 if (pl022->cur_transfer->cs_change)
840 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
841
842
843 msg->state = next_transfer(pl022);
844 tasklet_schedule(&pl022->pump_transfers);
845}
846
847static void setup_dma_scatter(struct pl022 *pl022,
848 void *buffer,
849 unsigned int length,
850 struct sg_table *sgtab)
851{
852 struct scatterlist *sg;
853 int bytesleft = length;
854 void *bufp = buffer;
855 int mapbytes;
856 int i;
857
858 if (buffer) {
859 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
860
861
862
863
864
865
866 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
867 mapbytes = bytesleft;
868 else
869 mapbytes = PAGE_SIZE - offset_in_page(bufp);
870 sg_set_page(sg, virt_to_page(bufp),
871 mapbytes, offset_in_page(bufp));
872 bufp += mapbytes;
873 bytesleft -= mapbytes;
874 dev_dbg(&pl022->adev->dev,
875 "set RX/TX target page @ %p, %d bytes, %d left\n",
876 bufp, mapbytes, bytesleft);
877 }
878 } else {
879
880 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
881 if (bytesleft < PAGE_SIZE)
882 mapbytes = bytesleft;
883 else
884 mapbytes = PAGE_SIZE;
885 sg_set_page(sg, virt_to_page(pl022->dummypage),
886 mapbytes, 0);
887 bytesleft -= mapbytes;
888 dev_dbg(&pl022->adev->dev,
889 "set RX/TX to dummy page %d bytes, %d left\n",
890 mapbytes, bytesleft);
891
892 }
893 }
894 BUG_ON(bytesleft);
895}
896
897
898
899
900
901static int configure_dma(struct pl022 *pl022)
902{
903 struct dma_slave_config rx_conf = {
904 .src_addr = SSP_DR(pl022->phybase),
905 .direction = DMA_DEV_TO_MEM,
906 .device_fc = false,
907 };
908 struct dma_slave_config tx_conf = {
909 .dst_addr = SSP_DR(pl022->phybase),
910 .direction = DMA_MEM_TO_DEV,
911 .device_fc = false,
912 };
913 unsigned int pages;
914 int ret;
915 int rx_sglen, tx_sglen;
916 struct dma_chan *rxchan = pl022->dma_rx_channel;
917 struct dma_chan *txchan = pl022->dma_tx_channel;
918 struct dma_async_tx_descriptor *rxdesc;
919 struct dma_async_tx_descriptor *txdesc;
920
921
922 if (!rxchan || !txchan)
923 return -ENODEV;
924
925
926
927
928
929
930
931 switch (pl022->rx_lev_trig) {
932 case SSP_RX_1_OR_MORE_ELEM:
933 rx_conf.src_maxburst = 1;
934 break;
935 case SSP_RX_4_OR_MORE_ELEM:
936 rx_conf.src_maxburst = 4;
937 break;
938 case SSP_RX_8_OR_MORE_ELEM:
939 rx_conf.src_maxburst = 8;
940 break;
941 case SSP_RX_16_OR_MORE_ELEM:
942 rx_conf.src_maxburst = 16;
943 break;
944 case SSP_RX_32_OR_MORE_ELEM:
945 rx_conf.src_maxburst = 32;
946 break;
947 default:
948 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
949 break;
950 }
951
952 switch (pl022->tx_lev_trig) {
953 case SSP_TX_1_OR_MORE_EMPTY_LOC:
954 tx_conf.dst_maxburst = 1;
955 break;
956 case SSP_TX_4_OR_MORE_EMPTY_LOC:
957 tx_conf.dst_maxburst = 4;
958 break;
959 case SSP_TX_8_OR_MORE_EMPTY_LOC:
960 tx_conf.dst_maxburst = 8;
961 break;
962 case SSP_TX_16_OR_MORE_EMPTY_LOC:
963 tx_conf.dst_maxburst = 16;
964 break;
965 case SSP_TX_32_OR_MORE_EMPTY_LOC:
966 tx_conf.dst_maxburst = 32;
967 break;
968 default:
969 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
970 break;
971 }
972
973 switch (pl022->read) {
974 case READING_NULL:
975
976 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
977 break;
978 case READING_U8:
979 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
980 break;
981 case READING_U16:
982 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
983 break;
984 case READING_U32:
985 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
986 break;
987 }
988
989 switch (pl022->write) {
990 case WRITING_NULL:
991
992 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
993 break;
994 case WRITING_U8:
995 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
996 break;
997 case WRITING_U16:
998 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
999 break;
1000 case WRITING_U32:
1001 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1002 break;
1003 }
1004
1005
1006 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1007 rx_conf.src_addr_width = tx_conf.dst_addr_width;
1008 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1009 tx_conf.dst_addr_width = rx_conf.src_addr_width;
1010 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
1011
1012 dmaengine_slave_config(rxchan, &rx_conf);
1013 dmaengine_slave_config(txchan, &tx_conf);
1014
1015
1016 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
1017 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1018
1019 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
1020 if (ret)
1021 goto err_alloc_rx_sg;
1022
1023 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
1024 if (ret)
1025 goto err_alloc_tx_sg;
1026
1027
1028 setup_dma_scatter(pl022, pl022->rx,
1029 pl022->cur_transfer->len, &pl022->sgt_rx);
1030 setup_dma_scatter(pl022, pl022->tx,
1031 pl022->cur_transfer->len, &pl022->sgt_tx);
1032
1033
1034 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1035 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1036 if (!rx_sglen)
1037 goto err_rx_sgmap;
1038
1039 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1040 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1041 if (!tx_sglen)
1042 goto err_tx_sgmap;
1043
1044
1045 rxdesc = dmaengine_prep_slave_sg(rxchan,
1046 pl022->sgt_rx.sgl,
1047 rx_sglen,
1048 DMA_DEV_TO_MEM,
1049 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1050 if (!rxdesc)
1051 goto err_rxdesc;
1052
1053 txdesc = dmaengine_prep_slave_sg(txchan,
1054 pl022->sgt_tx.sgl,
1055 tx_sglen,
1056 DMA_MEM_TO_DEV,
1057 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1058 if (!txdesc)
1059 goto err_txdesc;
1060
1061
1062 rxdesc->callback = dma_callback;
1063 rxdesc->callback_param = pl022;
1064
1065
1066 dmaengine_submit(rxdesc);
1067 dmaengine_submit(txdesc);
1068 dma_async_issue_pending(rxchan);
1069 dma_async_issue_pending(txchan);
1070 pl022->dma_running = true;
1071
1072 return 0;
1073
1074err_txdesc:
1075 dmaengine_terminate_all(txchan);
1076err_rxdesc:
1077 dmaengine_terminate_all(rxchan);
1078 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1079 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1080err_tx_sgmap:
1081 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1082 pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1083err_rx_sgmap:
1084 sg_free_table(&pl022->sgt_tx);
1085err_alloc_tx_sg:
1086 sg_free_table(&pl022->sgt_rx);
1087err_alloc_rx_sg:
1088 return -ENOMEM;
1089}
1090
1091static int __devinit pl022_dma_probe(struct pl022 *pl022)
1092{
1093 dma_cap_mask_t mask;
1094
1095
1096 dma_cap_zero(mask);
1097 dma_cap_set(DMA_SLAVE, mask);
1098
1099
1100
1101
1102 pl022->dma_rx_channel = dma_request_channel(mask,
1103 pl022->master_info->dma_filter,
1104 pl022->master_info->dma_rx_param);
1105 if (!pl022->dma_rx_channel) {
1106 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1107 goto err_no_rxchan;
1108 }
1109
1110 pl022->dma_tx_channel = dma_request_channel(mask,
1111 pl022->master_info->dma_filter,
1112 pl022->master_info->dma_tx_param);
1113 if (!pl022->dma_tx_channel) {
1114 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1115 goto err_no_txchan;
1116 }
1117
1118 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1119 if (!pl022->dummypage) {
1120 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
1121 goto err_no_dummypage;
1122 }
1123
1124 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1125 dma_chan_name(pl022->dma_rx_channel),
1126 dma_chan_name(pl022->dma_tx_channel));
1127
1128 return 0;
1129
1130err_no_dummypage:
1131 dma_release_channel(pl022->dma_tx_channel);
1132err_no_txchan:
1133 dma_release_channel(pl022->dma_rx_channel);
1134 pl022->dma_rx_channel = NULL;
1135err_no_rxchan:
1136 dev_err(&pl022->adev->dev,
1137 "Failed to work in dma mode, work without dma!\n");
1138 return -ENODEV;
1139}
1140
1141static void terminate_dma(struct pl022 *pl022)
1142{
1143 struct dma_chan *rxchan = pl022->dma_rx_channel;
1144 struct dma_chan *txchan = pl022->dma_tx_channel;
1145
1146 dmaengine_terminate_all(rxchan);
1147 dmaengine_terminate_all(txchan);
1148 unmap_free_dma_scatter(pl022);
1149 pl022->dma_running = false;
1150}
1151
1152static void pl022_dma_remove(struct pl022 *pl022)
1153{
1154 if (pl022->dma_running)
1155 terminate_dma(pl022);
1156 if (pl022->dma_tx_channel)
1157 dma_release_channel(pl022->dma_tx_channel);
1158 if (pl022->dma_rx_channel)
1159 dma_release_channel(pl022->dma_rx_channel);
1160 kfree(pl022->dummypage);
1161}
1162
1163#else
1164static inline int configure_dma(struct pl022 *pl022)
1165{
1166 return -ENODEV;
1167}
1168
1169static inline int pl022_dma_probe(struct pl022 *pl022)
1170{
1171 return 0;
1172}
1173
1174static inline void pl022_dma_remove(struct pl022 *pl022)
1175{
1176}
1177#endif
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1191{
1192 struct pl022 *pl022 = dev_id;
1193 struct spi_message *msg = pl022->cur_msg;
1194 u16 irq_status = 0;
1195 u16 flag = 0;
1196
1197 if (unlikely(!msg)) {
1198 dev_err(&pl022->adev->dev,
1199 "bad message state in interrupt handler");
1200
1201 return IRQ_HANDLED;
1202 }
1203
1204
1205 irq_status = readw(SSP_MIS(pl022->virtbase));
1206
1207 if (unlikely(!irq_status))
1208 return IRQ_NONE;
1209
1210
1211
1212
1213
1214
1215 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1216
1217
1218
1219
1220 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1221 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1222 dev_err(&pl022->adev->dev,
1223 "RXFIFO is full\n");
1224 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1225 dev_err(&pl022->adev->dev,
1226 "TXFIFO is full\n");
1227
1228
1229
1230
1231
1232
1233 writew(DISABLE_ALL_INTERRUPTS,
1234 SSP_IMSC(pl022->virtbase));
1235 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1236 writew((readw(SSP_CR1(pl022->virtbase)) &
1237 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1238 msg->state = STATE_ERROR;
1239
1240
1241 tasklet_schedule(&pl022->pump_transfers);
1242 return IRQ_HANDLED;
1243 }
1244
1245 readwriter(pl022);
1246
1247 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1248 flag = 1;
1249
1250 writew((readw(SSP_IMSC(pl022->virtbase)) &
1251 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
1252 SSP_IMSC(pl022->virtbase));
1253 }
1254
1255
1256
1257
1258
1259
1260 if (pl022->rx >= pl022->rx_end) {
1261 writew(DISABLE_ALL_INTERRUPTS,
1262 SSP_IMSC(pl022->virtbase));
1263 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1264 if (unlikely(pl022->rx > pl022->rx_end)) {
1265 dev_warn(&pl022->adev->dev, "read %u surplus "
1266 "bytes (did you request an odd "
1267 "number of bytes on a 16bit bus?)\n",
1268 (u32) (pl022->rx - pl022->rx_end));
1269 }
1270
1271 msg->actual_length += pl022->cur_transfer->len;
1272 if (pl022->cur_transfer->cs_change)
1273 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1274
1275 msg->state = next_transfer(pl022);
1276 tasklet_schedule(&pl022->pump_transfers);
1277 return IRQ_HANDLED;
1278 }
1279
1280 return IRQ_HANDLED;
1281}
1282
1283
1284
1285
1286
1287static int set_up_next_transfer(struct pl022 *pl022,
1288 struct spi_transfer *transfer)
1289{
1290 int residue;
1291
1292
1293 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1294 if (unlikely(residue != 0)) {
1295 dev_err(&pl022->adev->dev,
1296 "message of %u bytes to transmit but the current "
1297 "chip bus has a data width of %u bytes!\n",
1298 pl022->cur_transfer->len,
1299 pl022->cur_chip->n_bytes);
1300 dev_err(&pl022->adev->dev, "skipping this message\n");
1301 return -EIO;
1302 }
1303 pl022->tx = (void *)transfer->tx_buf;
1304 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1305 pl022->rx = (void *)transfer->rx_buf;
1306 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1307 pl022->write =
1308 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1309 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1310 return 0;
1311}
1312
1313
1314
1315
1316
1317
1318
1319static void pump_transfers(unsigned long data)
1320{
1321 struct pl022 *pl022 = (struct pl022 *) data;
1322 struct spi_message *message = NULL;
1323 struct spi_transfer *transfer = NULL;
1324 struct spi_transfer *previous = NULL;
1325
1326
1327 message = pl022->cur_msg;
1328 transfer = pl022->cur_transfer;
1329
1330
1331 if (message->state == STATE_ERROR) {
1332 message->status = -EIO;
1333 giveback(pl022);
1334 return;
1335 }
1336
1337
1338 if (message->state == STATE_DONE) {
1339 message->status = 0;
1340 giveback(pl022);
1341 return;
1342 }
1343
1344
1345 if (message->state == STATE_RUNNING) {
1346 previous = list_entry(transfer->transfer_list.prev,
1347 struct spi_transfer,
1348 transfer_list);
1349 if (previous->delay_usecs)
1350
1351
1352
1353
1354 udelay(previous->delay_usecs);
1355
1356
1357 if (previous->cs_change)
1358 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1359 } else {
1360
1361 message->state = STATE_RUNNING;
1362 }
1363
1364 if (set_up_next_transfer(pl022, transfer)) {
1365 message->state = STATE_ERROR;
1366 message->status = -EIO;
1367 giveback(pl022);
1368 return;
1369 }
1370
1371 flush(pl022);
1372
1373 if (pl022->cur_chip->enable_dma) {
1374 if (configure_dma(pl022)) {
1375 dev_dbg(&pl022->adev->dev,
1376 "configuration of DMA failed, fall back to interrupt mode\n");
1377 goto err_config_dma;
1378 }
1379 return;
1380 }
1381
1382err_config_dma:
1383
1384 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
1385}
1386
1387static void do_interrupt_dma_transfer(struct pl022 *pl022)
1388{
1389
1390
1391
1392
1393 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM;
1394
1395
1396 if (!pl022->next_msg_cs_active)
1397 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1398
1399 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1400
1401 pl022->cur_msg->state = STATE_ERROR;
1402 pl022->cur_msg->status = -EIO;
1403 giveback(pl022);
1404 return;
1405 }
1406
1407 if (pl022->cur_chip->enable_dma) {
1408
1409 if (configure_dma(pl022)) {
1410 dev_dbg(&pl022->adev->dev,
1411 "configuration of DMA failed, fall back to interrupt mode\n");
1412 goto err_config_dma;
1413 }
1414
1415 irqflags = DISABLE_ALL_INTERRUPTS;
1416 }
1417err_config_dma:
1418
1419 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1420 SSP_CR1(pl022->virtbase));
1421 writew(irqflags, SSP_IMSC(pl022->virtbase));
1422}
1423
1424static void do_polling_transfer(struct pl022 *pl022)
1425{
1426 struct spi_message *message = NULL;
1427 struct spi_transfer *transfer = NULL;
1428 struct spi_transfer *previous = NULL;
1429 struct chip_data *chip;
1430 unsigned long time, timeout;
1431
1432 chip = pl022->cur_chip;
1433 message = pl022->cur_msg;
1434
1435 while (message->state != STATE_DONE) {
1436
1437 if (message->state == STATE_ERROR)
1438 break;
1439 transfer = pl022->cur_transfer;
1440
1441
1442 if (message->state == STATE_RUNNING) {
1443 previous =
1444 list_entry(transfer->transfer_list.prev,
1445 struct spi_transfer, transfer_list);
1446 if (previous->delay_usecs)
1447 udelay(previous->delay_usecs);
1448 if (previous->cs_change)
1449 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1450 } else {
1451
1452 message->state = STATE_RUNNING;
1453 if (!pl022->next_msg_cs_active)
1454 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1455 }
1456
1457
1458 if (set_up_next_transfer(pl022, transfer)) {
1459
1460 message->state = STATE_ERROR;
1461 break;
1462 }
1463
1464 flush(pl022);
1465 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1466 SSP_CR1(pl022->virtbase));
1467
1468 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1469
1470 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1471 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1472 time = jiffies;
1473 readwriter(pl022);
1474 if (time_after(time, timeout)) {
1475 dev_warn(&pl022->adev->dev,
1476 "%s: timeout!\n", __func__);
1477 message->state = STATE_ERROR;
1478 goto out;
1479 }
1480 cpu_relax();
1481 }
1482
1483
1484 message->actual_length += pl022->cur_transfer->len;
1485 if (pl022->cur_transfer->cs_change)
1486 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1487
1488 message->state = next_transfer(pl022);
1489 }
1490out:
1491
1492 if (message->state == STATE_DONE)
1493 message->status = 0;
1494 else
1495 message->status = -EIO;
1496
1497 giveback(pl022);
1498 return;
1499}
1500
1501static int pl022_transfer_one_message(struct spi_master *master,
1502 struct spi_message *msg)
1503{
1504 struct pl022 *pl022 = spi_master_get_devdata(master);
1505
1506
1507 pl022->cur_msg = msg;
1508 msg->state = STATE_START;
1509
1510 pl022->cur_transfer = list_entry(msg->transfers.next,
1511 struct spi_transfer, transfer_list);
1512
1513
1514 pl022->cur_chip = spi_get_ctldata(msg->spi);
1515 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select];
1516
1517 restore_state(pl022);
1518 flush(pl022);
1519
1520 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1521 do_polling_transfer(pl022);
1522 else
1523 do_interrupt_dma_transfer(pl022);
1524
1525 return 0;
1526}
1527
1528static int pl022_prepare_transfer_hardware(struct spi_master *master)
1529{
1530 struct pl022 *pl022 = spi_master_get_devdata(master);
1531
1532
1533
1534
1535
1536 pm_runtime_get_sync(&pl022->adev->dev);
1537 return 0;
1538}
1539
1540static int pl022_unprepare_transfer_hardware(struct spi_master *master)
1541{
1542 struct pl022 *pl022 = spi_master_get_devdata(master);
1543
1544
1545 writew((readw(SSP_CR1(pl022->virtbase)) &
1546 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1547
1548 if (pl022->master_info->autosuspend_delay > 0) {
1549 pm_runtime_mark_last_busy(&pl022->adev->dev);
1550 pm_runtime_put_autosuspend(&pl022->adev->dev);
1551 } else {
1552 pm_runtime_put(&pl022->adev->dev);
1553 }
1554
1555 return 0;
1556}
1557
1558static int verify_controller_parameters(struct pl022 *pl022,
1559 struct pl022_config_chip const *chip_info)
1560{
1561 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1562 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1563 dev_err(&pl022->adev->dev,
1564 "interface is configured incorrectly\n");
1565 return -EINVAL;
1566 }
1567 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1568 (!pl022->vendor->unidir)) {
1569 dev_err(&pl022->adev->dev,
1570 "unidirectional mode not supported in this "
1571 "hardware version\n");
1572 return -EINVAL;
1573 }
1574 if ((chip_info->hierarchy != SSP_MASTER)
1575 && (chip_info->hierarchy != SSP_SLAVE)) {
1576 dev_err(&pl022->adev->dev,
1577 "hierarchy is configured incorrectly\n");
1578 return -EINVAL;
1579 }
1580 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1581 && (chip_info->com_mode != DMA_TRANSFER)
1582 && (chip_info->com_mode != POLLING_TRANSFER)) {
1583 dev_err(&pl022->adev->dev,
1584 "Communication mode is configured incorrectly\n");
1585 return -EINVAL;
1586 }
1587 switch (chip_info->rx_lev_trig) {
1588 case SSP_RX_1_OR_MORE_ELEM:
1589 case SSP_RX_4_OR_MORE_ELEM:
1590 case SSP_RX_8_OR_MORE_ELEM:
1591
1592 break;
1593 case SSP_RX_16_OR_MORE_ELEM:
1594 if (pl022->vendor->fifodepth < 16) {
1595 dev_err(&pl022->adev->dev,
1596 "RX FIFO Trigger Level is configured incorrectly\n");
1597 return -EINVAL;
1598 }
1599 break;
1600 case SSP_RX_32_OR_MORE_ELEM:
1601 if (pl022->vendor->fifodepth < 32) {
1602 dev_err(&pl022->adev->dev,
1603 "RX FIFO Trigger Level is configured incorrectly\n");
1604 return -EINVAL;
1605 }
1606 break;
1607 default:
1608 dev_err(&pl022->adev->dev,
1609 "RX FIFO Trigger Level is configured incorrectly\n");
1610 return -EINVAL;
1611 break;
1612 }
1613 switch (chip_info->tx_lev_trig) {
1614 case SSP_TX_1_OR_MORE_EMPTY_LOC:
1615 case SSP_TX_4_OR_MORE_EMPTY_LOC:
1616 case SSP_TX_8_OR_MORE_EMPTY_LOC:
1617
1618 break;
1619 case SSP_TX_16_OR_MORE_EMPTY_LOC:
1620 if (pl022->vendor->fifodepth < 16) {
1621 dev_err(&pl022->adev->dev,
1622 "TX FIFO Trigger Level is configured incorrectly\n");
1623 return -EINVAL;
1624 }
1625 break;
1626 case SSP_TX_32_OR_MORE_EMPTY_LOC:
1627 if (pl022->vendor->fifodepth < 32) {
1628 dev_err(&pl022->adev->dev,
1629 "TX FIFO Trigger Level is configured incorrectly\n");
1630 return -EINVAL;
1631 }
1632 break;
1633 default:
1634 dev_err(&pl022->adev->dev,
1635 "TX FIFO Trigger Level is configured incorrectly\n");
1636 return -EINVAL;
1637 break;
1638 }
1639 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1640 if ((chip_info->ctrl_len < SSP_BITS_4)
1641 || (chip_info->ctrl_len > SSP_BITS_32)) {
1642 dev_err(&pl022->adev->dev,
1643 "CTRL LEN is configured incorrectly\n");
1644 return -EINVAL;
1645 }
1646 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1647 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1648 dev_err(&pl022->adev->dev,
1649 "Wait State is configured incorrectly\n");
1650 return -EINVAL;
1651 }
1652
1653 if (pl022->vendor->extended_cr) {
1654 if ((chip_info->duplex !=
1655 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1656 && (chip_info->duplex !=
1657 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1658 dev_err(&pl022->adev->dev,
1659 "Microwire duplex mode is configured incorrectly\n");
1660 return -EINVAL;
1661 }
1662 } else {
1663 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1664 dev_err(&pl022->adev->dev,
1665 "Microwire half duplex mode requested,"
1666 " but this is only available in the"
1667 " ST version of PL022\n");
1668 return -EINVAL;
1669 }
1670 }
1671 return 0;
1672}
1673
1674static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1675{
1676 return rate / (cpsdvsr * (1 + scr));
1677}
1678
1679static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1680 ssp_clock_params * clk_freq)
1681{
1682
1683 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1684 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
1685 best_scr = 0, tmp, found = 0;
1686
1687 rate = clk_get_rate(pl022->clk);
1688
1689 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
1690
1691 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
1692
1693 if (freq > max_tclk)
1694 dev_warn(&pl022->adev->dev,
1695 "Max speed that can be programmed is %d Hz, you requested %d\n",
1696 max_tclk, freq);
1697
1698 if (freq < min_tclk) {
1699 dev_err(&pl022->adev->dev,
1700 "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
1701 freq, min_tclk);
1702 return -EINVAL;
1703 }
1704
1705
1706
1707
1708
1709 while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1710 while (scr <= SCR_MAX) {
1711 tmp = spi_rate(rate, cpsdvsr, scr);
1712
1713 if (tmp > freq) {
1714
1715 scr++;
1716 continue;
1717 }
1718
1719
1720
1721
1722
1723 if (tmp > best_freq) {
1724 best_freq = tmp;
1725 best_cpsdvsr = cpsdvsr;
1726 best_scr = scr;
1727
1728 if (tmp == freq)
1729 found = 1;
1730 }
1731
1732
1733
1734
1735 break;
1736 }
1737 cpsdvsr += 2;
1738 scr = SCR_MIN;
1739 }
1740
1741 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1742 freq);
1743
1744 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1745 clk_freq->scr = (u8) (best_scr & 0xFF);
1746 dev_dbg(&pl022->adev->dev,
1747 "SSP Target Frequency is: %u, Effective Frequency is %u\n",
1748 freq, best_freq);
1749 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1750 clk_freq->cpsdvsr, clk_freq->scr);
1751
1752 return 0;
1753}
1754
1755
1756
1757
1758
1759static const struct pl022_config_chip pl022_default_chip_info = {
1760 .com_mode = POLLING_TRANSFER,
1761 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1762 .hierarchy = SSP_SLAVE,
1763 .slave_tx_disable = DO_NOT_DRIVE_TX,
1764 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1765 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1766 .ctrl_len = SSP_BITS_8,
1767 .wait_state = SSP_MWIRE_WAIT_ZERO,
1768 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1769 .cs_control = null_cs_control,
1770};
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784static int pl022_setup(struct spi_device *spi)
1785{
1786 struct pl022_config_chip const *chip_info;
1787 struct pl022_config_chip chip_info_dt;
1788 struct chip_data *chip;
1789 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
1790 int status = 0;
1791 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1792 unsigned int bits = spi->bits_per_word;
1793 u32 tmp;
1794 struct device_node *np = spi->dev.of_node;
1795
1796 if (!spi->max_speed_hz)
1797 return -EINVAL;
1798
1799
1800 chip = spi_get_ctldata(spi);
1801
1802 if (chip == NULL) {
1803 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1804 if (!chip) {
1805 dev_err(&spi->dev,
1806 "cannot allocate controller state\n");
1807 return -ENOMEM;
1808 }
1809 dev_dbg(&spi->dev,
1810 "allocated memory for controller's runtime state\n");
1811 }
1812
1813
1814 chip_info = spi->controller_data;
1815
1816 if (chip_info == NULL) {
1817 if (np) {
1818 chip_info_dt = pl022_default_chip_info;
1819
1820 chip_info_dt.hierarchy = SSP_MASTER;
1821 of_property_read_u32(np, "pl022,interface",
1822 &chip_info_dt.iface);
1823 of_property_read_u32(np, "pl022,com-mode",
1824 &chip_info_dt.com_mode);
1825 of_property_read_u32(np, "pl022,rx-level-trig",
1826 &chip_info_dt.rx_lev_trig);
1827 of_property_read_u32(np, "pl022,tx-level-trig",
1828 &chip_info_dt.tx_lev_trig);
1829 of_property_read_u32(np, "pl022,ctrl-len",
1830 &chip_info_dt.ctrl_len);
1831 of_property_read_u32(np, "pl022,wait-state",
1832 &chip_info_dt.wait_state);
1833 of_property_read_u32(np, "pl022,duplex",
1834 &chip_info_dt.duplex);
1835
1836 chip_info = &chip_info_dt;
1837 } else {
1838 chip_info = &pl022_default_chip_info;
1839
1840 dev_dbg(&spi->dev,
1841 "using default controller_data settings\n");
1842 }
1843 } else
1844 dev_dbg(&spi->dev,
1845 "using user supplied controller_data settings\n");
1846
1847
1848
1849
1850
1851 if ((0 == chip_info->clk_freq.cpsdvsr)
1852 && (0 == chip_info->clk_freq.scr)) {
1853 status = calculate_effective_freq(pl022,
1854 spi->max_speed_hz,
1855 &clk_freq);
1856 if (status < 0)
1857 goto err_config_params;
1858 } else {
1859 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1860 if ((clk_freq.cpsdvsr % 2) != 0)
1861 clk_freq.cpsdvsr =
1862 clk_freq.cpsdvsr - 1;
1863 }
1864 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1865 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1866 status = -EINVAL;
1867 dev_err(&spi->dev,
1868 "cpsdvsr is configured incorrectly\n");
1869 goto err_config_params;
1870 }
1871
1872 status = verify_controller_parameters(pl022, chip_info);
1873 if (status) {
1874 dev_err(&spi->dev, "controller data is incorrect");
1875 goto err_config_params;
1876 }
1877
1878 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1879 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1880
1881
1882 chip->xfer_type = chip_info->com_mode;
1883 if (!chip_info->cs_control) {
1884 chip->cs_control = null_cs_control;
1885 if (!gpio_is_valid(pl022->chipselects[spi->chip_select]))
1886 dev_warn(&spi->dev,
1887 "invalid chip select\n");
1888 } else
1889 chip->cs_control = chip_info->cs_control;
1890
1891
1892 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
1893 status = -ENOTSUPP;
1894 dev_err(&spi->dev, "illegal data size for this controller!\n");
1895 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
1896 pl022->vendor->max_bpw);
1897 goto err_config_params;
1898 } else if (bits <= 8) {
1899 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1900 chip->n_bytes = 1;
1901 chip->read = READING_U8;
1902 chip->write = WRITING_U8;
1903 } else if (bits <= 16) {
1904 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1905 chip->n_bytes = 2;
1906 chip->read = READING_U16;
1907 chip->write = WRITING_U16;
1908 } else {
1909 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1910 chip->n_bytes = 4;
1911 chip->read = READING_U32;
1912 chip->write = WRITING_U32;
1913 }
1914
1915
1916 chip->cr0 = 0;
1917 chip->cr1 = 0;
1918 chip->dmacr = 0;
1919 chip->cpsr = 0;
1920 if ((chip_info->com_mode == DMA_TRANSFER)
1921 && ((pl022->master_info)->enable_dma)) {
1922 chip->enable_dma = true;
1923 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
1924 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1925 SSP_DMACR_MASK_RXDMAE, 0);
1926 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1927 SSP_DMACR_MASK_TXDMAE, 1);
1928 } else {
1929 chip->enable_dma = false;
1930 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1931 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1932 SSP_DMACR_MASK_RXDMAE, 0);
1933 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1934 SSP_DMACR_MASK_TXDMAE, 1);
1935 }
1936
1937 chip->cpsr = clk_freq.cpsdvsr;
1938
1939
1940 if (pl022->vendor->extended_cr) {
1941 u32 etx;
1942
1943 if (pl022->vendor->pl023) {
1944
1945 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1946 SSP_CR1_MASK_FBCLKDEL_ST, 13);
1947 } else {
1948
1949 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1950 SSP_CR0_MASK_HALFDUP_ST, 5);
1951 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1952 SSP_CR0_MASK_CSS_ST, 16);
1953 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1954 SSP_CR0_MASK_FRF_ST, 21);
1955 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1956 SSP_CR1_MASK_MWAIT_ST, 6);
1957 }
1958 SSP_WRITE_BITS(chip->cr0, bits - 1,
1959 SSP_CR0_MASK_DSS_ST, 0);
1960
1961 if (spi->mode & SPI_LSB_FIRST) {
1962 tmp = SSP_RX_LSB;
1963 etx = SSP_TX_LSB;
1964 } else {
1965 tmp = SSP_RX_MSB;
1966 etx = SSP_TX_MSB;
1967 }
1968 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
1969 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
1970 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
1971 SSP_CR1_MASK_RXIFLSEL_ST, 7);
1972 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
1973 SSP_CR1_MASK_TXIFLSEL_ST, 10);
1974 } else {
1975 SSP_WRITE_BITS(chip->cr0, bits - 1,
1976 SSP_CR0_MASK_DSS, 0);
1977 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1978 SSP_CR0_MASK_FRF, 4);
1979 }
1980
1981
1982 if (spi->mode & SPI_CPOL)
1983 tmp = SSP_CLK_POL_IDLE_HIGH;
1984 else
1985 tmp = SSP_CLK_POL_IDLE_LOW;
1986 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
1987
1988 if (spi->mode & SPI_CPHA)
1989 tmp = SSP_CLK_SECOND_EDGE;
1990 else
1991 tmp = SSP_CLK_FIRST_EDGE;
1992 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
1993
1994 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
1995
1996 if (pl022->vendor->loopback) {
1997 if (spi->mode & SPI_LOOP)
1998 tmp = LOOPBACK_ENABLED;
1999 else
2000 tmp = LOOPBACK_DISABLED;
2001 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2002 }
2003 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2004 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2005 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
2006 3);
2007
2008
2009 spi_set_ctldata(spi, chip);
2010 return status;
2011 err_config_params:
2012 spi_set_ctldata(spi, NULL);
2013 kfree(chip);
2014 return status;
2015}
2016
2017
2018
2019
2020
2021
2022
2023
2024static void pl022_cleanup(struct spi_device *spi)
2025{
2026 struct chip_data *chip = spi_get_ctldata(spi);
2027
2028 spi_set_ctldata(spi, NULL);
2029 kfree(chip);
2030}
2031
2032static struct pl022_ssp_controller *
2033pl022_platform_data_dt_get(struct device *dev)
2034{
2035 struct device_node *np = dev->of_node;
2036 struct pl022_ssp_controller *pd;
2037 u32 tmp;
2038
2039 if (!np) {
2040 dev_err(dev, "no dt node defined\n");
2041 return NULL;
2042 }
2043
2044 pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
2045 if (!pd) {
2046 dev_err(dev, "cannot allocate platform data memory\n");
2047 return NULL;
2048 }
2049
2050 pd->bus_id = -1;
2051 of_property_read_u32(np, "num-cs", &tmp);
2052 pd->num_chipselect = tmp;
2053 of_property_read_u32(np, "pl022,autosuspend-delay",
2054 &pd->autosuspend_delay);
2055 pd->rt = of_property_read_bool(np, "pl022,rt");
2056
2057 return pd;
2058}
2059
2060static int __devinit
2061pl022_probe(struct amba_device *adev, const struct amba_id *id)
2062{
2063 struct device *dev = &adev->dev;
2064 struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
2065 struct spi_master *master;
2066 struct pl022 *pl022 = NULL;
2067 struct device_node *np = adev->dev.of_node;
2068 int status = 0, i, num_cs;
2069
2070 dev_info(&adev->dev,
2071 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2072 if (!platform_info && IS_ENABLED(CONFIG_OF))
2073 platform_info = pl022_platform_data_dt_get(dev);
2074
2075 if (!platform_info) {
2076 dev_err(dev, "probe: no platform data defined\n");
2077 return -ENODEV;
2078 }
2079
2080 if (platform_info->num_chipselect) {
2081 num_cs = platform_info->num_chipselect;
2082 } else {
2083 dev_err(dev, "probe: no chip select defined\n");
2084 return -ENODEV;
2085 }
2086
2087
2088 master = spi_alloc_master(dev, sizeof(struct pl022));
2089 if (master == NULL) {
2090 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2091 return -ENOMEM;
2092 }
2093
2094 pl022 = spi_master_get_devdata(master);
2095 pl022->master = master;
2096 pl022->master_info = platform_info;
2097 pl022->adev = adev;
2098 pl022->vendor = id->data;
2099 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int),
2100 GFP_KERNEL);
2101
2102 pl022->pinctrl = devm_pinctrl_get(dev);
2103 if (IS_ERR(pl022->pinctrl)) {
2104 status = PTR_ERR(pl022->pinctrl);
2105 goto err_no_pinctrl;
2106 }
2107
2108 pl022->pins_default = pinctrl_lookup_state(pl022->pinctrl,
2109 PINCTRL_STATE_DEFAULT);
2110
2111 if (!IS_ERR(pl022->pins_default)) {
2112 status = pinctrl_select_state(pl022->pinctrl,
2113 pl022->pins_default);
2114 if (status)
2115 dev_err(dev, "could not set default pins\n");
2116 } else
2117 dev_err(dev, "could not get default pinstate\n");
2118
2119 pl022->pins_sleep = pinctrl_lookup_state(pl022->pinctrl,
2120 PINCTRL_STATE_SLEEP);
2121 if (IS_ERR(pl022->pins_sleep))
2122 dev_dbg(dev, "could not get sleep pinstate\n");
2123
2124
2125
2126
2127
2128 master->bus_num = platform_info->bus_id;
2129 master->num_chipselect = num_cs;
2130 master->cleanup = pl022_cleanup;
2131 master->setup = pl022_setup;
2132 master->prepare_transfer_hardware = pl022_prepare_transfer_hardware;
2133 master->transfer_one_message = pl022_transfer_one_message;
2134 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
2135 master->rt = platform_info->rt;
2136 master->dev.of_node = dev->of_node;
2137
2138 if (platform_info->num_chipselect && platform_info->chipselects) {
2139 for (i = 0; i < num_cs; i++)
2140 pl022->chipselects[i] = platform_info->chipselects[i];
2141 } else if (IS_ENABLED(CONFIG_OF)) {
2142 for (i = 0; i < num_cs; i++) {
2143 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
2144
2145 if (cs_gpio == -EPROBE_DEFER) {
2146 status = -EPROBE_DEFER;
2147 goto err_no_gpio;
2148 }
2149
2150 pl022->chipselects[i] = cs_gpio;
2151
2152 if (gpio_is_valid(cs_gpio)) {
2153 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022"))
2154 dev_err(&adev->dev,
2155 "could not request %d gpio\n",
2156 cs_gpio);
2157 else if (gpio_direction_output(cs_gpio, 1))
2158 dev_err(&adev->dev,
2159 "could set gpio %d as output\n",
2160 cs_gpio);
2161 }
2162 }
2163 }
2164
2165
2166
2167
2168
2169 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2170 if (pl022->vendor->extended_cr)
2171 master->mode_bits |= SPI_LSB_FIRST;
2172
2173 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2174
2175 status = amba_request_regions(adev, NULL);
2176 if (status)
2177 goto err_no_ioregion;
2178
2179 pl022->phybase = adev->res.start;
2180 pl022->virtbase = devm_ioremap(dev, adev->res.start,
2181 resource_size(&adev->res));
2182 if (pl022->virtbase == NULL) {
2183 status = -ENOMEM;
2184 goto err_no_ioremap;
2185 }
2186 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
2187 adev->res.start, pl022->virtbase);
2188
2189 pl022->clk = devm_clk_get(&adev->dev, NULL);
2190 if (IS_ERR(pl022->clk)) {
2191 status = PTR_ERR(pl022->clk);
2192 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2193 goto err_no_clk;
2194 }
2195
2196 status = clk_prepare(pl022->clk);
2197 if (status) {
2198 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n");
2199 goto err_clk_prep;
2200 }
2201
2202 status = clk_enable(pl022->clk);
2203 if (status) {
2204 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
2205 goto err_no_clk_en;
2206 }
2207
2208
2209 tasklet_init(&pl022->pump_transfers, pump_transfers,
2210 (unsigned long)pl022);
2211
2212
2213 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2214 SSP_CR1(pl022->virtbase));
2215 load_ssp_default_config(pl022);
2216
2217 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
2218 0, "pl022", pl022);
2219 if (status < 0) {
2220 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2221 goto err_no_irq;
2222 }
2223
2224
2225 if (platform_info->enable_dma) {
2226 status = pl022_dma_probe(pl022);
2227 if (status != 0)
2228 platform_info->enable_dma = 0;
2229 }
2230
2231
2232 amba_set_drvdata(adev, pl022);
2233 status = spi_register_master(master);
2234 if (status != 0) {
2235 dev_err(&adev->dev,
2236 "probe - problem registering spi master\n");
2237 goto err_spi_register;
2238 }
2239 dev_dbg(dev, "probe succeeded\n");
2240
2241
2242 if (platform_info->autosuspend_delay > 0) {
2243 dev_info(&adev->dev,
2244 "will use autosuspend for runtime pm, delay %dms\n",
2245 platform_info->autosuspend_delay);
2246 pm_runtime_set_autosuspend_delay(dev,
2247 platform_info->autosuspend_delay);
2248 pm_runtime_use_autosuspend(dev);
2249 pm_runtime_put_autosuspend(dev);
2250 } else {
2251 pm_runtime_put(dev);
2252 }
2253 return 0;
2254
2255 err_spi_register:
2256 if (platform_info->enable_dma)
2257 pl022_dma_remove(pl022);
2258 err_no_irq:
2259 clk_disable(pl022->clk);
2260 err_no_clk_en:
2261 clk_unprepare(pl022->clk);
2262 err_clk_prep:
2263 err_no_clk:
2264 err_no_ioremap:
2265 amba_release_regions(adev);
2266 err_no_ioregion:
2267 err_no_gpio:
2268 err_no_pinctrl:
2269 spi_master_put(master);
2270 return status;
2271}
2272
2273static int __devexit
2274pl022_remove(struct amba_device *adev)
2275{
2276 struct pl022 *pl022 = amba_get_drvdata(adev);
2277
2278 if (!pl022)
2279 return 0;
2280
2281
2282
2283
2284
2285 pm_runtime_get_noresume(&adev->dev);
2286
2287 load_ssp_default_config(pl022);
2288 if (pl022->master_info->enable_dma)
2289 pl022_dma_remove(pl022);
2290
2291 clk_disable(pl022->clk);
2292 clk_unprepare(pl022->clk);
2293 amba_release_regions(adev);
2294 tasklet_disable(&pl022->pump_transfers);
2295 spi_unregister_master(pl022->master);
2296 amba_set_drvdata(adev, NULL);
2297 return 0;
2298}
2299
2300#if defined(CONFIG_SUSPEND) || defined(CONFIG_PM_RUNTIME)
2301
2302
2303
2304
2305
2306static void pl022_suspend_resources(struct pl022 *pl022)
2307{
2308 int ret;
2309
2310 clk_disable(pl022->clk);
2311
2312
2313 if (!IS_ERR(pl022->pins_sleep)) {
2314 ret = pinctrl_select_state(pl022->pinctrl,
2315 pl022->pins_sleep);
2316 if (ret)
2317 dev_err(&pl022->adev->dev,
2318 "could not set pins to sleep state\n");
2319 }
2320}
2321
2322static void pl022_resume_resources(struct pl022 *pl022)
2323{
2324 int ret;
2325
2326
2327 if (!IS_ERR(pl022->pins_default)) {
2328 ret = pinctrl_select_state(pl022->pinctrl,
2329 pl022->pins_default);
2330 if (ret)
2331 dev_err(&pl022->adev->dev,
2332 "could not set default pins\n");
2333 }
2334
2335 clk_enable(pl022->clk);
2336}
2337#endif
2338
2339#ifdef CONFIG_SUSPEND
2340static int pl022_suspend(struct device *dev)
2341{
2342 struct pl022 *pl022 = dev_get_drvdata(dev);
2343 int ret;
2344
2345 ret = spi_master_suspend(pl022->master);
2346 if (ret) {
2347 dev_warn(dev, "cannot suspend master\n");
2348 return ret;
2349 }
2350 pl022_suspend_resources(pl022);
2351
2352 dev_dbg(dev, "suspended\n");
2353 return 0;
2354}
2355
2356static int pl022_resume(struct device *dev)
2357{
2358 struct pl022 *pl022 = dev_get_drvdata(dev);
2359 int ret;
2360
2361 pl022_resume_resources(pl022);
2362
2363
2364 ret = spi_master_resume(pl022->master);
2365 if (ret)
2366 dev_err(dev, "problem starting queue (%d)\n", ret);
2367 else
2368 dev_dbg(dev, "resumed\n");
2369
2370 return ret;
2371}
2372#endif
2373
2374#ifdef CONFIG_PM_RUNTIME
2375static int pl022_runtime_suspend(struct device *dev)
2376{
2377 struct pl022 *pl022 = dev_get_drvdata(dev);
2378
2379 pl022_suspend_resources(pl022);
2380 return 0;
2381}
2382
2383static int pl022_runtime_resume(struct device *dev)
2384{
2385 struct pl022 *pl022 = dev_get_drvdata(dev);
2386
2387 pl022_resume_resources(pl022);
2388 return 0;
2389}
2390#endif
2391
2392static const struct dev_pm_ops pl022_dev_pm_ops = {
2393 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2394 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2395};
2396
2397static struct vendor_data vendor_arm = {
2398 .fifodepth = 8,
2399 .max_bpw = 16,
2400 .unidir = false,
2401 .extended_cr = false,
2402 .pl023 = false,
2403 .loopback = true,
2404};
2405
2406static struct vendor_data vendor_st = {
2407 .fifodepth = 32,
2408 .max_bpw = 32,
2409 .unidir = false,
2410 .extended_cr = true,
2411 .pl023 = false,
2412 .loopback = true,
2413};
2414
2415static struct vendor_data vendor_st_pl023 = {
2416 .fifodepth = 32,
2417 .max_bpw = 32,
2418 .unidir = false,
2419 .extended_cr = true,
2420 .pl023 = true,
2421 .loopback = false,
2422};
2423
2424static struct amba_id pl022_ids[] = {
2425 {
2426
2427
2428
2429
2430 .id = 0x00041022,
2431 .mask = 0x000fffff,
2432 .data = &vendor_arm,
2433 },
2434 {
2435
2436
2437
2438
2439 .id = 0x01080022,
2440 .mask = 0xffffffff,
2441 .data = &vendor_st,
2442 },
2443 {
2444
2445
2446
2447
2448
2449
2450
2451 .id = 0x00080023,
2452 .mask = 0xffffffff,
2453 .data = &vendor_st_pl023,
2454 },
2455 { 0, 0 },
2456};
2457
2458MODULE_DEVICE_TABLE(amba, pl022_ids);
2459
2460static struct amba_driver pl022_driver = {
2461 .drv = {
2462 .name = "ssp-pl022",
2463 .pm = &pl022_dev_pm_ops,
2464 },
2465 .id_table = pl022_ids,
2466 .probe = pl022_probe,
2467 .remove = __devexit_p(pl022_remove),
2468};
2469
2470static int __init pl022_init(void)
2471{
2472 return amba_driver_register(&pl022_driver);
2473}
2474subsys_initcall(pl022_init);
2475
2476static void __exit pl022_exit(void)
2477{
2478 amba_driver_unregister(&pl022_driver);
2479}
2480module_exit(pl022_exit);
2481
2482MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2483MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2484MODULE_LICENSE("GPL");
2485