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12#ifndef __DRM_IPU_H__
13#define __DRM_IPU_H__
14
15#include <linux/types.h>
16#include <linux/videodev2.h>
17#include <linux/bitmap.h>
18#include <linux/fb.h>
19#include <linux/videodev2.h>
20
21struct ipu_soc;
22
23enum ipuv3_type {
24 IPUV3EX,
25 IPUV3M,
26 IPUV3H,
27};
28
29
30
31
32struct ipu_di_signal_cfg {
33 unsigned datamask_en:1;
34 unsigned interlaced:1;
35 unsigned odd_field_first:1;
36 unsigned clksel_en:1;
37 unsigned clkidle_en:1;
38 unsigned data_pol:1;
39 unsigned clk_pol:1;
40 unsigned enable_pol:1;
41 unsigned Hsync_pol:1;
42 unsigned Vsync_pol:1;
43
44 u16 width;
45 u16 height;
46 u32 pixel_fmt;
47 u16 h_start_width;
48 u16 h_sync_width;
49 u16 h_end_width;
50 u16 v_start_width;
51 u16 v_sync_width;
52 u16 v_end_width;
53 u32 v_to_h_sync;
54 unsigned long pixelclock;
55#define IPU_DI_CLKMODE_SYNC (1 << 0)
56#define IPU_DI_CLKMODE_EXT (1 << 1)
57 unsigned long clkflags;
58};
59
60enum ipu_color_space {
61 IPUV3_COLORSPACE_RGB,
62 IPUV3_COLORSPACE_YUV,
63 IPUV3_COLORSPACE_UNKNOWN,
64};
65
66struct ipuv3_channel;
67
68enum ipu_channel_irq {
69 IPU_IRQ_EOF = 0,
70 IPU_IRQ_NFACK = 64,
71 IPU_IRQ_NFB4EOF = 128,
72 IPU_IRQ_EOS = 192,
73};
74
75int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
76 enum ipu_channel_irq irq);
77
78#define IPU_IRQ_DP_SF_START (448 + 2)
79#define IPU_IRQ_DP_SF_END (448 + 3)
80#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
81#define IPU_IRQ_DC_FC_0 (448 + 8)
82#define IPU_IRQ_DC_FC_1 (448 + 9)
83#define IPU_IRQ_DC_FC_2 (448 + 10)
84#define IPU_IRQ_DC_FC_3 (448 + 11)
85#define IPU_IRQ_DC_FC_4 (448 + 12)
86#define IPU_IRQ_DC_FC_6 (448 + 13)
87#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
88#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
89
90
91
92
93struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
94void ipu_idmac_put(struct ipuv3_channel *);
95
96int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
97int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
98
99void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
100 bool doublebuffer);
101void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
102
103
104
105
106struct ipu_dc;
107struct ipu_di;
108struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
109void ipu_dc_put(struct ipu_dc *dc);
110int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
111 u32 pixel_fmt, u32 width);
112void ipu_dc_enable_channel(struct ipu_dc *dc);
113void ipu_dc_disable_channel(struct ipu_dc *dc);
114
115
116
117
118struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
119void ipu_di_put(struct ipu_di *);
120int ipu_di_disable(struct ipu_di *);
121int ipu_di_enable(struct ipu_di *);
122int ipu_di_get_num(struct ipu_di *);
123int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
124
125
126
127
128struct dmfc_channel;
129int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
130void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
131int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
132 unsigned long bandwidth_mbs, int burstsize);
133void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
134int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
135struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
136void ipu_dmfc_put(struct dmfc_channel *dmfc);
137
138
139
140
141#define IPU_DP_FLOW_SYNC_BG 0
142#define IPU_DP_FLOW_SYNC_FG 1
143#define IPU_DP_FLOW_ASYNC0_BG 2
144#define IPU_DP_FLOW_ASYNC0_FG 3
145#define IPU_DP_FLOW_ASYNC1_BG 4
146#define IPU_DP_FLOW_ASYNC1_FG 5
147
148struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
149void ipu_dp_put(struct ipu_dp *);
150int ipu_dp_enable_channel(struct ipu_dp *dp);
151void ipu_dp_disable_channel(struct ipu_dp *dp);
152int ipu_dp_setup_channel(struct ipu_dp *dp,
153 enum ipu_color_space in, enum ipu_color_space out);
154int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
155int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
156 bool bg_chan);
157
158#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
159
160#define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22)
161#define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22)
162#define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
163#define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1)
164#define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1)
165#define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14)
166#define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14)
167
168#define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10)
169#define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9)
170#define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13)
171#define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12)
172#define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1)
173#define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1)
174#define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12)
175#define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11)
176#define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10)
177#define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7)
178#define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10)
179#define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1)
180#define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1)
181#define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7)
182#define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1)
183#define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1)
184#define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3)
185#define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2)
186#define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1)
187#define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3)
188#define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2)
189#define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1)
190#define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1)
191#define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1)
192#define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1)
193#define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1)
194#define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1)
195#define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13)
196#define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12)
197#define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29)
198#define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29)
199#define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20)
200#define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7)
201#define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
202#define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1)
203#define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3)
204#define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2)
205#define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7)
206#define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14)
207#define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3)
208#define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3)
209#define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3)
210#define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3)
211#define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5)
212#define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5)
213#define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5)
214#define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5)
215#define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1)
216#define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1)
217#define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1)
218
219struct ipu_cpmem_word {
220 u32 data[5];
221 u32 res[3];
222};
223
224struct ipu_ch_param {
225 struct ipu_cpmem_word word[2];
226};
227
228void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v);
229u32 ipu_ch_param_read_field(struct ipu_ch_param __iomem *base, u32 wbs);
230struct ipu_ch_param __iomem *ipu_get_cpmem(struct ipuv3_channel *channel);
231void ipu_ch_param_dump(struct ipu_ch_param __iomem *p);
232
233static inline void ipu_ch_param_zero(struct ipu_ch_param __iomem *p)
234{
235 int i;
236 void __iomem *base = p;
237
238 for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
239 writel(0, base + i * sizeof(u32));
240}
241
242static inline void ipu_cpmem_set_buffer(struct ipu_ch_param __iomem *p,
243 int bufnum, dma_addr_t buf)
244{
245 if (bufnum)
246 ipu_ch_param_write_field(p, IPU_FIELD_EBA1, buf >> 3);
247 else
248 ipu_ch_param_write_field(p, IPU_FIELD_EBA0, buf >> 3);
249}
250
251static inline void ipu_cpmem_set_resolution(struct ipu_ch_param __iomem *p,
252 int xres, int yres)
253{
254 ipu_ch_param_write_field(p, IPU_FIELD_FW, xres - 1);
255 ipu_ch_param_write_field(p, IPU_FIELD_FH, yres - 1);
256}
257
258static inline void ipu_cpmem_set_stride(struct ipu_ch_param __iomem *p,
259 int stride)
260{
261 ipu_ch_param_write_field(p, IPU_FIELD_SLY, stride - 1);
262}
263
264void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel);
265
266struct ipu_rgb {
267 struct fb_bitfield red;
268 struct fb_bitfield green;
269 struct fb_bitfield blue;
270 struct fb_bitfield transp;
271 int bits_per_pixel;
272};
273
274struct ipu_image {
275 struct v4l2_pix_format pix;
276 struct v4l2_rect rect;
277 dma_addr_t phys;
278};
279
280int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem *p,
281 int width);
282
283int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *,
284 struct ipu_rgb *rgb);
285
286static inline void ipu_cpmem_interlaced_scan(struct ipu_ch_param *p,
287 int stride)
288{
289 ipu_ch_param_write_field(p, IPU_FIELD_SO, 1);
290 ipu_ch_param_write_field(p, IPU_FIELD_ILO, stride / 8);
291 ipu_ch_param_write_field(p, IPU_FIELD_SLY, (stride * 2) - 1);
292};
293
294void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem *p, u32 pixel_format,
295 int stride, int height);
296void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem *p,
297 u32 pixel_format, int stride, int u_offset, int v_offset);
298int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 pixelformat);
299int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem,
300 struct ipu_image *image);
301
302enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
303
304static inline void ipu_cpmem_set_burstsize(struct ipu_ch_param __iomem *p,
305 int burstsize)
306{
307 ipu_ch_param_write_field(p, IPU_FIELD_NPB, burstsize - 1);
308};
309
310struct ipu_client_platformdata {
311 int di;
312 int dc;
313 int dp;
314 int dmfc;
315 int dma[2];
316};
317
318#endif
319
