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19#define L4_34XX_BASE 0x48000000
20
21#include <linux/types.h>
22
23
24#include <dspbridge/host_os.h>
25#include <plat/dmtimer.h>
26#include <linux/platform_data/asoc-ti-mcbsp.h>
27
28
29#include <dspbridge/dbdefs.h>
30#include <dspbridge/drv.h>
31#include <dspbridge/dev.h>
32#include "_tiomap.h"
33
34
35#include <dspbridge/clk.h>
36
37
38
39#define OMAP_SSI_OFFSET 0x58000
40#define OMAP_SSI_SIZE 0x1000
41#define OMAP_SSI_SYSCONFIG_OFFSET 0x10
42
43#define SSI_AUTOIDLE (1 << 0)
44#define SSI_SIDLE_SMARTIDLE (2 << 3)
45#define SSI_MIDLE_NOIDLE (1 << 12)
46
47
48#define IVA2_CLK 0
49#define GPT_CLK 1
50#define WDT_CLK 2
51#define MCBSP_CLK 3
52#define SSI_CLK 4
53
54
55#define DMT_ID(id) ((id) + 4)
56#define DM_TIMER_CLOCKS 4
57
58
59#define MCBSP_ID(id) ((id) - 6)
60
61static struct omap_dm_timer *timer[4];
62
63struct clk *iva2_clk;
64
65struct dsp_ssi {
66 struct clk *sst_fck;
67 struct clk *ssr_fck;
68 struct clk *ick;
69};
70
71static struct dsp_ssi ssi;
72
73static u32 dsp_clocks;
74
75static inline u32 is_dsp_clk_active(u32 clk, u8 id)
76{
77 return clk & (1 << id);
78}
79
80static inline void set_dsp_clk_active(u32 *clk, u8 id)
81{
82 *clk |= (1 << id);
83}
84
85static inline void set_dsp_clk_inactive(u32 *clk, u8 id)
86{
87 *clk &= ~(1 << id);
88}
89
90static s8 get_clk_type(u8 id)
91{
92 s8 type;
93
94 if (id == DSP_CLK_IVA2)
95 type = IVA2_CLK;
96 else if (id <= DSP_CLK_GPT8)
97 type = GPT_CLK;
98 else if (id == DSP_CLK_WDT3)
99 type = WDT_CLK;
100 else if (id <= DSP_CLK_MCBSP5)
101 type = MCBSP_CLK;
102 else if (id == DSP_CLK_SSI)
103 type = SSI_CLK;
104 else
105 type = -1;
106
107 return type;
108}
109
110
111
112
113
114
115void dsp_clk_exit(void)
116{
117 int i;
118
119 dsp_clock_disable_all(dsp_clocks);
120
121 for (i = 0; i < DM_TIMER_CLOCKS; i++)
122 omap_dm_timer_free(timer[i]);
123
124 clk_put(iva2_clk);
125 clk_put(ssi.sst_fck);
126 clk_put(ssi.ssr_fck);
127 clk_put(ssi.ick);
128}
129
130
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132
133
134
135void dsp_clk_init(void)
136{
137 static struct platform_device dspbridge_device;
138 int i, id;
139
140 dspbridge_device.dev.bus = &platform_bus_type;
141
142 for (i = 0, id = 5; i < DM_TIMER_CLOCKS; i++, id++)
143 timer[i] = omap_dm_timer_request_specific(id);
144
145 iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck");
146 if (IS_ERR(iva2_clk))
147 dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk);
148
149 ssi.sst_fck = clk_get(&dspbridge_device.dev, "ssi_sst_fck");
150 ssi.ssr_fck = clk_get(&dspbridge_device.dev, "ssi_ssr_fck");
151 ssi.ick = clk_get(&dspbridge_device.dev, "ssi_ick");
152
153 if (IS_ERR(ssi.sst_fck) || IS_ERR(ssi.ssr_fck) || IS_ERR(ssi.ick))
154 dev_err(bridge, "failed to get ssi: sst %p, ssr %p, ick %p\n",
155 ssi.sst_fck, ssi.ssr_fck, ssi.ick);
156}
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165
166void dsp_gpt_wait_overflow(short int clk_id, unsigned int load)
167{
168 struct omap_dm_timer *gpt = timer[clk_id - 1];
169 unsigned long timeout;
170
171 if (!gpt)
172 return;
173
174
175 omap_dm_timer_set_int_enable(gpt, OMAP_TIMER_INT_OVERFLOW);
176
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179
180
181 omap_dm_timer_set_load_start(gpt, 0, load);
182
183
184 udelay(80);
185
186 timeout = msecs_to_jiffies(5);
187
188 while (!(omap_dm_timer_read_status(gpt) & OMAP_TIMER_INT_OVERFLOW)) {
189 if (time_is_after_jiffies(timeout)) {
190 pr_err("%s: GPTimer interrupt failed\n", __func__);
191 break;
192 }
193 }
194}
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200
201
202int dsp_clk_enable(enum dsp_clk_id clk_id)
203{
204 int status = 0;
205
206 if (is_dsp_clk_active(dsp_clocks, clk_id)) {
207 dev_err(bridge, "WARN: clock id %d already enabled\n", clk_id);
208 goto out;
209 }
210
211 switch (get_clk_type(clk_id)) {
212 case IVA2_CLK:
213 clk_enable(iva2_clk);
214 break;
215 case GPT_CLK:
216 status = omap_dm_timer_start(timer[clk_id - 1]);
217 break;
218#ifdef CONFIG_OMAP_MCBSP
219 case MCBSP_CLK:
220 omap_mcbsp_request(MCBSP_ID(clk_id));
221 omap2_mcbsp_set_clks_src(MCBSP_ID(clk_id), MCBSP_CLKS_PAD_SRC);
222 break;
223#endif
224 case WDT_CLK:
225 dev_err(bridge, "ERROR: DSP requested to enable WDT3 clk\n");
226 break;
227 case SSI_CLK:
228 clk_enable(ssi.sst_fck);
229 clk_enable(ssi.ssr_fck);
230 clk_enable(ssi.ick);
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238
239 ssi_clk_prepare(true);
240 break;
241 default:
242 dev_err(bridge, "Invalid clock id for enable\n");
243 status = -EPERM;
244 }
245
246 if (!status)
247 set_dsp_clk_active(&dsp_clocks, clk_id);
248
249out:
250 return status;
251}
252
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258
259u32 dsp_clock_enable_all(u32 dsp_per_clocks)
260{
261 u32 clk_id;
262 u32 status = -EPERM;
263
264 for (clk_id = 0; clk_id < DSP_CLK_NOT_DEFINED; clk_id++) {
265 if (is_dsp_clk_active(dsp_per_clocks, clk_id))
266 status = dsp_clk_enable(clk_id);
267 }
268
269 return status;
270}
271
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276
277
278int dsp_clk_disable(enum dsp_clk_id clk_id)
279{
280 int status = 0;
281
282 if (!is_dsp_clk_active(dsp_clocks, clk_id)) {
283 dev_err(bridge, "ERR: clock id %d already disabled\n", clk_id);
284 goto out;
285 }
286
287 switch (get_clk_type(clk_id)) {
288 case IVA2_CLK:
289 clk_disable(iva2_clk);
290 break;
291 case GPT_CLK:
292 status = omap_dm_timer_stop(timer[clk_id - 1]);
293 break;
294#ifdef CONFIG_OMAP_MCBSP
295 case MCBSP_CLK:
296 omap2_mcbsp_set_clks_src(MCBSP_ID(clk_id), MCBSP_CLKS_PRCM_SRC);
297 omap_mcbsp_free(MCBSP_ID(clk_id));
298 break;
299#endif
300 case WDT_CLK:
301 dev_err(bridge, "ERROR: DSP requested to disable WDT3 clk\n");
302 break;
303 case SSI_CLK:
304 ssi_clk_prepare(false);
305 ssi_clk_prepare(false);
306 clk_disable(ssi.sst_fck);
307 clk_disable(ssi.ssr_fck);
308 clk_disable(ssi.ick);
309 break;
310 default:
311 dev_err(bridge, "Invalid clock id for disable\n");
312 status = -EPERM;
313 }
314
315 if (!status)
316 set_dsp_clk_inactive(&dsp_clocks, clk_id);
317
318out:
319 return status;
320}
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329
330u32 dsp_clock_disable_all(u32 dsp_per_clocks)
331{
332 u32 clk_id;
333 u32 status = -EPERM;
334
335 for (clk_id = 0; clk_id < DSP_CLK_NOT_DEFINED; clk_id++) {
336 if (is_dsp_clk_active(dsp_per_clocks, clk_id))
337 status = dsp_clk_disable(clk_id);
338 }
339
340 return status;
341}
342
343u32 dsp_clk_get_iva2_rate(void)
344{
345 u32 clk_speed_khz;
346
347 clk_speed_khz = clk_get_rate(iva2_clk);
348 clk_speed_khz /= 1000;
349 dev_dbg(bridge, "%s: clk speed Khz = %d\n", __func__, clk_speed_khz);
350
351 return clk_speed_khz;
352}
353
354void ssi_clk_prepare(bool FLAG)
355{
356 void __iomem *ssi_base;
357 unsigned int value;
358
359 ssi_base = ioremap(L4_34XX_BASE + OMAP_SSI_OFFSET, OMAP_SSI_SIZE);
360 if (!ssi_base) {
361 pr_err("%s: error, SSI not configured\n", __func__);
362 return;
363 }
364
365 if (FLAG) {
366
367
368
369 value = SSI_AUTOIDLE | SSI_SIDLE_SMARTIDLE | SSI_MIDLE_NOIDLE;
370 } else {
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373
374 value = SSI_AUTOIDLE;
375 }
376
377 __raw_writel(value, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);
378 iounmap(ssi_base);
379}
380
381