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23#ifndef __SOUND_ASOUND_H
24#define __SOUND_ASOUND_H
25
26#include <linux/types.h>
27
28#ifdef __KERNEL__
29#include <linux/ioctl.h>
30#include <linux/time.h>
31#include <asm/byteorder.h>
32
33#ifdef __LITTLE_ENDIAN
34#define SNDRV_LITTLE_ENDIAN
35#else
36#ifdef __BIG_ENDIAN
37#define SNDRV_BIG_ENDIAN
38#else
39#error "Unsupported endian..."
40#endif
41#endif
42
43#endif
44
45
46
47
48
49#define SNDRV_PROTOCOL_VERSION(major, minor, subminor) (((major)<<16)|((minor)<<8)|(subminor))
50#define SNDRV_PROTOCOL_MAJOR(version) (((version)>>16)&0xffff)
51#define SNDRV_PROTOCOL_MINOR(version) (((version)>>8)&0xff)
52#define SNDRV_PROTOCOL_MICRO(version) ((version)&0xff)
53#define SNDRV_PROTOCOL_INCOMPATIBLE(kversion, uversion) \
54 (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || \
55 (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && \
56 SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion)))
57
58
59
60
61
62
63
64struct snd_aes_iec958 {
65 unsigned char status[24];
66 unsigned char subcode[147];
67 unsigned char pad;
68 unsigned char dig_subframe[4];
69};
70
71
72
73
74
75
76
77struct snd_cea_861_aud_if {
78 unsigned char db1_ct_cc;
79 unsigned char db2_sf_ss;
80 unsigned char db3;
81 unsigned char db4_ca;
82 unsigned char db5_dminh_lsv;
83};
84
85
86
87
88
89
90
91#define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
92
93enum {
94 SNDRV_HWDEP_IFACE_OPL2 = 0,
95 SNDRV_HWDEP_IFACE_OPL3,
96 SNDRV_HWDEP_IFACE_OPL4,
97 SNDRV_HWDEP_IFACE_SB16CSP,
98 SNDRV_HWDEP_IFACE_EMU10K1,
99 SNDRV_HWDEP_IFACE_YSS225,
100 SNDRV_HWDEP_IFACE_ICS2115,
101 SNDRV_HWDEP_IFACE_SSCAPE,
102 SNDRV_HWDEP_IFACE_VX,
103 SNDRV_HWDEP_IFACE_MIXART,
104 SNDRV_HWDEP_IFACE_USX2Y,
105 SNDRV_HWDEP_IFACE_EMUX_WAVETABLE,
106 SNDRV_HWDEP_IFACE_BLUETOOTH,
107 SNDRV_HWDEP_IFACE_USX2Y_PCM,
108 SNDRV_HWDEP_IFACE_PCXHR,
109 SNDRV_HWDEP_IFACE_SB_RC,
110 SNDRV_HWDEP_IFACE_HDA,
111 SNDRV_HWDEP_IFACE_USB_STREAM,
112
113
114 SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_USB_STREAM
115};
116
117struct snd_hwdep_info {
118 unsigned int device;
119 int card;
120 unsigned char id[64];
121 unsigned char name[80];
122 int iface;
123 unsigned char reserved[64];
124};
125
126
127struct snd_hwdep_dsp_status {
128 unsigned int version;
129 unsigned char id[32];
130 unsigned int num_dsps;
131 unsigned int dsp_loaded;
132 unsigned int chip_ready;
133 unsigned char reserved[16];
134};
135
136struct snd_hwdep_dsp_image {
137 unsigned int index;
138 unsigned char name[64];
139 unsigned char __user *image;
140 size_t length;
141 unsigned long driver_data;
142};
143
144#define SNDRV_HWDEP_IOCTL_PVERSION _IOR ('H', 0x00, int)
145#define SNDRV_HWDEP_IOCTL_INFO _IOR ('H', 0x01, struct snd_hwdep_info)
146#define SNDRV_HWDEP_IOCTL_DSP_STATUS _IOR('H', 0x02, struct snd_hwdep_dsp_status)
147#define SNDRV_HWDEP_IOCTL_DSP_LOAD _IOW('H', 0x03, struct snd_hwdep_dsp_image)
148
149
150
151
152
153
154
155#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 10)
156
157typedef unsigned long snd_pcm_uframes_t;
158typedef signed long snd_pcm_sframes_t;
159
160enum {
161 SNDRV_PCM_CLASS_GENERIC = 0,
162 SNDRV_PCM_CLASS_MULTI,
163 SNDRV_PCM_CLASS_MODEM,
164 SNDRV_PCM_CLASS_DIGITIZER,
165
166 SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER,
167};
168
169enum {
170 SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0,
171 SNDRV_PCM_SUBCLASS_MULTI_MIX,
172
173 SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX,
174};
175
176enum {
177 SNDRV_PCM_STREAM_PLAYBACK = 0,
178 SNDRV_PCM_STREAM_CAPTURE,
179 SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE,
180};
181
182typedef int __bitwise snd_pcm_access_t;
183#define SNDRV_PCM_ACCESS_MMAP_INTERLEAVED ((__force snd_pcm_access_t) 0)
184#define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED ((__force snd_pcm_access_t) 1)
185#define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((__force snd_pcm_access_t) 2)
186#define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((__force snd_pcm_access_t) 3)
187#define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED ((__force snd_pcm_access_t) 4)
188#define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED
189
190typedef int __bitwise snd_pcm_format_t;
191#define SNDRV_PCM_FORMAT_S8 ((__force snd_pcm_format_t) 0)
192#define SNDRV_PCM_FORMAT_U8 ((__force snd_pcm_format_t) 1)
193#define SNDRV_PCM_FORMAT_S16_LE ((__force snd_pcm_format_t) 2)
194#define SNDRV_PCM_FORMAT_S16_BE ((__force snd_pcm_format_t) 3)
195#define SNDRV_PCM_FORMAT_U16_LE ((__force snd_pcm_format_t) 4)
196#define SNDRV_PCM_FORMAT_U16_BE ((__force snd_pcm_format_t) 5)
197#define SNDRV_PCM_FORMAT_S24_LE ((__force snd_pcm_format_t) 6)
198#define SNDRV_PCM_FORMAT_S24_BE ((__force snd_pcm_format_t) 7)
199#define SNDRV_PCM_FORMAT_U24_LE ((__force snd_pcm_format_t) 8)
200#define SNDRV_PCM_FORMAT_U24_BE ((__force snd_pcm_format_t) 9)
201#define SNDRV_PCM_FORMAT_S32_LE ((__force snd_pcm_format_t) 10)
202#define SNDRV_PCM_FORMAT_S32_BE ((__force snd_pcm_format_t) 11)
203#define SNDRV_PCM_FORMAT_U32_LE ((__force snd_pcm_format_t) 12)
204#define SNDRV_PCM_FORMAT_U32_BE ((__force snd_pcm_format_t) 13)
205#define SNDRV_PCM_FORMAT_FLOAT_LE ((__force snd_pcm_format_t) 14)
206#define SNDRV_PCM_FORMAT_FLOAT_BE ((__force snd_pcm_format_t) 15)
207#define SNDRV_PCM_FORMAT_FLOAT64_LE ((__force snd_pcm_format_t) 16)
208#define SNDRV_PCM_FORMAT_FLOAT64_BE ((__force snd_pcm_format_t) 17)
209#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE ((__force snd_pcm_format_t) 18)
210#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE ((__force snd_pcm_format_t) 19)
211#define SNDRV_PCM_FORMAT_MU_LAW ((__force snd_pcm_format_t) 20)
212#define SNDRV_PCM_FORMAT_A_LAW ((__force snd_pcm_format_t) 21)
213#define SNDRV_PCM_FORMAT_IMA_ADPCM ((__force snd_pcm_format_t) 22)
214#define SNDRV_PCM_FORMAT_MPEG ((__force snd_pcm_format_t) 23)
215#define SNDRV_PCM_FORMAT_GSM ((__force snd_pcm_format_t) 24)
216#define SNDRV_PCM_FORMAT_SPECIAL ((__force snd_pcm_format_t) 31)
217#define SNDRV_PCM_FORMAT_S24_3LE ((__force snd_pcm_format_t) 32)
218#define SNDRV_PCM_FORMAT_S24_3BE ((__force snd_pcm_format_t) 33)
219#define SNDRV_PCM_FORMAT_U24_3LE ((__force snd_pcm_format_t) 34)
220#define SNDRV_PCM_FORMAT_U24_3BE ((__force snd_pcm_format_t) 35)
221#define SNDRV_PCM_FORMAT_S20_3LE ((__force snd_pcm_format_t) 36)
222#define SNDRV_PCM_FORMAT_S20_3BE ((__force snd_pcm_format_t) 37)
223#define SNDRV_PCM_FORMAT_U20_3LE ((__force snd_pcm_format_t) 38)
224#define SNDRV_PCM_FORMAT_U20_3BE ((__force snd_pcm_format_t) 39)
225#define SNDRV_PCM_FORMAT_S18_3LE ((__force snd_pcm_format_t) 40)
226#define SNDRV_PCM_FORMAT_S18_3BE ((__force snd_pcm_format_t) 41)
227#define SNDRV_PCM_FORMAT_U18_3LE ((__force snd_pcm_format_t) 42)
228#define SNDRV_PCM_FORMAT_U18_3BE ((__force snd_pcm_format_t) 43)
229#define SNDRV_PCM_FORMAT_G723_24 ((__force snd_pcm_format_t) 44)
230#define SNDRV_PCM_FORMAT_G723_24_1B ((__force snd_pcm_format_t) 45)
231#define SNDRV_PCM_FORMAT_G723_40 ((__force snd_pcm_format_t) 46)
232#define SNDRV_PCM_FORMAT_G723_40_1B ((__force snd_pcm_format_t) 47)
233#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_G723_40_1B
234
235#ifdef SNDRV_LITTLE_ENDIAN
236#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE
237#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_LE
238#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_LE
239#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_LE
240#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_LE
241#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_LE
242#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE
243#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE
244#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE
245#endif
246#ifdef SNDRV_BIG_ENDIAN
247#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE
248#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_BE
249#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_BE
250#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_BE
251#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_BE
252#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_BE
253#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE
254#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE
255#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE
256#endif
257
258typedef int __bitwise snd_pcm_subformat_t;
259#define SNDRV_PCM_SUBFORMAT_STD ((__force snd_pcm_subformat_t) 0)
260#define SNDRV_PCM_SUBFORMAT_LAST SNDRV_PCM_SUBFORMAT_STD
261
262#define SNDRV_PCM_INFO_MMAP 0x00000001
263#define SNDRV_PCM_INFO_MMAP_VALID 0x00000002
264#define SNDRV_PCM_INFO_DOUBLE 0x00000004
265#define SNDRV_PCM_INFO_BATCH 0x00000010
266#define SNDRV_PCM_INFO_INTERLEAVED 0x00000100
267#define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200
268#define SNDRV_PCM_INFO_COMPLEX 0x00000400
269#define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000
270#define SNDRV_PCM_INFO_OVERRANGE 0x00020000
271#define SNDRV_PCM_INFO_RESUME 0x00040000
272#define SNDRV_PCM_INFO_PAUSE 0x00080000
273#define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000
274#define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000
275#define SNDRV_PCM_INFO_SYNC_START 0x00400000
276#define SNDRV_PCM_INFO_NO_PERIOD_WAKEUP 0x00800000
277#define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000
278
279typedef int __bitwise snd_pcm_state_t;
280#define SNDRV_PCM_STATE_OPEN ((__force snd_pcm_state_t) 0)
281#define SNDRV_PCM_STATE_SETUP ((__force snd_pcm_state_t) 1)
282#define SNDRV_PCM_STATE_PREPARED ((__force snd_pcm_state_t) 2)
283#define SNDRV_PCM_STATE_RUNNING ((__force snd_pcm_state_t) 3)
284#define SNDRV_PCM_STATE_XRUN ((__force snd_pcm_state_t) 4)
285#define SNDRV_PCM_STATE_DRAINING ((__force snd_pcm_state_t) 5)
286#define SNDRV_PCM_STATE_PAUSED ((__force snd_pcm_state_t) 6)
287#define SNDRV_PCM_STATE_SUSPENDED ((__force snd_pcm_state_t) 7)
288#define SNDRV_PCM_STATE_DISCONNECTED ((__force snd_pcm_state_t) 8)
289#define SNDRV_PCM_STATE_LAST SNDRV_PCM_STATE_DISCONNECTED
290
291enum {
292 SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000,
293 SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000,
294 SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000,
295};
296
297union snd_pcm_sync_id {
298 unsigned char id[16];
299 unsigned short id16[8];
300 unsigned int id32[4];
301};
302
303struct snd_pcm_info {
304 unsigned int device;
305 unsigned int subdevice;
306 int stream;
307 int card;
308 unsigned char id[64];
309 unsigned char name[80];
310 unsigned char subname[32];
311 int dev_class;
312 int dev_subclass;
313 unsigned int subdevices_count;
314 unsigned int subdevices_avail;
315 union snd_pcm_sync_id sync;
316 unsigned char reserved[64];
317};
318
319typedef int snd_pcm_hw_param_t;
320#define SNDRV_PCM_HW_PARAM_ACCESS 0
321#define SNDRV_PCM_HW_PARAM_FORMAT 1
322#define SNDRV_PCM_HW_PARAM_SUBFORMAT 2
323#define SNDRV_PCM_HW_PARAM_FIRST_MASK SNDRV_PCM_HW_PARAM_ACCESS
324#define SNDRV_PCM_HW_PARAM_LAST_MASK SNDRV_PCM_HW_PARAM_SUBFORMAT
325
326#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS 8
327#define SNDRV_PCM_HW_PARAM_FRAME_BITS 9
328#define SNDRV_PCM_HW_PARAM_CHANNELS 10
329#define SNDRV_PCM_HW_PARAM_RATE 11
330#define SNDRV_PCM_HW_PARAM_PERIOD_TIME 12
331
332
333#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE 13
334
335
336#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES 14
337
338
339#define SNDRV_PCM_HW_PARAM_PERIODS 15
340
341
342#define SNDRV_PCM_HW_PARAM_BUFFER_TIME 16
343
344
345#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE 17
346#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES 18
347#define SNDRV_PCM_HW_PARAM_TICK_TIME 19
348#define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL SNDRV_PCM_HW_PARAM_SAMPLE_BITS
349#define SNDRV_PCM_HW_PARAM_LAST_INTERVAL SNDRV_PCM_HW_PARAM_TICK_TIME
350
351#define SNDRV_PCM_HW_PARAMS_NORESAMPLE (1<<0)
352#define SNDRV_PCM_HW_PARAMS_EXPORT_BUFFER (1<<1)
353#define SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP (1<<2)
354
355struct snd_interval {
356 unsigned int min, max;
357 unsigned int openmin:1,
358 openmax:1,
359 integer:1,
360 empty:1;
361};
362
363#define SNDRV_MASK_MAX 256
364
365struct snd_mask {
366 __u32 bits[(SNDRV_MASK_MAX+31)/32];
367};
368
369struct snd_pcm_hw_params {
370 unsigned int flags;
371 struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK -
372 SNDRV_PCM_HW_PARAM_FIRST_MASK + 1];
373 struct snd_mask mres[5];
374 struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL -
375 SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1];
376 struct snd_interval ires[9];
377 unsigned int rmask;
378 unsigned int cmask;
379 unsigned int info;
380 unsigned int msbits;
381 unsigned int rate_num;
382 unsigned int rate_den;
383 snd_pcm_uframes_t fifo_size;
384 unsigned char reserved[64];
385};
386
387enum {
388 SNDRV_PCM_TSTAMP_NONE = 0,
389 SNDRV_PCM_TSTAMP_ENABLE,
390 SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_ENABLE,
391};
392
393struct snd_pcm_sw_params {
394 int tstamp_mode;
395 unsigned int period_step;
396 unsigned int sleep_min;
397 snd_pcm_uframes_t avail_min;
398 snd_pcm_uframes_t xfer_align;
399 snd_pcm_uframes_t start_threshold;
400 snd_pcm_uframes_t stop_threshold;
401 snd_pcm_uframes_t silence_threshold;
402 snd_pcm_uframes_t silence_size;
403 snd_pcm_uframes_t boundary;
404 unsigned char reserved[64];
405};
406
407struct snd_pcm_channel_info {
408 unsigned int channel;
409 __kernel_off_t offset;
410 unsigned int first;
411 unsigned int step;
412};
413
414struct snd_pcm_status {
415 snd_pcm_state_t state;
416 struct timespec trigger_tstamp;
417 struct timespec tstamp;
418 snd_pcm_uframes_t appl_ptr;
419 snd_pcm_uframes_t hw_ptr;
420 snd_pcm_sframes_t delay;
421 snd_pcm_uframes_t avail;
422 snd_pcm_uframes_t avail_max;
423 snd_pcm_uframes_t overrange;
424 snd_pcm_state_t suspended_state;
425 unsigned char reserved[60];
426};
427
428struct snd_pcm_mmap_status {
429 snd_pcm_state_t state;
430 int pad1;
431 snd_pcm_uframes_t hw_ptr;
432 struct timespec tstamp;
433 snd_pcm_state_t suspended_state;
434};
435
436struct snd_pcm_mmap_control {
437 snd_pcm_uframes_t appl_ptr;
438 snd_pcm_uframes_t avail_min;
439};
440
441#define SNDRV_PCM_SYNC_PTR_HWSYNC (1<<0)
442#define SNDRV_PCM_SYNC_PTR_APPL (1<<1)
443#define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2)
444
445struct snd_pcm_sync_ptr {
446 unsigned int flags;
447 union {
448 struct snd_pcm_mmap_status status;
449 unsigned char reserved[64];
450 } s;
451 union {
452 struct snd_pcm_mmap_control control;
453 unsigned char reserved[64];
454 } c;
455};
456
457struct snd_xferi {
458 snd_pcm_sframes_t result;
459 void __user *buf;
460 snd_pcm_uframes_t frames;
461};
462
463struct snd_xfern {
464 snd_pcm_sframes_t result;
465 void __user * __user *bufs;
466 snd_pcm_uframes_t frames;
467};
468
469enum {
470 SNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0,
471 SNDRV_PCM_TSTAMP_TYPE_MONOTONIC,
472 SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC,
473};
474
475
476enum {
477 SNDRV_CHMAP_UNKNOWN = 0,
478 SNDRV_CHMAP_NA,
479 SNDRV_CHMAP_MONO,
480
481 SNDRV_CHMAP_FL,
482 SNDRV_CHMAP_FR,
483 SNDRV_CHMAP_RL,
484 SNDRV_CHMAP_RR,
485 SNDRV_CHMAP_FC,
486 SNDRV_CHMAP_LFE,
487 SNDRV_CHMAP_SL,
488 SNDRV_CHMAP_SR,
489 SNDRV_CHMAP_RC,
490
491 SNDRV_CHMAP_FLC,
492 SNDRV_CHMAP_FRC,
493 SNDRV_CHMAP_RLC,
494 SNDRV_CHMAP_RRC,
495 SNDRV_CHMAP_FLW,
496 SNDRV_CHMAP_FRW,
497 SNDRV_CHMAP_FLH,
498 SNDRV_CHMAP_FCH,
499 SNDRV_CHMAP_FRH,
500 SNDRV_CHMAP_TC,
501 SNDRV_CHMAP_TFL,
502 SNDRV_CHMAP_TFR,
503 SNDRV_CHMAP_TFC,
504 SNDRV_CHMAP_TRL,
505 SNDRV_CHMAP_TRR,
506 SNDRV_CHMAP_TRC,
507 SNDRV_CHMAP_LAST = SNDRV_CHMAP_TRC,
508};
509
510#define SNDRV_CHMAP_POSITION_MASK 0xffff
511#define SNDRV_CHMAP_PHASE_INVERSE (0x01 << 16)
512#define SNDRV_CHMAP_DRIVER_SPEC (0x02 << 16)
513
514#define SNDRV_PCM_IOCTL_PVERSION _IOR('A', 0x00, int)
515#define SNDRV_PCM_IOCTL_INFO _IOR('A', 0x01, struct snd_pcm_info)
516#define SNDRV_PCM_IOCTL_TSTAMP _IOW('A', 0x02, int)
517#define SNDRV_PCM_IOCTL_TTSTAMP _IOW('A', 0x03, int)
518#define SNDRV_PCM_IOCTL_HW_REFINE _IOWR('A', 0x10, struct snd_pcm_hw_params)
519#define SNDRV_PCM_IOCTL_HW_PARAMS _IOWR('A', 0x11, struct snd_pcm_hw_params)
520#define SNDRV_PCM_IOCTL_HW_FREE _IO('A', 0x12)
521#define SNDRV_PCM_IOCTL_SW_PARAMS _IOWR('A', 0x13, struct snd_pcm_sw_params)
522#define SNDRV_PCM_IOCTL_STATUS _IOR('A', 0x20, struct snd_pcm_status)
523#define SNDRV_PCM_IOCTL_DELAY _IOR('A', 0x21, snd_pcm_sframes_t)
524#define SNDRV_PCM_IOCTL_HWSYNC _IO('A', 0x22)
525#define SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct snd_pcm_sync_ptr)
526#define SNDRV_PCM_IOCTL_CHANNEL_INFO _IOR('A', 0x32, struct snd_pcm_channel_info)
527#define SNDRV_PCM_IOCTL_PREPARE _IO('A', 0x40)
528#define SNDRV_PCM_IOCTL_RESET _IO('A', 0x41)
529#define SNDRV_PCM_IOCTL_START _IO('A', 0x42)
530#define SNDRV_PCM_IOCTL_DROP _IO('A', 0x43)
531#define SNDRV_PCM_IOCTL_DRAIN _IO('A', 0x44)
532#define SNDRV_PCM_IOCTL_PAUSE _IOW('A', 0x45, int)
533#define SNDRV_PCM_IOCTL_REWIND _IOW('A', 0x46, snd_pcm_uframes_t)
534#define SNDRV_PCM_IOCTL_RESUME _IO('A', 0x47)
535#define SNDRV_PCM_IOCTL_XRUN _IO('A', 0x48)
536#define SNDRV_PCM_IOCTL_FORWARD _IOW('A', 0x49, snd_pcm_uframes_t)
537#define SNDRV_PCM_IOCTL_WRITEI_FRAMES _IOW('A', 0x50, struct snd_xferi)
538#define SNDRV_PCM_IOCTL_READI_FRAMES _IOR('A', 0x51, struct snd_xferi)
539#define SNDRV_PCM_IOCTL_WRITEN_FRAMES _IOW('A', 0x52, struct snd_xfern)
540#define SNDRV_PCM_IOCTL_READN_FRAMES _IOR('A', 0x53, struct snd_xfern)
541#define SNDRV_PCM_IOCTL_LINK _IOW('A', 0x60, int)
542#define SNDRV_PCM_IOCTL_UNLINK _IO('A', 0x61)
543
544
545
546
547
548
549
550
551
552
553
554#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0)
555
556enum {
557 SNDRV_RAWMIDI_STREAM_OUTPUT = 0,
558 SNDRV_RAWMIDI_STREAM_INPUT,
559 SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT,
560};
561
562#define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001
563#define SNDRV_RAWMIDI_INFO_INPUT 0x00000002
564#define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004
565
566struct snd_rawmidi_info {
567 unsigned int device;
568 unsigned int subdevice;
569 int stream;
570 int card;
571 unsigned int flags;
572 unsigned char id[64];
573 unsigned char name[80];
574 unsigned char subname[32];
575 unsigned int subdevices_count;
576 unsigned int subdevices_avail;
577 unsigned char reserved[64];
578};
579
580struct snd_rawmidi_params {
581 int stream;
582 size_t buffer_size;
583 size_t avail_min;
584 unsigned int no_active_sensing: 1;
585 unsigned char reserved[16];
586};
587
588struct snd_rawmidi_status {
589 int stream;
590 struct timespec tstamp;
591 size_t avail;
592 size_t xruns;
593 unsigned char reserved[16];
594};
595
596#define SNDRV_RAWMIDI_IOCTL_PVERSION _IOR('W', 0x00, int)
597#define SNDRV_RAWMIDI_IOCTL_INFO _IOR('W', 0x01, struct snd_rawmidi_info)
598#define SNDRV_RAWMIDI_IOCTL_PARAMS _IOWR('W', 0x10, struct snd_rawmidi_params)
599#define SNDRV_RAWMIDI_IOCTL_STATUS _IOWR('W', 0x20, struct snd_rawmidi_status)
600#define SNDRV_RAWMIDI_IOCTL_DROP _IOW('W', 0x30, int)
601#define SNDRV_RAWMIDI_IOCTL_DRAIN _IOW('W', 0x31, int)
602
603
604
605
606
607#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 6)
608
609enum {
610 SNDRV_TIMER_CLASS_NONE = -1,
611 SNDRV_TIMER_CLASS_SLAVE = 0,
612 SNDRV_TIMER_CLASS_GLOBAL,
613 SNDRV_TIMER_CLASS_CARD,
614 SNDRV_TIMER_CLASS_PCM,
615 SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM,
616};
617
618
619enum {
620 SNDRV_TIMER_SCLASS_NONE = 0,
621 SNDRV_TIMER_SCLASS_APPLICATION,
622 SNDRV_TIMER_SCLASS_SEQUENCER,
623 SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
624 SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
625};
626
627
628#define SNDRV_TIMER_GLOBAL_SYSTEM 0
629#define SNDRV_TIMER_GLOBAL_RTC 1
630#define SNDRV_TIMER_GLOBAL_HPET 2
631#define SNDRV_TIMER_GLOBAL_HRTIMER 3
632
633
634#define SNDRV_TIMER_FLG_SLAVE (1<<0)
635
636struct snd_timer_id {
637 int dev_class;
638 int dev_sclass;
639 int card;
640 int device;
641 int subdevice;
642};
643
644struct snd_timer_ginfo {
645 struct snd_timer_id tid;
646 unsigned int flags;
647 int card;
648 unsigned char id[64];
649 unsigned char name[80];
650 unsigned long reserved0;
651 unsigned long resolution;
652 unsigned long resolution_min;
653 unsigned long resolution_max;
654 unsigned int clients;
655 unsigned char reserved[32];
656};
657
658struct snd_timer_gparams {
659 struct snd_timer_id tid;
660 unsigned long period_num;
661 unsigned long period_den;
662 unsigned char reserved[32];
663};
664
665struct snd_timer_gstatus {
666 struct snd_timer_id tid;
667 unsigned long resolution;
668 unsigned long resolution_num;
669 unsigned long resolution_den;
670 unsigned char reserved[32];
671};
672
673struct snd_timer_select {
674 struct snd_timer_id id;
675 unsigned char reserved[32];
676};
677
678struct snd_timer_info {
679 unsigned int flags;
680 int card;
681 unsigned char id[64];
682 unsigned char name[80];
683 unsigned long reserved0;
684 unsigned long resolution;
685 unsigned char reserved[64];
686};
687
688#define SNDRV_TIMER_PSFLG_AUTO (1<<0)
689#define SNDRV_TIMER_PSFLG_EXCLUSIVE (1<<1)
690#define SNDRV_TIMER_PSFLG_EARLY_EVENT (1<<2)
691
692struct snd_timer_params {
693 unsigned int flags;
694 unsigned int ticks;
695 unsigned int queue_size;
696 unsigned int reserved0;
697 unsigned int filter;
698 unsigned char reserved[60];
699};
700
701struct snd_timer_status {
702 struct timespec tstamp;
703 unsigned int resolution;
704 unsigned int lost;
705 unsigned int overrun;
706 unsigned int queue;
707 unsigned char reserved[64];
708};
709
710#define SNDRV_TIMER_IOCTL_PVERSION _IOR('T', 0x00, int)
711#define SNDRV_TIMER_IOCTL_NEXT_DEVICE _IOWR('T', 0x01, struct snd_timer_id)
712#define SNDRV_TIMER_IOCTL_TREAD _IOW('T', 0x02, int)
713#define SNDRV_TIMER_IOCTL_GINFO _IOWR('T', 0x03, struct snd_timer_ginfo)
714#define SNDRV_TIMER_IOCTL_GPARAMS _IOW('T', 0x04, struct snd_timer_gparams)
715#define SNDRV_TIMER_IOCTL_GSTATUS _IOWR('T', 0x05, struct snd_timer_gstatus)
716#define SNDRV_TIMER_IOCTL_SELECT _IOW('T', 0x10, struct snd_timer_select)
717#define SNDRV_TIMER_IOCTL_INFO _IOR('T', 0x11, struct snd_timer_info)
718#define SNDRV_TIMER_IOCTL_PARAMS _IOW('T', 0x12, struct snd_timer_params)
719#define SNDRV_TIMER_IOCTL_STATUS _IOR('T', 0x14, struct snd_timer_status)
720
721#define SNDRV_TIMER_IOCTL_START _IO('T', 0xa0)
722#define SNDRV_TIMER_IOCTL_STOP _IO('T', 0xa1)
723#define SNDRV_TIMER_IOCTL_CONTINUE _IO('T', 0xa2)
724#define SNDRV_TIMER_IOCTL_PAUSE _IO('T', 0xa3)
725
726struct snd_timer_read {
727 unsigned int resolution;
728 unsigned int ticks;
729};
730
731enum {
732 SNDRV_TIMER_EVENT_RESOLUTION = 0,
733 SNDRV_TIMER_EVENT_TICK,
734 SNDRV_TIMER_EVENT_START,
735 SNDRV_TIMER_EVENT_STOP,
736 SNDRV_TIMER_EVENT_CONTINUE,
737 SNDRV_TIMER_EVENT_PAUSE,
738 SNDRV_TIMER_EVENT_EARLY,
739 SNDRV_TIMER_EVENT_SUSPEND,
740 SNDRV_TIMER_EVENT_RESUME,
741
742 SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10,
743 SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10,
744 SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10,
745 SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10,
746 SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10,
747 SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10,
748};
749
750struct snd_timer_tread {
751 int event;
752 struct timespec tstamp;
753 unsigned int val;
754};
755
756
757
758
759
760
761
762#define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7)
763
764struct snd_ctl_card_info {
765 int card;
766 int pad;
767 unsigned char id[16];
768 unsigned char driver[16];
769 unsigned char name[32];
770 unsigned char longname[80];
771 unsigned char reserved_[16];
772 unsigned char mixername[80];
773 unsigned char components[128];
774};
775
776typedef int __bitwise snd_ctl_elem_type_t;
777#define SNDRV_CTL_ELEM_TYPE_NONE ((__force snd_ctl_elem_type_t) 0)
778#define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((__force snd_ctl_elem_type_t) 1)
779#define SNDRV_CTL_ELEM_TYPE_INTEGER ((__force snd_ctl_elem_type_t) 2)
780#define SNDRV_CTL_ELEM_TYPE_ENUMERATED ((__force snd_ctl_elem_type_t) 3)
781#define SNDRV_CTL_ELEM_TYPE_BYTES ((__force snd_ctl_elem_type_t) 4)
782#define SNDRV_CTL_ELEM_TYPE_IEC958 ((__force snd_ctl_elem_type_t) 5)
783#define SNDRV_CTL_ELEM_TYPE_INTEGER64 ((__force snd_ctl_elem_type_t) 6)
784#define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64
785
786typedef int __bitwise snd_ctl_elem_iface_t;
787#define SNDRV_CTL_ELEM_IFACE_CARD ((__force snd_ctl_elem_iface_t) 0)
788#define SNDRV_CTL_ELEM_IFACE_HWDEP ((__force snd_ctl_elem_iface_t) 1)
789#define SNDRV_CTL_ELEM_IFACE_MIXER ((__force snd_ctl_elem_iface_t) 2)
790#define SNDRV_CTL_ELEM_IFACE_PCM ((__force snd_ctl_elem_iface_t) 3)
791#define SNDRV_CTL_ELEM_IFACE_RAWMIDI ((__force snd_ctl_elem_iface_t) 4)
792#define SNDRV_CTL_ELEM_IFACE_TIMER ((__force snd_ctl_elem_iface_t) 5)
793#define SNDRV_CTL_ELEM_IFACE_SEQUENCER ((__force snd_ctl_elem_iface_t) 6)
794#define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER
795
796#define SNDRV_CTL_ELEM_ACCESS_READ (1<<0)
797#define SNDRV_CTL_ELEM_ACCESS_WRITE (1<<1)
798#define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE)
799#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2)
800#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1<<3)
801#define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1<<4)
802#define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1<<5)
803#define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ|SNDRV_CTL_ELEM_ACCESS_TLV_WRITE)
804#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1<<6)
805#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1<<8)
806#define SNDRV_CTL_ELEM_ACCESS_LOCK (1<<9)
807#define SNDRV_CTL_ELEM_ACCESS_OWNER (1<<10)
808#define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1<<28)
809#define SNDRV_CTL_ELEM_ACCESS_USER (1<<29)
810
811
812
813#define SNDRV_CTL_POWER_D0 0x0000
814#define SNDRV_CTL_POWER_D1 0x0100
815#define SNDRV_CTL_POWER_D2 0x0200
816#define SNDRV_CTL_POWER_D3 0x0300
817#define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3|0x0000)
818#define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3|0x0001)
819
820struct snd_ctl_elem_id {
821 unsigned int numid;
822 snd_ctl_elem_iface_t iface;
823 unsigned int device;
824 unsigned int subdevice;
825 unsigned char name[44];
826 unsigned int index;
827};
828
829struct snd_ctl_elem_list {
830 unsigned int offset;
831 unsigned int space;
832 unsigned int used;
833 unsigned int count;
834 struct snd_ctl_elem_id __user *pids;
835 unsigned char reserved[50];
836};
837
838struct snd_ctl_elem_info {
839 struct snd_ctl_elem_id id;
840 snd_ctl_elem_type_t type;
841 unsigned int access;
842 unsigned int count;
843 __kernel_pid_t owner;
844 union {
845 struct {
846 long min;
847 long max;
848 long step;
849 } integer;
850 struct {
851 long long min;
852 long long max;
853 long long step;
854 } integer64;
855 struct {
856 unsigned int items;
857 unsigned int item;
858 char name[64];
859 __u64 names_ptr;
860 unsigned int names_length;
861 } enumerated;
862 unsigned char reserved[128];
863 } value;
864 union {
865 unsigned short d[4];
866 unsigned short *d_ptr;
867 } dimen;
868 unsigned char reserved[64-4*sizeof(unsigned short)];
869};
870
871struct snd_ctl_elem_value {
872 struct snd_ctl_elem_id id;
873 unsigned int indirect: 1;
874 union {
875 union {
876 long value[128];
877 long *value_ptr;
878 } integer;
879 union {
880 long long value[64];
881 long long *value_ptr;
882 } integer64;
883 union {
884 unsigned int item[128];
885 unsigned int *item_ptr;
886 } enumerated;
887 union {
888 unsigned char data[512];
889 unsigned char *data_ptr;
890 } bytes;
891 struct snd_aes_iec958 iec958;
892 } value;
893 struct timespec tstamp;
894 unsigned char reserved[128-sizeof(struct timespec)];
895};
896
897struct snd_ctl_tlv {
898 unsigned int numid;
899 unsigned int length;
900 unsigned int tlv[0];
901};
902
903#define SNDRV_CTL_IOCTL_PVERSION _IOR('U', 0x00, int)
904#define SNDRV_CTL_IOCTL_CARD_INFO _IOR('U', 0x01, struct snd_ctl_card_info)
905#define SNDRV_CTL_IOCTL_ELEM_LIST _IOWR('U', 0x10, struct snd_ctl_elem_list)
906#define SNDRV_CTL_IOCTL_ELEM_INFO _IOWR('U', 0x11, struct snd_ctl_elem_info)
907#define SNDRV_CTL_IOCTL_ELEM_READ _IOWR('U', 0x12, struct snd_ctl_elem_value)
908#define SNDRV_CTL_IOCTL_ELEM_WRITE _IOWR('U', 0x13, struct snd_ctl_elem_value)
909#define SNDRV_CTL_IOCTL_ELEM_LOCK _IOW('U', 0x14, struct snd_ctl_elem_id)
910#define SNDRV_CTL_IOCTL_ELEM_UNLOCK _IOW('U', 0x15, struct snd_ctl_elem_id)
911#define SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS _IOWR('U', 0x16, int)
912#define SNDRV_CTL_IOCTL_ELEM_ADD _IOWR('U', 0x17, struct snd_ctl_elem_info)
913#define SNDRV_CTL_IOCTL_ELEM_REPLACE _IOWR('U', 0x18, struct snd_ctl_elem_info)
914#define SNDRV_CTL_IOCTL_ELEM_REMOVE _IOWR('U', 0x19, struct snd_ctl_elem_id)
915#define SNDRV_CTL_IOCTL_TLV_READ _IOWR('U', 0x1a, struct snd_ctl_tlv)
916#define SNDRV_CTL_IOCTL_TLV_WRITE _IOWR('U', 0x1b, struct snd_ctl_tlv)
917#define SNDRV_CTL_IOCTL_TLV_COMMAND _IOWR('U', 0x1c, struct snd_ctl_tlv)
918#define SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE _IOWR('U', 0x20, int)
919#define SNDRV_CTL_IOCTL_HWDEP_INFO _IOR('U', 0x21, struct snd_hwdep_info)
920#define SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE _IOR('U', 0x30, int)
921#define SNDRV_CTL_IOCTL_PCM_INFO _IOWR('U', 0x31, struct snd_pcm_info)
922#define SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE _IOW('U', 0x32, int)
923#define SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE _IOWR('U', 0x40, int)
924#define SNDRV_CTL_IOCTL_RAWMIDI_INFO _IOWR('U', 0x41, struct snd_rawmidi_info)
925#define SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE _IOW('U', 0x42, int)
926#define SNDRV_CTL_IOCTL_POWER _IOWR('U', 0xd0, int)
927#define SNDRV_CTL_IOCTL_POWER_STATE _IOR('U', 0xd1, int)
928
929
930
931
932
933enum sndrv_ctl_event_type {
934 SNDRV_CTL_EVENT_ELEM = 0,
935 SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM,
936};
937
938#define SNDRV_CTL_EVENT_MASK_VALUE (1<<0)
939#define SNDRV_CTL_EVENT_MASK_INFO (1<<1)
940#define SNDRV_CTL_EVENT_MASK_ADD (1<<2)
941#define SNDRV_CTL_EVENT_MASK_TLV (1<<3)
942#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U)
943
944struct snd_ctl_event {
945 int type;
946 union {
947 struct {
948 unsigned int mask;
949 struct snd_ctl_elem_id id;
950 } elem;
951 unsigned char data8[60];
952 } data;
953};
954
955
956
957
958
959#define SNDRV_CTL_NAME_NONE ""
960#define SNDRV_CTL_NAME_PLAYBACK "Playback "
961#define SNDRV_CTL_NAME_CAPTURE "Capture "
962
963#define SNDRV_CTL_NAME_IEC958_NONE ""
964#define SNDRV_CTL_NAME_IEC958_SWITCH "Switch"
965#define SNDRV_CTL_NAME_IEC958_VOLUME "Volume"
966#define SNDRV_CTL_NAME_IEC958_DEFAULT "Default"
967#define SNDRV_CTL_NAME_IEC958_MASK "Mask"
968#define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask"
969#define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask"
970#define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream"
971#define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_##direction SNDRV_CTL_NAME_IEC958_##what
972
973#endif
974