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13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/fs.h>
17#include <linux/debugfs.h>
18#include <linux/seq_file.h>
19#include <linux/list.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <linux/spinlock.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26#include <linux/of_address.h>
27
28#include <mach/hardware.h>
29#include <mach/at91_pmc.h>
30#include <mach/cpu.h>
31
32#include <asm/proc-fns.h>
33
34#include "clock.h"
35#include "generic.h"
36
37void __iomem *at91_pmc_base;
38EXPORT_SYMBOL_GPL(at91_pmc_base);
39
40
41
42
43
44
45
46#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
47#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
48#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
49#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
50
51
52
53
54
55#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
56 || cpu_is_at91sam9g45() \
57 || cpu_is_at91sam9x5())
58
59#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
60 || cpu_is_at91sam9g45() \
61 || cpu_is_at91sam9x5() \
62 || cpu_is_at91sam9n12())
63
64#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
65
66#define cpu_has_240M_plla() (cpu_is_at91sam9261() \
67 || cpu_is_at91sam9263() \
68 || cpu_is_at91sam9rl())
69
70#define cpu_has_210M_plla() (cpu_is_at91sam9260())
71
72#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
73 || cpu_is_at91sam9g45() \
74 || cpu_is_at91sam9x5() \
75 || cpu_is_at91sam9n12()))
76
77#define cpu_has_upll() (cpu_is_at91sam9g45() \
78 || cpu_is_at91sam9x5())
79
80
81#define cpu_has_uhp() (!cpu_is_at91sam9rl())
82
83
84#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
85 || cpu_is_at91sam9g45() \
86 || cpu_is_at91sam9x5()))
87
88#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
89 || cpu_is_at91sam9x5() \
90 || cpu_is_at91sam9n12())
91
92#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
93 || cpu_is_at91sam9x5() \
94 || cpu_is_at91sam9n12())
95
96#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
97 || cpu_is_at91sam9n12())
98
99static LIST_HEAD(clocks);
100static DEFINE_SPINLOCK(clk_lock);
101
102static u32 at91_pllb_usb_init;
103
104
105
106
107
108
109
110static struct clk clk32k = {
111 .name = "clk32k",
112 .rate_hz = AT91_SLOW_CLOCK,
113 .users = 1,
114 .id = 0,
115 .type = CLK_TYPE_PRIMARY,
116};
117static struct clk main_clk = {
118 .name = "main",
119 .pmc_mask = AT91_PMC_MOSCS,
120 .id = 1,
121 .type = CLK_TYPE_PRIMARY,
122};
123static struct clk plla = {
124 .name = "plla",
125 .parent = &main_clk,
126 .pmc_mask = AT91_PMC_LOCKA,
127 .id = 2,
128 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
129};
130
131static void pllb_mode(struct clk *clk, int is_on)
132{
133 u32 value;
134
135 if (is_on) {
136 is_on = AT91_PMC_LOCKB;
137 value = at91_pllb_usb_init;
138 } else
139 value = 0;
140
141
142 at91_pmc_write(AT91_CKGR_PLLBR, value);
143
144 do {
145 cpu_relax();
146 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
147}
148
149static struct clk pllb = {
150 .name = "pllb",
151 .parent = &main_clk,
152 .pmc_mask = AT91_PMC_LOCKB,
153 .mode = pllb_mode,
154 .id = 3,
155 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
156};
157
158static void pmc_sys_mode(struct clk *clk, int is_on)
159{
160 if (is_on)
161 at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
162 else
163 at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
164}
165
166static void pmc_uckr_mode(struct clk *clk, int is_on)
167{
168 unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
169
170 if (is_on) {
171 is_on = AT91_PMC_LOCKU;
172 at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
173 } else
174 at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
175
176 do {
177 cpu_relax();
178 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
179}
180
181
182static struct clk udpck = {
183 .name = "udpck",
184 .parent = &pllb,
185 .mode = pmc_sys_mode,
186};
187struct clk utmi_clk = {
188 .name = "utmi_clk",
189 .parent = &main_clk,
190 .pmc_mask = AT91_PMC_UPLLEN,
191 .mode = pmc_uckr_mode,
192 .type = CLK_TYPE_PLL,
193};
194static struct clk uhpck = {
195 .name = "uhpck",
196
197 .mode = pmc_sys_mode,
198};
199
200
201
202
203
204
205
206struct clk mck = {
207 .name = "mck",
208 .pmc_mask = AT91_PMC_MCKRDY,
209};
210
211static void pmc_periph_mode(struct clk *clk, int is_on)
212{
213 if (is_on)
214 at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
215 else
216 at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
217}
218
219static struct clk __init *at91_css_to_clk(unsigned long css)
220{
221 switch (css) {
222 case AT91_PMC_CSS_SLOW:
223 return &clk32k;
224 case AT91_PMC_CSS_MAIN:
225 return &main_clk;
226 case AT91_PMC_CSS_PLLA:
227 return &plla;
228 case AT91_PMC_CSS_PLLB:
229 if (cpu_has_upll())
230
231 return &utmi_clk;
232 else if (cpu_has_pllb())
233 return &pllb;
234 break;
235
236 case AT91_PMC_CSS_MASTER:
237 return &mck;
238 }
239
240 return NULL;
241}
242
243static int pmc_prescaler_divider(u32 reg)
244{
245 if (cpu_has_alt_prescaler()) {
246 return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
247 } else {
248 return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
249 }
250}
251
252static void __clk_enable(struct clk *clk)
253{
254 if (clk->parent)
255 __clk_enable(clk->parent);
256 if (clk->users++ == 0 && clk->mode)
257 clk->mode(clk, 1);
258}
259
260int clk_enable(struct clk *clk)
261{
262 unsigned long flags;
263
264 spin_lock_irqsave(&clk_lock, flags);
265 __clk_enable(clk);
266 spin_unlock_irqrestore(&clk_lock, flags);
267 return 0;
268}
269EXPORT_SYMBOL(clk_enable);
270
271static void __clk_disable(struct clk *clk)
272{
273 BUG_ON(clk->users == 0);
274 if (--clk->users == 0 && clk->mode)
275 clk->mode(clk, 0);
276 if (clk->parent)
277 __clk_disable(clk->parent);
278}
279
280void clk_disable(struct clk *clk)
281{
282 unsigned long flags;
283
284 spin_lock_irqsave(&clk_lock, flags);
285 __clk_disable(clk);
286 spin_unlock_irqrestore(&clk_lock, flags);
287}
288EXPORT_SYMBOL(clk_disable);
289
290unsigned long clk_get_rate(struct clk *clk)
291{
292 unsigned long flags;
293 unsigned long rate;
294
295 spin_lock_irqsave(&clk_lock, flags);
296 for (;;) {
297 rate = clk->rate_hz;
298 if (rate || !clk->parent)
299 break;
300 clk = clk->parent;
301 }
302 spin_unlock_irqrestore(&clk_lock, flags);
303 return rate;
304}
305EXPORT_SYMBOL(clk_get_rate);
306
307
308
309#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
310
311
312
313
314
315
316
317
318long clk_round_rate(struct clk *clk, unsigned long rate)
319{
320 unsigned long flags;
321 unsigned prescale;
322 unsigned long actual;
323 unsigned long prev = ULONG_MAX;
324
325 if (!clk_is_programmable(clk))
326 return -EINVAL;
327 spin_lock_irqsave(&clk_lock, flags);
328
329 actual = clk->parent->rate_hz;
330 for (prescale = 0; prescale < 7; prescale++) {
331 if (actual > rate)
332 prev = actual;
333
334 if (actual && actual <= rate) {
335 if ((prev - rate) < (rate - actual)) {
336 actual = prev;
337 prescale--;
338 }
339 break;
340 }
341 actual >>= 1;
342 }
343
344 spin_unlock_irqrestore(&clk_lock, flags);
345 return (prescale < 7) ? actual : -ENOENT;
346}
347EXPORT_SYMBOL(clk_round_rate);
348
349int clk_set_rate(struct clk *clk, unsigned long rate)
350{
351 unsigned long flags;
352 unsigned prescale;
353 unsigned long prescale_offset, css_mask;
354 unsigned long actual;
355
356 if (!clk_is_programmable(clk))
357 return -EINVAL;
358 if (clk->users)
359 return -EBUSY;
360
361 if (cpu_has_alt_prescaler()) {
362 prescale_offset = PMC_ALT_PRES_OFFSET;
363 css_mask = AT91_PMC_ALT_PCKR_CSS;
364 } else {
365 prescale_offset = PMC_PRES_OFFSET;
366 css_mask = AT91_PMC_CSS;
367 }
368
369 spin_lock_irqsave(&clk_lock, flags);
370
371 actual = clk->parent->rate_hz;
372 for (prescale = 0; prescale < 7; prescale++) {
373 if (actual && actual <= rate) {
374 u32 pckr;
375
376 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
377 pckr &= css_mask;
378 pckr |= prescale << prescale_offset;
379 at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
380 clk->rate_hz = actual;
381 break;
382 }
383 actual >>= 1;
384 }
385
386 spin_unlock_irqrestore(&clk_lock, flags);
387 return (prescale < 7) ? actual : -ENOENT;
388}
389EXPORT_SYMBOL(clk_set_rate);
390
391struct clk *clk_get_parent(struct clk *clk)
392{
393 return clk->parent;
394}
395EXPORT_SYMBOL(clk_get_parent);
396
397int clk_set_parent(struct clk *clk, struct clk *parent)
398{
399 unsigned long flags;
400
401 if (clk->users)
402 return -EBUSY;
403 if (!clk_is_primary(parent) || !clk_is_programmable(clk))
404 return -EINVAL;
405
406 if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
407 return -EINVAL;
408
409 spin_lock_irqsave(&clk_lock, flags);
410
411 clk->rate_hz = parent->rate_hz;
412 clk->parent = parent;
413 at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
414
415 spin_unlock_irqrestore(&clk_lock, flags);
416 return 0;
417}
418EXPORT_SYMBOL(clk_set_parent);
419
420
421static void __init init_programmable_clock(struct clk *clk)
422{
423 struct clk *parent;
424 u32 pckr;
425 unsigned int css_mask;
426
427 if (cpu_has_alt_prescaler())
428 css_mask = AT91_PMC_ALT_PCKR_CSS;
429 else
430 css_mask = AT91_PMC_CSS;
431
432 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
433 parent = at91_css_to_clk(pckr & css_mask);
434 clk->parent = parent;
435 clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
436}
437
438#endif
439
440
441
442#ifdef CONFIG_DEBUG_FS
443
444static int at91_clk_show(struct seq_file *s, void *unused)
445{
446 u32 scsr, pcsr, uckr = 0, sr;
447 struct clk *clk;
448
449 scsr = at91_pmc_read(AT91_PMC_SCSR);
450 pcsr = at91_pmc_read(AT91_PMC_PCSR);
451 sr = at91_pmc_read(AT91_PMC_SR);
452 seq_printf(s, "SCSR = %8x\n", scsr);
453 seq_printf(s, "PCSR = %8x\n", pcsr);
454 seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
455 seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
456 seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
457 if (cpu_has_pllb())
458 seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
459 if (cpu_has_utmi()) {
460 uckr = at91_pmc_read(AT91_CKGR_UCKR);
461 seq_printf(s, "UCKR = %8x\n", uckr);
462 }
463 seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
464 if (cpu_has_upll())
465 seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
466 seq_printf(s, "SR = %8x\n", sr);
467
468 seq_printf(s, "\n");
469
470 list_for_each_entry(clk, &clocks, node) {
471 char *state;
472
473 if (clk->mode == pmc_sys_mode)
474 state = (scsr & clk->pmc_mask) ? "on" : "off";
475 else if (clk->mode == pmc_periph_mode)
476 state = (pcsr & clk->pmc_mask) ? "on" : "off";
477 else if (clk->mode == pmc_uckr_mode)
478 state = (uckr & clk->pmc_mask) ? "on" : "off";
479 else if (clk->pmc_mask)
480 state = (sr & clk->pmc_mask) ? "on" : "off";
481 else if (clk == &clk32k || clk == &main_clk)
482 state = "on";
483 else
484 state = "";
485
486 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
487 clk->name, clk->users, state, clk_get_rate(clk),
488 clk->parent ? clk->parent->name : "");
489 }
490 return 0;
491}
492
493static int at91_clk_open(struct inode *inode, struct file *file)
494{
495 return single_open(file, at91_clk_show, NULL);
496}
497
498static const struct file_operations at91_clk_operations = {
499 .open = at91_clk_open,
500 .read = seq_read,
501 .llseek = seq_lseek,
502 .release = single_release,
503};
504
505static int __init at91_clk_debugfs_init(void)
506{
507
508 (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
509
510 return 0;
511}
512postcore_initcall(at91_clk_debugfs_init);
513
514#endif
515
516
517
518
519static void __init at91_clk_add(struct clk *clk)
520{
521 list_add_tail(&clk->node, &clocks);
522
523 clk->cl.con_id = clk->name;
524 clk->cl.clk = clk;
525 clkdev_add(&clk->cl);
526}
527
528int __init clk_register(struct clk *clk)
529{
530 if (clk_is_peripheral(clk)) {
531 if (!clk->parent)
532 clk->parent = &mck;
533 clk->mode = pmc_periph_mode;
534 }
535 else if (clk_is_sys(clk)) {
536 clk->parent = &mck;
537 clk->mode = pmc_sys_mode;
538 }
539#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
540 else if (clk_is_programmable(clk)) {
541 clk->mode = pmc_sys_mode;
542 init_programmable_clock(clk);
543 }
544#endif
545
546 at91_clk_add(clk);
547
548 return 0;
549}
550
551
552
553static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
554{
555 unsigned mul, div;
556
557 div = reg & 0xff;
558 mul = (reg >> 16) & 0x7ff;
559 if (div && mul) {
560 freq /= div;
561 freq *= mul + 1;
562 } else
563 freq = 0;
564
565 return freq;
566}
567
568static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
569{
570 if (pll == &pllb && (reg & AT91_PMC_USB96M))
571 return freq / 2;
572 else
573 return freq;
574}
575
576static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
577{
578 unsigned i, div = 0, mul = 0, diff = 1 << 30;
579 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
580
581
582 if (out_freq > 240000000)
583 goto fail;
584
585 for (i = 1; i < 256; i++) {
586 int diff1;
587 unsigned input, mul1;
588
589
590
591
592
593
594 input = main_freq / i;
595 if (cpu_is_at91sam9g20() && input < 2000000)
596 continue;
597 if (input < 100000)
598 continue;
599 if (input > 32000000)
600 continue;
601
602 mul1 = out_freq / input;
603 if (cpu_is_at91sam9g20() && mul > 63)
604 continue;
605 if (mul1 > 2048)
606 continue;
607 if (mul1 < 2)
608 goto fail;
609
610 diff1 = out_freq - input * mul1;
611 if (diff1 < 0)
612 diff1 = -diff1;
613 if (diff > diff1) {
614 diff = diff1;
615 div = i;
616 mul = mul1;
617 if (diff == 0)
618 break;
619 }
620 }
621 if (i == 256 && diff > (out_freq >> 5))
622 goto fail;
623 return ret | ((mul - 1) << 16) | div;
624fail:
625 return 0;
626}
627
628static struct clk *const standard_pmc_clocks[] __initconst = {
629
630 &clk32k,
631 &main_clk,
632 &plla,
633
634
635 &mck
636};
637
638
639static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
640{
641
642
643
644
645
646
647 uhpck.parent = &pllb;
648
649 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
650 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
651 if (cpu_is_at91rm9200()) {
652 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
653 udpck.pmc_mask = AT91RM9200_PMC_UDP;
654 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
655 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
656 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
657 cpu_is_at91sam9g10()) {
658 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
659 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
660 }
661 at91_pmc_write(AT91_CKGR_PLLBR, 0);
662
663 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
664 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
665}
666
667
668static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
669{
670
671
672
673 unsigned int usbr = AT91_PMC_USBS_UPLL;
674
675
676 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
677
678 at91_pmc_write(AT91_PMC_USB, usbr);
679
680
681 uhpck.parent = &utmi_clk;
682 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
683 uhpck.rate_hz = utmi_clk.rate_hz;
684 uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
685}
686
687static int __init at91_pmc_init(unsigned long main_clock)
688{
689 unsigned tmp, freq, mckr;
690 int i;
691 int pll_overclock = false;
692
693
694
695
696
697
698
699 if (!main_clock) {
700 do {
701 tmp = at91_pmc_read(AT91_CKGR_MCFR);
702 } while (!(tmp & AT91_PMC_MAINRDY));
703 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
704 }
705 main_clk.rate_hz = main_clock;
706
707
708 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
709 if (cpu_has_300M_plla()) {
710 if (plla.rate_hz > 300000000)
711 pll_overclock = true;
712 } else if (cpu_has_800M_plla()) {
713 if (plla.rate_hz > 800000000)
714 pll_overclock = true;
715 } else if (cpu_has_240M_plla()) {
716 if (plla.rate_hz > 240000000)
717 pll_overclock = true;
718 } else if (cpu_has_210M_plla()) {
719 if (plla.rate_hz > 210000000)
720 pll_overclock = true;
721 } else {
722 if (plla.rate_hz > 209000000)
723 pll_overclock = true;
724 }
725 if (pll_overclock)
726 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
727
728 if (cpu_has_plladiv2()) {
729 mckr = at91_pmc_read(AT91_PMC_MCKR);
730 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));
731 }
732
733 if (!cpu_has_pllb() && cpu_has_upll()) {
734
735
736 utmi_clk.type |= CLK_TYPE_PRIMARY;
737 utmi_clk.id = 3;
738 }
739
740
741
742
743
744 if (cpu_has_utmi()) {
745
746
747
748
749 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
750
751
752 if (cpu_has_upll())
753 utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
754 }
755
756
757
758
759 if (cpu_has_pllb())
760 at91_pllb_usbfs_clock_init(main_clock);
761 if (cpu_has_upll())
762
763 at91_upll_usbfs_clock_init(main_clock);
764
765
766
767
768
769 mckr = at91_pmc_read(AT91_PMC_MCKR);
770 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
771 freq = mck.parent->rate_hz;
772 freq /= pmc_prescaler_divider(mckr);
773 if (cpu_is_at91rm9200()) {
774 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));
775 } else if (cpu_is_at91sam9g20()) {
776 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
777 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;
778 if (mckr & AT91_PMC_PDIV)
779 freq /= 2;
780 } else if (cpu_has_mdiv3()) {
781 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
782 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));
783 } else {
784 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));
785 }
786
787 if (cpu_has_alt_prescaler()) {
788
789 mck.type |= CLK_TYPE_PRIMARY;
790 mck.id = 4;
791 }
792
793
794 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
795 at91_clk_add(standard_pmc_clocks[i]);
796
797 if (cpu_has_pllb())
798 at91_clk_add(&pllb);
799
800 if (cpu_has_uhp())
801 at91_clk_add(&uhpck);
802
803 if (cpu_has_udpfs())
804 at91_clk_add(&udpck);
805
806 if (cpu_has_utmi())
807 at91_clk_add(&utmi_clk);
808
809
810 clk_enable(&mck);
811
812 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
813 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
814 (unsigned) main_clock / 1000000,
815 ((unsigned) main_clock % 1000000) / 1000);
816
817 return 0;
818}
819
820#if defined(CONFIG_OF)
821static struct of_device_id pmc_ids[] = {
822 { .compatible = "atmel,at91rm9200-pmc" },
823 { }
824};
825
826static struct of_device_id osc_ids[] = {
827 { .compatible = "atmel,osc" },
828 { }
829};
830
831int __init at91_dt_clock_init(void)
832{
833 struct device_node *np;
834 u32 main_clock = 0;
835
836 np = of_find_matching_node(NULL, pmc_ids);
837 if (!np)
838 panic("unable to find compatible pmc node in dtb\n");
839
840 at91_pmc_base = of_iomap(np, 0);
841 if (!at91_pmc_base)
842 panic("unable to map pmc cpu registers\n");
843
844 of_node_put(np);
845
846
847 np = of_find_matching_node(NULL, osc_ids);
848 if (np) {
849 u32 rate;
850 if (!of_property_read_u32(np, "clock-frequency", &rate))
851 main_clock = rate;
852 }
853
854 of_node_put(np);
855
856 return at91_pmc_init(main_clock);
857}
858#endif
859
860int __init at91_clock_init(unsigned long main_clock)
861{
862 at91_pmc_base = ioremap(AT91_PMC, 256);
863 if (!at91_pmc_base)
864 panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
865
866 return at91_pmc_init(main_clock);
867}
868
869
870
871
872static int __init at91_clock_reset(void)
873{
874 unsigned long pcdr = 0;
875 unsigned long scdr = 0;
876 struct clk *clk;
877
878 list_for_each_entry(clk, &clocks, node) {
879 if (clk->users > 0)
880 continue;
881
882 if (clk->mode == pmc_periph_mode)
883 pcdr |= clk->pmc_mask;
884
885 if (clk->mode == pmc_sys_mode)
886 scdr |= clk->pmc_mask;
887
888 pr_debug("Clocks: disable unused %s\n", clk->name);
889 }
890
891 at91_pmc_write(AT91_PMC_PCDR, pcdr);
892 at91_pmc_write(AT91_PMC_SCDR, scdr);
893
894 return 0;
895}
896late_initcall(at91_clock_reset);
897
898void at91sam9_idle(void)
899{
900 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
901 cpu_do_idle();
902}
903