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15#include <linux/gpio.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/delay.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21#include <linux/types.h>
22
23#include <linux/usb/otg.h>
24
25#include "common.h"
26#include "devices-imx31.h"
27#include "hardware.h"
28#include "iomux-mx3.h"
29#include "ulpi.h"
30
31static unsigned int devboard_pins[] = {
32
33 MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
34 MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
35
36 MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2,
37 MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
38 MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
39 MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
40
41 MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
42 MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
43 MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
44 MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
45 MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
46
47 MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
48 MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
49};
50
51static const struct imxuart_platform_data uart_pdata __initconst = {
52 .flags = IMXUART_HAVE_RTSCTS,
53};
54
55#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
56#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW)
57
58static int devboard_sdhc2_get_ro(struct device *dev)
59{
60 return !gpio_get_value(SDHC2_WP);
61}
62
63static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
64 void *data)
65{
66 int ret;
67
68 ret = gpio_request(SDHC2_CD, "sdhc-detect");
69 if (ret)
70 return ret;
71
72 gpio_direction_input(SDHC2_CD);
73
74 ret = gpio_request(SDHC2_WP, "sdhc-wp");
75 if (ret)
76 goto err_gpio_free;
77 gpio_direction_input(SDHC2_WP);
78
79 ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq,
80 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
81 "sdhc2-card-detect", data);
82 if (ret)
83 goto err_gpio_free_2;
84
85 return 0;
86
87err_gpio_free_2:
88 gpio_free(SDHC2_WP);
89err_gpio_free:
90 gpio_free(SDHC2_CD);
91
92 return ret;
93}
94
95static void devboard_sdhc2_exit(struct device *dev, void *data)
96{
97 free_irq(gpio_to_irq(SDHC2_CD), data);
98 gpio_free(SDHC2_WP);
99 gpio_free(SDHC2_CD);
100}
101
102static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
103 .get_ro = devboard_sdhc2_get_ro,
104 .init = devboard_sdhc2_init,
105 .exit = devboard_sdhc2_exit,
106};
107
108#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
109#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
110#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
111#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
112
113static void devboard_init_sel_gpios(void)
114{
115 if (!gpio_request(SEL0, "sel0")) {
116 gpio_direction_input(SEL0);
117 gpio_export(SEL0, true);
118 }
119
120 if (!gpio_request(SEL1, "sel1")) {
121 gpio_direction_input(SEL1);
122 gpio_export(SEL1, true);
123 }
124
125 if (!gpio_request(SEL2, "sel2")) {
126 gpio_direction_input(SEL2);
127 gpio_export(SEL2, true);
128 }
129
130 if (!gpio_request(SEL3, "sel3")) {
131 gpio_direction_input(SEL3);
132 gpio_export(SEL3, true);
133 }
134}
135#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
136 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
137
138static int devboard_usbh1_hw_init(struct platform_device *pdev)
139{
140 mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
141
142 mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
143 mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
144 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
145 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
146 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
147 mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
148 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
149 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
150
151 mdelay(10);
152
153 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
154 MXC_EHCI_INTERFACE_SINGLE_UNI);
155}
156
157#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
158#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
159
160static int devboard_isp1105_init(struct usb_phy *otg)
161{
162 int ret = gpio_request(USBH1_MODE, "usbh1-mode");
163 if (ret)
164 return ret;
165
166 gpio_direction_output(USBH1_MODE, 0);
167
168 ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
169 if (ret) {
170 gpio_free(USBH1_MODE);
171 return ret;
172 }
173 gpio_direction_output(USBH1_VBUSEN_B, 1);
174
175 return 0;
176}
177
178
179static int devboard_isp1105_set_vbus(struct usb_otg *otg, bool on)
180{
181 if (on)
182 gpio_set_value(USBH1_VBUSEN_B, 0);
183 else
184 gpio_set_value(USBH1_VBUSEN_B, 1);
185
186 return 0;
187}
188
189static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
190 .init = devboard_usbh1_hw_init,
191 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
192};
193
194static int __init devboard_usbh1_init(void)
195{
196 struct usb_phy *phy;
197 struct platform_device *pdev;
198
199 phy = kzalloc(sizeof(*phy), GFP_KERNEL);
200 if (!phy)
201 return -ENOMEM;
202
203 phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
204 if (!phy->otg) {
205 kfree(phy);
206 return -ENOMEM;
207 }
208
209 phy->label = "ISP1105";
210 phy->init = devboard_isp1105_init;
211 phy->otg->set_vbus = devboard_isp1105_set_vbus;
212
213 usbh1_pdata.otg = phy;
214
215 pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
216 if (IS_ERR(pdev))
217 return PTR_ERR(pdev);
218
219 return 0;
220}
221
222
223static const struct fsl_usb2_platform_data usb_pdata __initconst = {
224 .operating_mode = FSL_USB2_DR_DEVICE,
225 .phy_mode = FSL_USB2_PHY_ULPI,
226};
227
228
229
230
231void __init mx31moboard_devboard_init(void)
232{
233 printk(KERN_INFO "Initializing mx31devboard peripherals\n");
234
235 mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins),
236 "devboard");
237
238 imx31_add_imx_uart1(&uart_pdata);
239
240 imx31_add_mxc_mmc(1, &sdhc2_pdata);
241
242 devboard_init_sel_gpios();
243
244 imx31_add_fsl_usb2_udc(&usb_pdata);
245
246 devboard_usbh1_init();
247}
248
