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21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/interrupt.h>
24#include <linux/clockchips.h>
25
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31
32#include <asm/sched_clock.h>
33#include <mach/addr-map.h>
34#include <mach/regs-timers.h>
35#include <mach/regs-apbc.h>
36#include <mach/irqs.h>
37#include <mach/cputype.h>
38#include <asm/mach/time.h>
39
40#include "clock.h"
41
42#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
43
44#define MAX_DELTA (0xfffffffe)
45#define MIN_DELTA (16)
46
47static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
48
49
50
51
52static inline uint32_t timer_read(void)
53{
54 int delay = 100;
55
56 __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
57
58 while (delay--)
59 cpu_relax();
60
61 return __raw_readl(mmp_timer_base + TMR_CVWR(1));
62}
63
64static u32 notrace mmp_read_sched_clock(void)
65{
66 return timer_read();
67}
68
69static irqreturn_t timer_interrupt(int irq, void *dev_id)
70{
71 struct clock_event_device *c = dev_id;
72
73
74
75
76 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
77
78
79
80
81 __raw_writel(0x02, mmp_timer_base + TMR_CER);
82
83 c->event_handler(c);
84
85 return IRQ_HANDLED;
86}
87
88static int timer_set_next_event(unsigned long delta,
89 struct clock_event_device *dev)
90{
91 unsigned long flags;
92
93 local_irq_save(flags);
94
95
96
97
98 __raw_writel(0x02, mmp_timer_base + TMR_CER);
99
100
101
102
103 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
104 __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
105
106
107
108
109 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
110
111
112
113
114 __raw_writel(0x03, mmp_timer_base + TMR_CER);
115
116 local_irq_restore(flags);
117
118 return 0;
119}
120
121static void timer_set_mode(enum clock_event_mode mode,
122 struct clock_event_device *dev)
123{
124 unsigned long flags;
125
126 local_irq_save(flags);
127 switch (mode) {
128 case CLOCK_EVT_MODE_ONESHOT:
129 case CLOCK_EVT_MODE_UNUSED:
130 case CLOCK_EVT_MODE_SHUTDOWN:
131
132 __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
133 break;
134 case CLOCK_EVT_MODE_RESUME:
135 case CLOCK_EVT_MODE_PERIODIC:
136 break;
137 }
138 local_irq_restore(flags);
139}
140
141static struct clock_event_device ckevt = {
142 .name = "clockevent",
143 .features = CLOCK_EVT_FEAT_ONESHOT,
144 .shift = 32,
145 .rating = 200,
146 .set_next_event = timer_set_next_event,
147 .set_mode = timer_set_mode,
148};
149
150static cycle_t clksrc_read(struct clocksource *cs)
151{
152 return timer_read();
153}
154
155static struct clocksource cksrc = {
156 .name = "clocksource",
157 .rating = 200,
158 .read = clksrc_read,
159 .mask = CLOCKSOURCE_MASK(32),
160 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
161};
162
163static void __init timer_config(void)
164{
165 uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
166
167 __raw_writel(0x0, mmp_timer_base + TMR_CER);
168
169 ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
170 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
171 __raw_writel(ccr, mmp_timer_base + TMR_CCR);
172
173
174 __raw_writel(0x2, mmp_timer_base + TMR_CMR);
175
176 __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0));
177 __raw_writel(0x7, mmp_timer_base + TMR_ICR(0));
178 __raw_writel(0x0, mmp_timer_base + TMR_IER(0));
179
180 __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1));
181 __raw_writel(0x7, mmp_timer_base + TMR_ICR(1));
182 __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
183
184
185 __raw_writel(0x2, mmp_timer_base + TMR_CER);
186}
187
188static struct irqaction timer_irq = {
189 .name = "timer",
190 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
191 .handler = timer_interrupt,
192 .dev_id = &ckevt,
193};
194
195void __init timer_init(int irq)
196{
197 timer_config();
198
199 setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
200
201 ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
202 ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
203 ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt);
204 ckevt.cpumask = cpumask_of(0);
205
206 setup_irq(irq, &timer_irq);
207
208 clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
209 clockevents_register_device(&ckevt);
210}
211
212#ifdef CONFIG_OF
213static struct of_device_id mmp_timer_dt_ids[] = {
214 { .compatible = "mrvl,mmp-timer", },
215 {}
216};
217
218void __init mmp_dt_init_timer(void)
219{
220 struct device_node *np;
221 int irq, ret;
222
223 np = of_find_matching_node(NULL, mmp_timer_dt_ids);
224 if (!np) {
225 ret = -ENODEV;
226 goto out;
227 }
228
229 irq = irq_of_parse_and_map(np, 0);
230 if (!irq) {
231 ret = -EINVAL;
232 goto out;
233 }
234 mmp_timer_base = of_iomap(np, 0);
235 if (!mmp_timer_base) {
236 ret = -ENOMEM;
237 goto out;
238 }
239 timer_init(irq);
240 return;
241out:
242 pr_err("Failed to get timer from device tree with error:%d\n", ret);
243}
244#endif
245