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15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h>
18#include <linux/io.h>
19
20#include <linux/platform_data/mtd-nand-omap2.h>
21#include <linux/platform_data/mtd-onenand-omap2.h>
22
23#include "soc.h"
24#include "common.h"
25#include "board-flash.h"
26#include "gpmc-onenand.h"
27#include "gpmc-nand.h"
28
29#define REG_FPGA_REV 0x10
30#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
31#define MAX_SUPPORTED_GPMC_CONFIG 3
32
33#define DEBUG_BASE 0x08000000
34
35
36#define FLASH_SIZE_SDPV1 SZ_64M
37#define FLASH_SIZE_SDPV2 SZ_128M
38
39static struct physmap_flash_data board_nor_data = {
40 .width = 2,
41};
42
43static struct resource board_nor_resource = {
44 .flags = IORESOURCE_MEM,
45};
46
47static struct platform_device board_nor_device = {
48 .name = "physmap-flash",
49 .id = 0,
50 .dev = {
51 .platform_data = &board_nor_data,
52 },
53 .num_resources = 1,
54 .resource = &board_nor_resource,
55};
56
57static void
58__init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
59{
60 int err;
61
62 board_nor_data.parts = nor_parts;
63 board_nor_data.nr_parts = nr_parts;
64
65
66 if (omap_rev() >= OMAP3430_REV_ES1_0) {
67 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1,
68 (unsigned long *)&board_nor_resource.start);
69 board_nor_resource.end = board_nor_resource.start
70 + FLASH_SIZE_SDPV2 - 1;
71 } else {
72 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1,
73 (unsigned long *)&board_nor_resource.start);
74 board_nor_resource.end = board_nor_resource.start
75 + FLASH_SIZE_SDPV1 - 1;
76 }
77 if (err < 0) {
78 pr_err("NOR: Can't request GPMC CS\n");
79 return;
80 }
81 if (platform_device_register(&board_nor_device) < 0)
82 pr_err("Unable to register NOR device\n");
83}
84
85#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
86 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
87static struct omap_onenand_platform_data board_onenand_data = {
88 .dma_channel = -1,
89};
90
91void
92__init board_onenand_init(struct mtd_partition *onenand_parts,
93 u8 nr_parts, u8 cs)
94{
95 board_onenand_data.cs = cs;
96 board_onenand_data.parts = onenand_parts;
97 board_onenand_data.nr_parts = nr_parts;
98
99 gpmc_onenand_init(&board_onenand_data);
100}
101#endif
102
103#if defined(CONFIG_MTD_NAND_OMAP2) || \
104 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
105
106
107struct gpmc_timings nand_default_timings[1] = {
108 {
109 .sync_clk = 0,
110
111 .cs_on = 0,
112 .cs_rd_off = 36,
113 .cs_wr_off = 36,
114
115 .adv_on = 6,
116 .adv_rd_off = 24,
117 .adv_wr_off = 36,
118
119 .we_off = 30,
120 .oe_off = 48,
121
122 .access = 54,
123 .rd_cycle = 72,
124 .wr_cycle = 72,
125
126 .wr_access = 30,
127 .wr_data_mux_bus = 0,
128 },
129};
130
131static struct omap_nand_platform_data board_nand_data;
132
133void
134__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
135 int nand_type, struct gpmc_timings *gpmc_t)
136{
137 board_nand_data.cs = cs;
138 board_nand_data.parts = nand_parts;
139 board_nand_data.nr_parts = nr_parts;
140 board_nand_data.devsize = nand_type;
141
142 board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
143 gpmc_nand_init(&board_nand_data, gpmc_t);
144}
145#endif
146
147
148
149
150
151static u8 get_gpmc0_type(void)
152{
153 u8 cs = 0;
154 void __iomem *fpga_map_addr;
155
156 fpga_map_addr = ioremap(DEBUG_BASE, 4096);
157 if (!fpga_map_addr)
158 return -ENOMEM;
159
160 if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV)))
161
162
163 goto unmap;
164
165
166 cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
167
168
169 if (omap_rev() >= OMAP3430_REV_ES1_0)
170
171 cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) |
172 ((cs & 2) << 1) | ((cs & 1) << 3);
173 else
174
175 cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2);
176unmap:
177 iounmap(fpga_map_addr);
178 return cs;
179}
180
181
182
183
184
185
186void __init board_flash_init(struct flash_partitions partition_info[],
187 char chip_sel_board[][GPMC_CS_NUM], int nand_type)
188{
189 u8 cs = 0;
190 u8 norcs = GPMC_CS_NUM + 1;
191 u8 nandcs = GPMC_CS_NUM + 1;
192 u8 onenandcs = GPMC_CS_NUM + 1;
193 u8 idx;
194 unsigned char *config_sel = NULL;
195
196
197
198
199 idx = get_gpmc0_type();
200 if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
201 pr_err("%s: Invalid chip select: %d\n", __func__, cs);
202 return;
203 }
204 config_sel = (unsigned char *)(chip_sel_board[idx]);
205
206 while (cs < GPMC_CS_NUM) {
207 switch (config_sel[cs]) {
208 case PDC_NOR:
209 if (norcs > GPMC_CS_NUM)
210 norcs = cs;
211 break;
212 case PDC_NAND:
213 if (nandcs > GPMC_CS_NUM)
214 nandcs = cs;
215 break;
216 case PDC_ONENAND:
217 if (onenandcs > GPMC_CS_NUM)
218 onenandcs = cs;
219 break;
220 }
221 cs++;
222 }
223
224 if (norcs > GPMC_CS_NUM)
225 pr_err("NOR: Unable to find configuration in GPMC\n");
226 else
227 board_nor_init(partition_info[0].parts,
228 partition_info[0].nr_parts, norcs);
229
230 if (onenandcs > GPMC_CS_NUM)
231 pr_err("OneNAND: Unable to find configuration in GPMC\n");
232 else
233 board_onenand_init(partition_info[1].parts,
234 partition_info[1].nr_parts, onenandcs);
235
236 if (nandcs > GPMC_CS_NUM)
237 pr_err("NAND: Unable to find configuration in GPMC\n");
238 else
239 board_nand_init(partition_info[2].parts,
240 partition_info[2].nr_parts, nandcs,
241 nand_type, nand_default_timings);
242}
243