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19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/err.h>
23#include <linux/io.h>
24
25#include "clockdomain.h"
26#include "cm.h"
27#include "cm33xx.h"
28#include "cm-regbits-34xx.h"
29#include "cm-regbits-33xx.h"
30#include "prm33xx.h"
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42
43#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
44#define CLKCTRL_IDLEST_INTRANSITION 0x1
45#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
46#define CLKCTRL_IDLEST_DISABLED 0x3
47
48
49
50
51static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
52{
53 return __raw_readl(cm_base + inst + idx);
54}
55
56
57static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
58{
59 __raw_writel(val, cm_base + inst + idx);
60}
61
62
63static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
64{
65 u32 v;
66
67 v = am33xx_cm_read_reg(inst, idx);
68 v &= ~mask;
69 v |= bits;
70 am33xx_cm_write_reg(v, inst, idx);
71
72 return v;
73}
74
75static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx)
76{
77 return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx);
78}
79
80static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx)
81{
82 return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
83}
84
85static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
86{
87 u32 v;
88
89 v = am33xx_cm_read_reg(inst, idx);
90 v &= mask;
91 v >>= __ffs(mask);
92
93 return v;
94}
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104
105static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
106{
107 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
108 v &= AM33XX_IDLEST_MASK;
109 v >>= AM33XX_IDLEST_SHIFT;
110 return v;
111}
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121
122static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
123{
124 u32 v;
125
126 v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs);
127
128 return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
129 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
130}
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140
141static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
142{
143 u32 v;
144
145 v = am33xx_cm_read_reg(inst, cdoffs);
146 v &= ~AM33XX_CLKTRCTRL_MASK;
147 v |= c << AM33XX_CLKTRCTRL_SHIFT;
148 am33xx_cm_write_reg(v, inst, cdoffs);
149}
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161bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
162{
163 u32 v;
164
165 v = am33xx_cm_read_reg(inst, cdoffs);
166 v &= AM33XX_CLKTRCTRL_MASK;
167 v >>= AM33XX_CLKTRCTRL_SHIFT;
168
169 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
170}
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179
180void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
181{
182 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
183}
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194void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
195{
196 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
197}
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207void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
208{
209 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
210}
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220void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
221{
222 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
223}
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240int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
241{
242 int i = 0;
243
244 if (!clkctrl_offs)
245 return 0;
246
247 omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
248 MAX_MODULE_READY_TIME, i);
249
250 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
251}
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263
264int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
265{
266 int i = 0;
267
268 if (!clkctrl_offs)
269 return 0;
270
271 omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) ==
272 CLKCTRL_IDLEST_DISABLED),
273 MAX_MODULE_READY_TIME, i);
274
275 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
276}
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287void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
288{
289 u32 v;
290
291 v = am33xx_cm_read_reg(inst, clkctrl_offs);
292 v &= ~AM33XX_MODULEMODE_MASK;
293 v |= mode << AM33XX_MODULEMODE_SHIFT;
294 am33xx_cm_write_reg(v, inst, clkctrl_offs);
295}
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305void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
306{
307 u32 v;
308
309 v = am33xx_cm_read_reg(inst, clkctrl_offs);
310 v &= ~AM33XX_MODULEMODE_MASK;
311 am33xx_cm_write_reg(v, inst, clkctrl_offs);
312}
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317
318static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
319{
320 am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
321 return 0;
322}
323
324static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
325{
326 am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
327 return 0;
328}
329
330static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
331{
332 am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
333}
334
335static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
336{
337 am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
338}
339
340static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
341{
342 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
343 return am33xx_clkdm_wakeup(clkdm);
344
345 return 0;
346}
347
348static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
349{
350 bool hwsup = false;
351
352 hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
353
354 if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
355 am33xx_clkdm_sleep(clkdm);
356
357 return 0;
358}
359
360struct clkdm_ops am33xx_clkdm_operations = {
361 .clkdm_sleep = am33xx_clkdm_sleep,
362 .clkdm_wakeup = am33xx_clkdm_wakeup,
363 .clkdm_allow_idle = am33xx_clkdm_allow_idle,
364 .clkdm_deny_idle = am33xx_clkdm_deny_idle,
365 .clkdm_clk_enable = am33xx_clkdm_clk_enable,
366 .clkdm_clk_disable = am33xx_clkdm_clk_disable,
367};
368