LXR linux/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h

   1/*
   2 *  arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
   3 *
   4 *  Taken from pxa-regs.h by Russell King
   5 *
   6 *  Author:     Nicolas Pitre
   7 *  Copyright:  MontaVista Software Inc.
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 */
  13
  14#ifndef __PXA2XX_REGS_H
  15#define __PXA2XX_REGS_H
  16
  17#include <mach/hardware.h>
  18
  19/*
  20 * Power Manager
  21 */
  22
  23#define PMCR            __REG(0x40F00000)  /* Power Manager Control Register */
  24#define PSSR            __REG(0x40F00004)  /* Power Manager Sleep Status Register */
  25#define PSPR            __REG(0x40F00008)  /* Power Manager Scratch Pad Register */
  26#define PWER            __REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
  27#define PRER            __REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
  28#define PFER            __REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
  29#define PEDR            __REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
  30#define PCFR            __REG(0x40F0001C)  /* Power Manager General Configuration Register */
  31#define PGSR0           __REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
  32#define PGSR1           __REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
  33#define PGSR2           __REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
  34#define PGSR3           __REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
  35#define RCSR            __REG(0x40F00030)  /* Reset Controller Status Register */
  36
  37#define PSLR            __REG(0x40F00034)       /* Power Manager Sleep Config Register */
  38#define PSTR            __REG(0x40F00038)       /* Power Manager Standby Config Register */
  39#define PSNR            __REG(0x40F0003C)       /* Power Manager Sense Config Register */
  40#define PVCR            __REG(0x40F00040)       /* Power Manager VoltageControl Register */
  41#define PKWR            __REG(0x40F00050)       /* Power Manager KB Wake-up Enable Reg */
  42#define PKSR            __REG(0x40F00054)       /* Power Manager KB Level-Detect Register */
  43#define PCMD(x) __REG2(0x40F00080, (x)<<2)
  44#define PCMD0   __REG(0x40F00080 + 0 * 4)
  45#define PCMD1   __REG(0x40F00080 + 1 * 4)
  46#define PCMD2   __REG(0x40F00080 + 2 * 4)
  47#define PCMD3   __REG(0x40F00080 + 3 * 4)
  48#define PCMD4   __REG(0x40F00080 + 4 * 4)
  49#define PCMD5   __REG(0x40F00080 + 5 * 4)
  50#define PCMD6   __REG(0x40F00080 + 6 * 4)
  51#define PCMD7   __REG(0x40F00080 + 7 * 4)
  52#define PCMD8   __REG(0x40F00080 + 8 * 4)
  53#define PCMD9   __REG(0x40F00080 + 9 * 4)
  54#define PCMD10  __REG(0x40F00080 + 10 * 4)
  55#define PCMD11  __REG(0x40F00080 + 11 * 4)
  56#define PCMD12  __REG(0x40F00080 + 12 * 4)
  57#define PCMD13  __REG(0x40F00080 + 13 * 4)
  58#define PCMD14  __REG(0x40F00080 + 14 * 4)
  59#define PCMD15  __REG(0x40F00080 + 15 * 4)
  60#define PCMD16  __REG(0x40F00080 + 16 * 4)
  61#define PCMD17  __REG(0x40F00080 + 17 * 4)
  62#define PCMD18  __REG(0x40F00080 + 18 * 4)
  63#define PCMD19  __REG(0x40F00080 + 19 * 4)
  64#define PCMD20  __REG(0x40F00080 + 20 * 4)
  65#define PCMD21  __REG(0x40F00080 + 21 * 4)
  66#define PCMD22  __REG(0x40F00080 + 22 * 4)
  67#define PCMD23  __REG(0x40F00080 + 23 * 4)
  68#define PCMD24  __REG(0x40F00080 + 24 * 4)
  69#define PCMD25  __REG(0x40F00080 + 25 * 4)
  70#define PCMD26  __REG(0x40F00080 + 26 * 4)
  71#define PCMD27  __REG(0x40F00080 + 27 * 4)
  72#define PCMD28  __REG(0x40F00080 + 28 * 4)
  73#define PCMD29  __REG(0x40F00080 + 29 * 4)
  74#define PCMD30  __REG(0x40F00080 + 30 * 4)
  75#define PCMD31  __REG(0x40F00080 + 31 * 4)
  76
  77#define PCMD_MBC        (1<<12)
  78#define PCMD_DCE        (1<<11)
  79#define PCMD_LC (1<<10)
  80/* FIXME:  PCMD_SQC need be checked.   */
  81#define PCMD_SQC        (3<<8)  /* currently only bit 8 is changeable,
  82                                   bit 9 should be 0 all day. */
  83#define PVCR_VCSA       (0x1<<14)
  84#define PVCR_CommandDelay (0xf80)
  85#define PCFR_PI2C_EN    (0x1 << 6)
  86
  87#define PSSR_OTGPH      (1 << 6)        /* OTG Peripheral control Hold */
  88#define PSSR_RDH        (1 << 5)        /* Read Disable Hold */
  89#define PSSR_PH         (1 << 4)        /* Peripheral Control Hold */
  90#define PSSR_STS        (1 << 3)        /* Standby Mode Status */
  91#define PSSR_VFS        (1 << 2)        /* VDD Fault Status */
  92#define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
  93#define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
  94
  95#define PSLR_SL_ROD     (1 << 20)       /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
  96
  97#define PCFR_RO         (1 << 15)       /* RDH Override */
  98#define PCFR_PO         (1 << 14)       /* PH Override */
  99#define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
 100#define PCFR_L1_EN      (1 << 11)       /* Sleep Mode L1 converter Enable */
 101#define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
 102#define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
 103#define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
 104#define PCFR_GPR_EN     (1 << 4)        /* nRESET_GPIO Pin Enable */
 105#define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
 106#define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
 107#define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
 108#define PCFR_OPDE       (1 << 0)        /* 3.6864 MHz oscillator power-down enable */
 109
 110#define RCSR_GPR        (1 << 3)        /* GPIO Reset */
 111#define RCSR_SMR        (1 << 2)        /* Sleep Mode */
 112#define RCSR_WDR        (1 << 1)        /* Watchdog Reset */
 113#define RCSR_HWR        (1 << 0)        /* Hardware Reset */
 114
 115#define PWER_GPIO(Nb)   (1 << Nb)       /* GPIO [0..15] wake-up enable     */
 116#define PWER_GPIO0      PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
 117#define PWER_GPIO1      PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
 118#define PWER_GPIO2      PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
 119#define PWER_GPIO3      PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
 120#define PWER_GPIO4      PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
 121#define PWER_GPIO5      PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
 122#define PWER_GPIO6      PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
 123#define PWER_GPIO7      PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
 124#define PWER_GPIO8      PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
 125#define PWER_GPIO9      PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
 126#define PWER_GPIO10     PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
 127#define PWER_GPIO11     PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
 128#define PWER_GPIO12     PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
 129#define PWER_GPIO13     PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
 130#define PWER_GPIO14     PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
 131#define PWER_GPIO15     PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
 132#define PWER_RTC        0x80000000      /* RTC alarm wake-up enable        */
 133
 134/*
 135 * PXA2xx specific Core clock definitions
 136 */
 137#define CCCR            __REG(0x41300000)  /* Core Clock Configuration Register */
 138#define CCSR            __REG(0x4130000C)  /* Core Clock Status Register */
 139#define CKEN            __REG(0x41300004)  /* Clock Enable Register */
 140#define OSCC            __REG(0x41300008)  /* Oscillator Configuration Register */
 141
 142#define CCCR_N_MASK     0x0380  /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
 143#define CCCR_M_MASK     0x0060  /* Memory Frequency to Run Mode Frequency Multiplier */
 144#define CCCR_L_MASK     0x001f  /* Crystal Frequency to Memory Frequency Multiplier */
 145
 146#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
 147#define CKEN_CAMERA     (24)    /* Camera Interface Clock Enable */
 148#define CKEN_SSP1       (23)    /* SSP1 Unit Clock Enable */
 149#define CKEN_MEMC       (22)    /* Memory Controller Clock Enable */
 150#define CKEN_MEMSTK     (21)    /* Memory Stick Host Controller */
 151#define CKEN_IM         (20)    /* Internal Memory Clock Enable */
 152#define CKEN_KEYPAD     (19)    /* Keypad Interface Clock Enable */
 153#define CKEN_USIM       (18)    /* USIM Unit Clock Enable */
 154#define CKEN_MSL        (17)    /* MSL Unit Clock Enable */
 155#define CKEN_LCD        (16)    /* LCD Unit Clock Enable */
 156#define CKEN_PWRI2C     (15)    /* PWR I2C Unit Clock Enable */
 157#define CKEN_I2C        (14)    /* I2C Unit Clock Enable */
 158#define CKEN_FICP       (13)    /* FICP Unit Clock Enable */
 159#define CKEN_MMC        (12)    /* MMC Unit Clock Enable */
 160#define CKEN_USB        (11)    /* USB Unit Clock Enable */
 161#define CKEN_ASSP       (10)    /* ASSP (SSP3) Clock Enable */
 162#define CKEN_USBHOST    (10)    /* USB Host Unit Clock Enable */
 163#define CKEN_OSTIMER    (9)     /* OS Timer Unit Clock Enable */
 164#define CKEN_NSSP       (9)     /* NSSP (SSP2) Clock Enable */
 165#define CKEN_I2S        (8)     /* I2S Unit Clock Enable */
 166#define CKEN_BTUART     (7)     /* BTUART Unit Clock Enable */
 167#define CKEN_FFUART     (6)     /* FFUART Unit Clock Enable */
 168#define CKEN_STUART     (5)     /* STUART Unit Clock Enable */
 169#define CKEN_HWUART     (4)     /* HWUART Unit Clock Enable */
 170#define CKEN_SSP3       (4)     /* SSP3 Unit Clock Enable */
 171#define CKEN_SSP        (3)     /* SSP Unit Clock Enable */
 172#define CKEN_SSP2       (3)     /* SSP2 Unit Clock Enable */
 173#define CKEN_AC97       (2)     /* AC97 Unit Clock Enable */
 174#define CKEN_PWM1       (1)     /* PWM1 Clock Enable */
 175#define CKEN_PWM0       (0)     /* PWM0 Clock Enable */
 176
 177#define OSCC_OON        (1 << 1)        /* 32.768kHz OON (write-once only bit) */
 178#define OSCC_OOK        (1 << 0)        /* 32.768kHz OOK (read-only bit) */
 179
 180/* PWRMODE register M field values */
 181
 182#define PWRMODE_IDLE            0x1
 183#define PWRMODE_STANDBY         0x2
 184#define PWRMODE_SLEEP           0x3
 185#define PWRMODE_DEEPSLEEP       0x7
 186
 187#endif
 188