LXR linux/arch/mips/include/asm/pci.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 */
   6#ifndef _ASM_PCI_H
   7#define _ASM_PCI_H
   8
   9#include <linux/mm.h>
  10
  11#ifdef __KERNEL__
  12
  13/*
  14 * This file essentially defines the interface between board
  15 * specific PCI code and MIPS common PCI code.  Should potentially put
  16 * into include/asm/pci.h file.
  17 */
  18
  19#include <linux/ioport.h>
  20#include <linux/of.h>
  21
  22/*
  23 * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
  24 * multiple PCI channels may have multiple PCI host controllers or a
  25 * single controller supporting multiple channels.
  26 */
  27struct pci_controller {
  28        struct pci_controller *next;
  29        struct pci_bus *bus;
  30        struct device_node *of_node;
  31
  32        struct pci_ops *pci_ops;
  33        struct resource *mem_resource;
  34        unsigned long mem_offset;
  35        struct resource *io_resource;
  36        unsigned long io_offset;
  37        unsigned long io_map_base;
  38
  39        unsigned int index;
  40        /* For compatibility with current (as of July 2003) pciutils
  41           and XFree86. Eventually will be removed. */
  42        unsigned int need_domain_info;
  43
  44        int iommu;
  45
  46        /* Optional access methods for reading/writing the bus number
  47           of the PCI controller */
  48        int (*get_busno)(void);
  49        void (*set_busno)(int busno);
  50};
  51
  52/*
  53 * Used by boards to register their PCI busses before the actual scanning.
  54 */
  55extern struct pci_controller * alloc_pci_controller(void);
  56extern void register_pci_controller(struct pci_controller *hose);
  57
  58/*
  59 * board supplied pci irq fixup routine
  60 */
  61extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
  62
  63
  64/* Can be used to override the logic in pci_scan_bus for skipping
  65   already-configured bus numbers - to be used for buggy BIOSes
  66   or architectures with incomplete PCI setup by the loader */
  67
  68extern unsigned int pcibios_assign_all_busses(void);
  69
  70extern unsigned long PCIBIOS_MIN_IO;
  71extern unsigned long PCIBIOS_MIN_MEM;
  72
  73#define PCIBIOS_MIN_CARDBUS_IO  0x4000
  74
  75extern void pcibios_set_master(struct pci_dev *dev);
  76
  77static inline void pcibios_penalize_isa_irq(int irq, int active)
  78{
  79        /* We don't do dynamic PCI IRQ allocation */
  80}
  81
  82#define HAVE_PCI_MMAP
  83
  84extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  85        enum pci_mmap_state mmap_state, int write_combine);
  86
  87/*
  88 * Dynamic DMA mapping stuff.
  89 * MIPS has everything mapped statically.
  90 */
  91
  92#include <linux/types.h>
  93#include <linux/slab.h>
  94#include <asm/scatterlist.h>
  95#include <linux/string.h>
  96#include <asm/io.h>
  97#include <asm-generic/pci-bridge.h>
  98
  99struct pci_dev;
 100
 101/*
 102 * The PCI address space does equal the physical memory address space.  The
 103 * networking and block device layers use this boolean for bounce buffer
 104 * decisions.  This is set if any hose does not have an IOMMU.
 105 */
 106extern unsigned int PCI_DMA_BUS_IS_PHYS;
 107
 108#ifdef CONFIG_PCI
 109static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 110                                        enum pci_dma_burst_strategy *strat,
 111                                        unsigned long *strategy_parameter)
 112{
 113        *strat = PCI_DMA_BURST_INFINITY;
 114        *strategy_parameter = ~0UL;
 115}
 116#endif
 117
 118#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 119
 120static inline int pci_proc_domain(struct pci_bus *bus)
 121{
 122        struct pci_controller *hose = bus->sysdata;
 123        return hose->need_domain_info;
 124}
 125
 126#endif /* __KERNEL__ */
 127
 128/* implement the pci_ DMA API in terms of the generic device dma_ one */
 129#include <asm-generic/pci-dma-compat.h>
 130
 131/* Do platform specific device initialization at pci_enable_device() time */
 132extern int pcibios_plat_dev_init(struct pci_dev *dev);
 133
 134/* Chances are this interrupt is wired PC-style ...  */
 135static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 136{
 137        return channel ? 15 : 14;
 138}
 139
 140#ifdef CONFIG_CPU_CAVIUM_OCTEON
 141/* MSI arch hook for OCTEON */
 142#define arch_setup_msi_irqs arch_setup_msi_irqs
 143#endif
 144
 145extern char * (*pcibios_plat_setup)(char *str);
 146
 147/* this function parses memory ranges from a device node */
 148extern void pci_load_of_ranges(struct pci_controller *hose,
 149                               struct device_node *node);
 150
 151#endif /* _ASM_PCI_H */
 152