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14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/gpio.h>
18#include <linux/spinlock.h>
19#include <linux/io.h>
20
21#define MSP71XX_CFG_OFFSET(gpio) (4 * (gpio))
22#define CONF_MASK 0x0F
23#define MSP71XX_GPIO_INPUT 0x01
24#define MSP71XX_GPIO_OUTPUT 0x08
25
26#define MSP71XX_GPIO_BASE 0x0B8400000L
27
28#define to_msp71xx_gpio_chip(c) container_of(c, struct msp71xx_gpio_chip, chip)
29
30static spinlock_t gpio_lock;
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39struct msp71xx_gpio_chip {
40 struct gpio_chip chip;
41 void __iomem *data_reg;
42 void __iomem *config_reg;
43 void __iomem *out_drive_reg;
44};
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52
53static int msp71xx_gpio_get(struct gpio_chip *chip, unsigned offset)
54{
55 struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
56
57 return __raw_readl(msp_chip->data_reg) & (1 << offset);
58}
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68
69static void msp71xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
70{
71 struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
72 unsigned long flags;
73 u32 data;
74
75 spin_lock_irqsave(&gpio_lock, flags);
76
77 data = __raw_readl(msp_chip->data_reg);
78 if (value)
79 data |= (1 << offset);
80 else
81 data &= ~(1 << offset);
82 __raw_writel(data, msp_chip->data_reg);
83
84 spin_unlock_irqrestore(&gpio_lock, flags);
85}
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95static int msp71xx_set_gpio_mode(struct gpio_chip *chip,
96 unsigned offset, int mode)
97{
98 struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
99 const unsigned bit_offset = MSP71XX_CFG_OFFSET(offset);
100 unsigned long flags;
101 u32 cfg;
102
103 spin_lock_irqsave(&gpio_lock, flags);
104
105 cfg = __raw_readl(msp_chip->config_reg);
106 cfg &= ~(CONF_MASK << bit_offset);
107 cfg |= (mode << bit_offset);
108 __raw_writel(cfg, msp_chip->config_reg);
109
110 spin_unlock_irqrestore(&gpio_lock, flags);
111
112 return 0;
113}
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124static int msp71xx_direction_output(struct gpio_chip *chip,
125 unsigned offset, int value)
126{
127 msp71xx_gpio_set(chip, offset, value);
128
129 return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_OUTPUT);
130}
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139static int msp71xx_direction_input(struct gpio_chip *chip, unsigned offset)
140{
141 return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_INPUT);
142}
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151int msp71xx_set_output_drive(unsigned gpio, int value)
152{
153 unsigned long flags;
154 u32 data;
155
156 if (gpio > 15 || gpio < 0)
157 return -EINVAL;
158
159 spin_lock_irqsave(&gpio_lock, flags);
160
161 data = __raw_readl((void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
162 if (value)
163 data |= (1 << gpio);
164 else
165 data &= ~(1 << gpio);
166 __raw_writel(data, (void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
167
168 spin_unlock_irqrestore(&gpio_lock, flags);
169
170 return 0;
171}
172EXPORT_SYMBOL(msp71xx_set_output_drive);
173
174#define MSP71XX_GPIO_BANK(name, dr, cr, base_gpio, num_gpio) \
175{ \
176 .chip = { \
177 .label = name, \
178 .direction_input = msp71xx_direction_input, \
179 .direction_output = msp71xx_direction_output, \
180 .get = msp71xx_gpio_get, \
181 .set = msp71xx_gpio_set, \
182 .base = base_gpio, \
183 .ngpio = num_gpio \
184 }, \
185 .data_reg = (void __iomem *)(MSP71XX_GPIO_BASE + dr), \
186 .config_reg = (void __iomem *)(MSP71XX_GPIO_BASE + cr), \
187 .out_drive_reg = (void __iomem *)(MSP71XX_GPIO_BASE + 0x190), \
188}
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200static struct msp71xx_gpio_chip msp71xx_gpio_banks[] = {
201
202 MSP71XX_GPIO_BANK("GPIO_1_0", 0x170, 0x180, 0, 2),
203 MSP71XX_GPIO_BANK("GPIO_5_2", 0x174, 0x184, 2, 4),
204 MSP71XX_GPIO_BANK("GPIO_9_6", 0x178, 0x188, 6, 4),
205 MSP71XX_GPIO_BANK("GPIO_15_10", 0x17C, 0x18C, 10, 6),
206};
207
208void __init msp71xx_init_gpio(void)
209{
210 int i;
211
212 spin_lock_init(&gpio_lock);
213
214 for (i = 0; i < ARRAY_SIZE(msp71xx_gpio_banks); i++)
215 gpiochip_add(&msp71xx_gpio_banks[i].chip);
216}
217