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19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/export.h>
25#include <linux/of_address.h>
26#include <linux/of_pci.h>
27#include <linux/mm.h>
28#include <linux/list.h>
29#include <linux/syscalls.h>
30#include <linux/irq.h>
31#include <linux/vmalloc.h>
32#include <linux/slab.h>
33
34#include <asm/processor.h>
35#include <asm/io.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#include <asm/byteorder.h>
39#include <asm/machdep.h>
40#include <asm/ppc-pci.h>
41#include <asm/eeh.h>
42
43static DEFINE_SPINLOCK(hose_spinlock);
44LIST_HEAD(hose_list);
45
46
47static int global_phb_number;
48
49
50resource_size_t isa_mem_base;
51
52
53static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
54
55void set_pci_dma_ops(struct dma_map_ops *dma_ops)
56{
57 pci_dma_ops = dma_ops;
58}
59
60struct dma_map_ops *get_pci_dma_ops(void)
61{
62 return pci_dma_ops;
63}
64EXPORT_SYMBOL(get_pci_dma_ops);
65
66struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
67{
68 struct pci_controller *phb;
69
70 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
71 if (phb == NULL)
72 return NULL;
73 spin_lock(&hose_spinlock);
74 phb->global_number = global_phb_number++;
75 list_add_tail(&phb->list_node, &hose_list);
76 spin_unlock(&hose_spinlock);
77 phb->dn = dev;
78 phb->is_dynamic = mem_init_done;
79#ifdef CONFIG_PPC64
80 if (dev) {
81 int nid = of_node_to_nid(dev);
82
83 if (nid < 0 || !node_online(nid))
84 nid = -1;
85
86 PHB_SET_NODE(phb, nid);
87 }
88#endif
89 return phb;
90}
91
92void pcibios_free_controller(struct pci_controller *phb)
93{
94 spin_lock(&hose_spinlock);
95 list_del(&phb->list_node);
96 spin_unlock(&hose_spinlock);
97
98 if (phb->is_dynamic)
99 kfree(phb);
100}
101
102
103
104
105
106
107
108resource_size_t pcibios_window_alignment(struct pci_bus *bus,
109 unsigned long type)
110{
111 if (ppc_md.pcibios_window_alignment)
112 return ppc_md.pcibios_window_alignment(bus, type);
113
114
115
116
117
118
119 return 1;
120}
121
122static resource_size_t pcibios_io_size(const struct pci_controller *hose)
123{
124#ifdef CONFIG_PPC64
125 return hose->pci_io_size;
126#else
127 return resource_size(&hose->io_resource);
128#endif
129}
130
131int pcibios_vaddr_is_ioport(void __iomem *address)
132{
133 int ret = 0;
134 struct pci_controller *hose;
135 resource_size_t size;
136
137 spin_lock(&hose_spinlock);
138 list_for_each_entry(hose, &hose_list, list_node) {
139 size = pcibios_io_size(hose);
140 if (address >= hose->io_base_virt &&
141 address < (hose->io_base_virt + size)) {
142 ret = 1;
143 break;
144 }
145 }
146 spin_unlock(&hose_spinlock);
147 return ret;
148}
149
150unsigned long pci_address_to_pio(phys_addr_t address)
151{
152 struct pci_controller *hose;
153 resource_size_t size;
154 unsigned long ret = ~0;
155
156 spin_lock(&hose_spinlock);
157 list_for_each_entry(hose, &hose_list, list_node) {
158 size = pcibios_io_size(hose);
159 if (address >= hose->io_base_phys &&
160 address < (hose->io_base_phys + size)) {
161 unsigned long base =
162 (unsigned long)hose->io_base_virt - _IO_BASE;
163 ret = base + (address - hose->io_base_phys);
164 break;
165 }
166 }
167 spin_unlock(&hose_spinlock);
168
169 return ret;
170}
171EXPORT_SYMBOL_GPL(pci_address_to_pio);
172
173
174
175
176int pci_domain_nr(struct pci_bus *bus)
177{
178 struct pci_controller *hose = pci_bus_to_host(bus);
179
180 return hose->global_number;
181}
182EXPORT_SYMBOL(pci_domain_nr);
183
184
185
186
187
188
189
190
191struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
192{
193 while(node) {
194 struct pci_controller *hose, *tmp;
195 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
196 if (hose->dn == node)
197 return hose;
198 node = node->parent;
199 }
200 return NULL;
201}
202
203static ssize_t pci_show_devspec(struct device *dev,
204 struct device_attribute *attr, char *buf)
205{
206 struct pci_dev *pdev;
207 struct device_node *np;
208
209 pdev = to_pci_dev (dev);
210 np = pci_device_to_OF_node(pdev);
211 if (np == NULL || np->full_name == NULL)
212 return 0;
213 return sprintf(buf, "%s", np->full_name);
214}
215static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
216
217
218int pcibios_add_platform_entries(struct pci_dev *pdev)
219{
220 return device_create_file(&pdev->dev, &dev_attr_devspec);
221}
222
223
224
225
226
227
228static int pci_read_irq_line(struct pci_dev *pci_dev)
229{
230 struct of_irq oirq;
231 unsigned int virq;
232
233 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
234
235#ifdef DEBUG
236 memset(&oirq, 0xff, sizeof(oirq));
237#endif
238
239 if (of_irq_map_pci(pci_dev, &oirq)) {
240 u8 line, pin;
241
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243
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245
246
247
248
249 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
250 return -1;
251 if (pin == 0)
252 return -1;
253 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
254 line == 0xff || line == 0) {
255 return -1;
256 }
257 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
258 line, pin);
259
260 virq = irq_create_mapping(NULL, line);
261 if (virq != NO_IRQ)
262 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
263 } else {
264 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
265 oirq.size, oirq.specifier[0], oirq.specifier[1],
266 of_node_full_name(oirq.controller));
267
268 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
269 oirq.size);
270 }
271 if(virq == NO_IRQ) {
272 pr_debug(" Failed to map !\n");
273 return -1;
274 }
275
276 pr_debug(" Mapped to linux irq %d\n", virq);
277
278 pci_dev->irq = virq;
279
280 return 0;
281}
282
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299
300static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
301 resource_size_t *offset,
302 enum pci_mmap_state mmap_state)
303{
304 struct pci_controller *hose = pci_bus_to_host(dev->bus);
305 unsigned long io_offset = 0;
306 int i, res_bit;
307
308 if (hose == 0)
309 return NULL;
310
311
312 if (mmap_state == pci_mmap_mem) {
313#if 0
314 *offset += hose->pci_mem_offset;
315#endif
316 res_bit = IORESOURCE_MEM;
317 } else {
318 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
319 *offset += io_offset;
320 res_bit = IORESOURCE_IO;
321 }
322
323
324
325
326
327 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
328 struct resource *rp = &dev->resource[i];
329 int flags = rp->flags;
330
331
332 if (i == PCI_ROM_RESOURCE)
333 flags |= IORESOURCE_MEM;
334
335
336 if ((flags & res_bit) == 0)
337 continue;
338
339
340 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
341 continue;
342
343
344 if (mmap_state == pci_mmap_io)
345 *offset += hose->io_base_phys - io_offset;
346 return rp;
347 }
348
349 return NULL;
350}
351
352
353
354
355
356static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
357 pgprot_t protection,
358 enum pci_mmap_state mmap_state,
359 int write_combine)
360{
361 unsigned long prot = pgprot_val(protection);
362
363
364
365
366
367
368
369 if (mmap_state != pci_mmap_mem)
370 write_combine = 0;
371 else if (write_combine == 0) {
372 if (rp->flags & IORESOURCE_PREFETCH)
373 write_combine = 1;
374 }
375
376
377 if (write_combine)
378 return pgprot_noncached_wc(prot);
379 else
380 return pgprot_noncached(prot);
381}
382
383
384
385
386
387
388pgprot_t pci_phys_mem_access_prot(struct file *file,
389 unsigned long pfn,
390 unsigned long size,
391 pgprot_t prot)
392{
393 struct pci_dev *pdev = NULL;
394 struct resource *found = NULL;
395 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
396 int i;
397
398 if (page_is_ram(pfn))
399 return prot;
400
401 prot = pgprot_noncached(prot);
402 for_each_pci_dev(pdev) {
403 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
404 struct resource *rp = &pdev->resource[i];
405 int flags = rp->flags;
406
407
408 if ((flags & IORESOURCE_MEM) == 0)
409 continue;
410
411 if (offset < (rp->start & PAGE_MASK) ||
412 offset > rp->end)
413 continue;
414 found = rp;
415 break;
416 }
417 if (found)
418 break;
419 }
420 if (found) {
421 if (found->flags & IORESOURCE_PREFETCH)
422 prot = pgprot_noncached_wc(prot);
423 pci_dev_put(pdev);
424 }
425
426 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
427 (unsigned long long)offset, pgprot_val(prot));
428
429 return prot;
430}
431
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442
443int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
444 enum pci_mmap_state mmap_state, int write_combine)
445{
446 resource_size_t offset =
447 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
448 struct resource *rp;
449 int ret;
450
451 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
452 if (rp == NULL)
453 return -EINVAL;
454
455 vma->vm_pgoff = offset >> PAGE_SHIFT;
456 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
457 vma->vm_page_prot,
458 mmap_state, write_combine);
459
460 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
461 vma->vm_end - vma->vm_start, vma->vm_page_prot);
462
463 return ret;
464}
465
466
467int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
468{
469 unsigned long offset;
470 struct pci_controller *hose = pci_bus_to_host(bus);
471 struct resource *rp = &hose->io_resource;
472 void __iomem *addr;
473
474
475
476
477
478
479 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
480 offset += port;
481
482 if (!(rp->flags & IORESOURCE_IO))
483 return -ENXIO;
484 if (offset < rp->start || (offset + size) > rp->end)
485 return -ENXIO;
486 addr = hose->io_base_virt + port;
487
488 switch(size) {
489 case 1:
490 *((u8 *)val) = in_8(addr);
491 return 1;
492 case 2:
493 if (port & 1)
494 return -EINVAL;
495 *((u16 *)val) = in_le16(addr);
496 return 2;
497 case 4:
498 if (port & 3)
499 return -EINVAL;
500 *((u32 *)val) = in_le32(addr);
501 return 4;
502 }
503 return -EINVAL;
504}
505
506
507int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
508{
509 unsigned long offset;
510 struct pci_controller *hose = pci_bus_to_host(bus);
511 struct resource *rp = &hose->io_resource;
512 void __iomem *addr;
513
514
515
516
517
518
519 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
520 offset += port;
521
522 if (!(rp->flags & IORESOURCE_IO))
523 return -ENXIO;
524 if (offset < rp->start || (offset + size) > rp->end)
525 return -ENXIO;
526 addr = hose->io_base_virt + port;
527
528
529
530
531
532
533 switch(size) {
534 case 1:
535 out_8(addr, val >> 24);
536 return 1;
537 case 2:
538 if (port & 1)
539 return -EINVAL;
540 out_le16(addr, val >> 16);
541 return 2;
542 case 4:
543 if (port & 3)
544 return -EINVAL;
545 out_le32(addr, val);
546 return 4;
547 }
548 return -EINVAL;
549}
550
551
552int pci_mmap_legacy_page_range(struct pci_bus *bus,
553 struct vm_area_struct *vma,
554 enum pci_mmap_state mmap_state)
555{
556 struct pci_controller *hose = pci_bus_to_host(bus);
557 resource_size_t offset =
558 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
559 resource_size_t size = vma->vm_end - vma->vm_start;
560 struct resource *rp;
561
562 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
563 pci_domain_nr(bus), bus->number,
564 mmap_state == pci_mmap_mem ? "MEM" : "IO",
565 (unsigned long long)offset,
566 (unsigned long long)(offset + size - 1));
567
568 if (mmap_state == pci_mmap_mem) {
569
570
571
572
573
574
575
576 if ((offset + size) > hose->isa_mem_size) {
577 printk(KERN_DEBUG
578 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
579 current->comm, current->pid, pci_domain_nr(bus), bus->number);
580 if (vma->vm_flags & VM_SHARED)
581 return shmem_zero_setup(vma);
582 return 0;
583 }
584 offset += hose->isa_mem_phys;
585 } else {
586 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
587 unsigned long roffset = offset + io_offset;
588 rp = &hose->io_resource;
589 if (!(rp->flags & IORESOURCE_IO))
590 return -ENXIO;
591 if (roffset < rp->start || (roffset + size) > rp->end)
592 return -ENXIO;
593 offset += hose->io_base_phys;
594 }
595 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
596
597 vma->vm_pgoff = offset >> PAGE_SHIFT;
598 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
599 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
600 vma->vm_end - vma->vm_start,
601 vma->vm_page_prot);
602}
603
604void pci_resource_to_user(const struct pci_dev *dev, int bar,
605 const struct resource *rsrc,
606 resource_size_t *start, resource_size_t *end)
607{
608 struct pci_controller *hose = pci_bus_to_host(dev->bus);
609 resource_size_t offset = 0;
610
611 if (hose == NULL)
612 return;
613
614 if (rsrc->flags & IORESOURCE_IO)
615 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
616
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623
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628
629
630
631
632
633
634#if 0
635 else if (rsrc->flags & IORESOURCE_MEM)
636 offset = hose->pci_mem_offset;
637#endif
638
639 *start = rsrc->start - offset;
640 *end = rsrc->end - offset;
641}
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675
676void pci_process_bridge_OF_ranges(struct pci_controller *hose,
677 struct device_node *dev, int primary)
678{
679 const u32 *ranges;
680 int rlen;
681 int pna = of_n_addr_cells(dev);
682 int np = pna + 5;
683 int memno = 0, isa_hole = -1;
684 u32 pci_space;
685 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
686 unsigned long long isa_mb = 0;
687 struct resource *res;
688
689 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
690 dev->full_name, primary ? "(primary)" : "");
691
692
693 ranges = of_get_property(dev, "ranges", &rlen);
694 if (ranges == NULL)
695 return;
696
697
698 while ((rlen -= np * 4) >= 0) {
699
700 pci_space = ranges[0];
701 pci_addr = of_read_number(ranges + 1, 2);
702 cpu_addr = of_translate_address(dev, ranges + 3);
703 size = of_read_number(ranges + pna + 3, 2);
704 ranges += np;
705
706
707
708
709
710
711 if (cpu_addr == OF_BAD_ADDR || size == 0)
712 continue;
713
714
715 for (; rlen >= np * sizeof(u32);
716 ranges += np, rlen -= np * 4) {
717 if (ranges[0] != pci_space)
718 break;
719 pci_next = of_read_number(ranges + 1, 2);
720 cpu_next = of_translate_address(dev, ranges + 3);
721 if (pci_next != pci_addr + size ||
722 cpu_next != cpu_addr + size)
723 break;
724 size += of_read_number(ranges + pna + 3, 2);
725 }
726
727
728 res = NULL;
729 switch ((pci_space >> 24) & 0x3) {
730 case 1:
731 printk(KERN_INFO
732 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
733 cpu_addr, cpu_addr + size - 1, pci_addr);
734
735
736 if (hose->pci_io_size) {
737 printk(KERN_INFO
738 " \\--> Skipped (too many) !\n");
739 continue;
740 }
741#ifdef CONFIG_PPC32
742
743 if (size > 0x01000000)
744 size = 0x01000000;
745
746
747 hose->io_base_virt = ioremap(cpu_addr, size);
748
749
750 if (primary)
751 isa_io_base =
752 (unsigned long)hose->io_base_virt;
753#endif
754
755
756
757 hose->pci_io_size = pci_addr + size;
758 hose->io_base_phys = cpu_addr - pci_addr;
759
760
761 res = &hose->io_resource;
762 res->flags = IORESOURCE_IO;
763 res->start = pci_addr;
764 break;
765 case 2:
766 case 3:
767 printk(KERN_INFO
768 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
769 cpu_addr, cpu_addr + size - 1, pci_addr,
770 (pci_space & 0x40000000) ? "Prefetch" : "");
771
772
773 if (memno >= 3) {
774 printk(KERN_INFO
775 " \\--> Skipped (too many) !\n");
776 continue;
777 }
778
779 if (pci_addr == 0) {
780 isa_mb = cpu_addr;
781 isa_hole = memno;
782 if (primary || isa_mem_base == 0)
783 isa_mem_base = cpu_addr;
784 hose->isa_mem_phys = cpu_addr;
785 hose->isa_mem_size = size;
786 }
787
788
789
790
791
792 if (memno == 0 ||
793 (isa_hole >= 0 && pci_addr != 0 &&
794 hose->pci_mem_offset == isa_mb))
795 hose->pci_mem_offset = cpu_addr - pci_addr;
796 else if (pci_addr != 0 &&
797 hose->pci_mem_offset != cpu_addr - pci_addr) {
798 printk(KERN_INFO
799 " \\--> Skipped (offset mismatch) !\n");
800 continue;
801 }
802
803
804 res = &hose->mem_resources[memno++];
805 res->flags = IORESOURCE_MEM;
806 if (pci_space & 0x40000000)
807 res->flags |= IORESOURCE_PREFETCH;
808 res->start = cpu_addr;
809 break;
810 }
811 if (res != NULL) {
812 res->name = dev->full_name;
813 res->end = res->start + size - 1;
814 res->parent = NULL;
815 res->sibling = NULL;
816 res->child = NULL;
817 }
818 }
819
820
821
822
823
824 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
825 unsigned int next = isa_hole + 1;
826 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
827 if (next < memno)
828 memmove(&hose->mem_resources[isa_hole],
829 &hose->mem_resources[next],
830 sizeof(struct resource) * (memno - next));
831 hose->mem_resources[--memno].flags = 0;
832 }
833}
834
835
836int pci_proc_domain(struct pci_bus *bus)
837{
838 struct pci_controller *hose = pci_bus_to_host(bus);
839
840 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
841 return 0;
842 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
843 return hose->global_number != 0;
844 return 1;
845}
846
847
848
849
850static void pcibios_fixup_resources(struct pci_dev *dev)
851{
852 struct pci_controller *hose = pci_bus_to_host(dev->bus);
853 int i;
854
855 if (!hose) {
856 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
857 pci_name(dev));
858 return;
859 }
860 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
861 struct resource *res = dev->resource + i;
862 if (!res->flags)
863 continue;
864
865
866
867
868
869
870 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
871 (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
872
873 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
874 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
875 "is unassigned\n",
876 pci_name(dev), i,
877 (unsigned long long)res->start,
878 (unsigned long long)res->end,
879 (unsigned int)res->flags);
880 res->end -= res->start;
881 res->start = 0;
882 res->flags |= IORESOURCE_UNSET;
883 continue;
884 }
885
886 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
887 pci_name(dev), i,
888 (unsigned long long)res->start,\
889 (unsigned long long)res->end,
890 (unsigned int)res->flags);
891 }
892
893
894 if (ppc_md.pcibios_fixup_resources)
895 ppc_md.pcibios_fixup_resources(dev);
896}
897DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
898
899
900
901
902
903
904static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
905 struct resource *res)
906{
907 struct pci_controller *hose = pci_bus_to_host(bus);
908 struct pci_dev *dev = bus->self;
909 resource_size_t offset;
910 u16 command;
911 int i;
912
913
914 if (pci_has_flag(PCI_PROBE_ONLY))
915 return 0;
916
917
918 if (res->flags & IORESOURCE_MEM) {
919
920
921
922 if (res->start != hose->pci_mem_offset)
923 return 0;
924
925
926
927
928 pci_read_config_word(dev, PCI_COMMAND, &command);
929 if ((command & PCI_COMMAND_MEMORY) == 0)
930 return 1;
931
932
933
934
935
936 for (i = 0; i < 3; i++) {
937 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
938 hose->mem_resources[i].start == hose->pci_mem_offset)
939 return 0;
940 }
941
942
943
944
945 return 1;
946 } else {
947
948 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
949 if (((res->start - offset) & 0xfffffffful) != 0)
950 return 0;
951
952
953
954
955
956
957 pci_read_config_word(dev, PCI_COMMAND, &command);
958 if (command & PCI_COMMAND_IO)
959 return 0;
960
961
962
963
964 return 1;
965 }
966}
967
968
969static void pcibios_fixup_bridge(struct pci_bus *bus)
970{
971 struct resource *res;
972 int i;
973
974 struct pci_dev *dev = bus->self;
975
976 pci_bus_for_each_resource(bus, res, i) {
977 if (!res || !res->flags)
978 continue;
979 if (i >= 3 && bus->self->transparent)
980 continue;
981
982
983
984
985
986 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
987 res->flags |= IORESOURCE_UNSET;
988 res->start = 0;
989 res->end = -1;
990 continue;
991 }
992
993 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
994 pci_name(dev), i,
995 (unsigned long long)res->start,\
996 (unsigned long long)res->end,
997 (unsigned int)res->flags);
998
999
1000
1001
1002 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1003 res->flags = 0;
1004 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1005 }
1006 }
1007}
1008
1009void pcibios_setup_bus_self(struct pci_bus *bus)
1010{
1011
1012 if (bus->self != NULL)
1013 pcibios_fixup_bridge(bus);
1014
1015
1016
1017
1018 if (ppc_md.pcibios_fixup_bus)
1019 ppc_md.pcibios_fixup_bus(bus);
1020
1021
1022 if (ppc_md.pci_dma_bus_setup)
1023 ppc_md.pci_dma_bus_setup(bus);
1024}
1025
1026void pcibios_setup_bus_devices(struct pci_bus *bus)
1027{
1028 struct pci_dev *dev;
1029
1030 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1031 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1032
1033 list_for_each_entry(dev, &bus->devices, bus_list) {
1034
1035
1036
1037 if (dev->is_added)
1038 continue;
1039
1040
1041
1042
1043 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1044
1045
1046 set_dma_ops(&dev->dev, pci_dma_ops);
1047 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1048
1049
1050 if (ppc_md.pci_dma_dev_setup)
1051 ppc_md.pci_dma_dev_setup(dev);
1052
1053
1054 pci_read_irq_line(dev);
1055 if (ppc_md.pci_irq_fixup)
1056 ppc_md.pci_irq_fixup(dev);
1057 }
1058}
1059
1060void pcibios_set_master(struct pci_dev *dev)
1061{
1062
1063}
1064
1065void pcibios_fixup_bus(struct pci_bus *bus)
1066{
1067
1068
1069
1070
1071 if (bus->self != NULL)
1072 pci_read_bridge_bases(bus);
1073
1074
1075 pcibios_setup_bus_self(bus);
1076
1077
1078 pcibios_setup_bus_devices(bus);
1079}
1080EXPORT_SYMBOL(pcibios_fixup_bus);
1081
1082void pci_fixup_cardbus(struct pci_bus *bus)
1083{
1084
1085 pcibios_setup_bus_devices(bus);
1086}
1087
1088
1089static int skip_isa_ioresource_align(struct pci_dev *dev)
1090{
1091 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1092 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1093 return 1;
1094 return 0;
1095}
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1111 resource_size_t size, resource_size_t align)
1112{
1113 struct pci_dev *dev = data;
1114 resource_size_t start = res->start;
1115
1116 if (res->flags & IORESOURCE_IO) {
1117 if (skip_isa_ioresource_align(dev))
1118 return start;
1119 if (start & 0x300)
1120 start = (start + 0x3ff) & ~0x3ff;
1121 }
1122
1123 return start;
1124}
1125EXPORT_SYMBOL(pcibios_align_resource);
1126
1127
1128
1129
1130
1131static int reparent_resources(struct resource *parent,
1132 struct resource *res)
1133{
1134 struct resource *p, **pp;
1135 struct resource **firstpp = NULL;
1136
1137 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1138 if (p->end < res->start)
1139 continue;
1140 if (res->end < p->start)
1141 break;
1142 if (p->start < res->start || p->end > res->end)
1143 return -1;
1144 if (firstpp == NULL)
1145 firstpp = pp;
1146 }
1147 if (firstpp == NULL)
1148 return -1;
1149 res->parent = parent;
1150 res->child = *firstpp;
1151 res->sibling = *pp;
1152 *firstpp = res;
1153 *pp = NULL;
1154 for (p = res->child; p != NULL; p = p->sibling) {
1155 p->parent = res;
1156 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1157 p->name,
1158 (unsigned long long)p->start,
1159 (unsigned long long)p->end, res->name);
1160 }
1161 return 0;
1162}
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197void pcibios_allocate_bus_resources(struct pci_bus *bus)
1198{
1199 struct pci_bus *b;
1200 int i;
1201 struct resource *res, *pr;
1202
1203 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1204 pci_domain_nr(bus), bus->number);
1205
1206 pci_bus_for_each_resource(bus, res, i) {
1207 if (!res || !res->flags || res->start > res->end || res->parent)
1208 continue;
1209
1210
1211 if (res->flags & IORESOURCE_UNSET)
1212 goto clear_resource;
1213
1214 if (bus->parent == NULL)
1215 pr = (res->flags & IORESOURCE_IO) ?
1216 &ioport_resource : &iomem_resource;
1217 else {
1218 pr = pci_find_parent_resource(bus->self, res);
1219 if (pr == res) {
1220
1221
1222
1223
1224 continue;
1225 }
1226 }
1227
1228 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1229 "[0x%x], parent %p (%s)\n",
1230 bus->self ? pci_name(bus->self) : "PHB",
1231 bus->number, i,
1232 (unsigned long long)res->start,
1233 (unsigned long long)res->end,
1234 (unsigned int)res->flags,
1235 pr, (pr && pr->name) ? pr->name : "nil");
1236
1237 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1238 if (request_resource(pr, res) == 0)
1239 continue;
1240
1241
1242
1243
1244
1245 if (reparent_resources(pr, res) == 0)
1246 continue;
1247 }
1248 pr_warning("PCI: Cannot allocate resource region "
1249 "%d of PCI bridge %d, will remap\n", i, bus->number);
1250 clear_resource:
1251
1252
1253
1254
1255
1256
1257 res->start = 0;
1258 res->end = -1;
1259 res->flags = 0;
1260 }
1261
1262 list_for_each_entry(b, &bus->children, node)
1263 pcibios_allocate_bus_resources(b);
1264}
1265
1266static inline void alloc_resource(struct pci_dev *dev, int idx)
1267{
1268 struct resource *pr, *r = &dev->resource[idx];
1269
1270 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1271 pci_name(dev), idx,
1272 (unsigned long long)r->start,
1273 (unsigned long long)r->end,
1274 (unsigned int)r->flags);
1275
1276 pr = pci_find_parent_resource(dev, r);
1277 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1278 request_resource(pr, r) < 0) {
1279 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1280 " of device %s, will remap\n", idx, pci_name(dev));
1281 if (pr)
1282 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1283 pr,
1284 (unsigned long long)pr->start,
1285 (unsigned long long)pr->end,
1286 (unsigned int)pr->flags);
1287
1288 r->flags |= IORESOURCE_UNSET;
1289 r->end -= r->start;
1290 r->start = 0;
1291 }
1292}
1293
1294static void __init pcibios_allocate_resources(int pass)
1295{
1296 struct pci_dev *dev = NULL;
1297 int idx, disabled;
1298 u16 command;
1299 struct resource *r;
1300
1301 for_each_pci_dev(dev) {
1302 pci_read_config_word(dev, PCI_COMMAND, &command);
1303 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1304 r = &dev->resource[idx];
1305 if (r->parent)
1306 continue;
1307 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1308 continue;
1309
1310
1311
1312 if (idx == PCI_ROM_RESOURCE )
1313 disabled = 1;
1314 if (r->flags & IORESOURCE_IO)
1315 disabled = !(command & PCI_COMMAND_IO);
1316 else
1317 disabled = !(command & PCI_COMMAND_MEMORY);
1318 if (pass == disabled)
1319 alloc_resource(dev, idx);
1320 }
1321 if (pass)
1322 continue;
1323 r = &dev->resource[PCI_ROM_RESOURCE];
1324 if (r->flags) {
1325
1326
1327
1328 u32 reg;
1329 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1330 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1331 pr_debug("PCI: Switching off ROM of %s\n",
1332 pci_name(dev));
1333 r->flags &= ~IORESOURCE_ROM_ENABLE;
1334 pci_write_config_dword(dev, dev->rom_base_reg,
1335 reg & ~PCI_ROM_ADDRESS_ENABLE);
1336 }
1337 }
1338 }
1339}
1340
1341static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1342{
1343 struct pci_controller *hose = pci_bus_to_host(bus);
1344 resource_size_t offset;
1345 struct resource *res, *pres;
1346 int i;
1347
1348 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1349
1350
1351 if (!(hose->io_resource.flags & IORESOURCE_IO))
1352 goto no_io;
1353 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1354 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1355 BUG_ON(res == NULL);
1356 res->name = "Legacy IO";
1357 res->flags = IORESOURCE_IO;
1358 res->start = offset;
1359 res->end = (offset + 0xfff) & 0xfffffffful;
1360 pr_debug("Candidate legacy IO: %pR\n", res);
1361 if (request_resource(&hose->io_resource, res)) {
1362 printk(KERN_DEBUG
1363 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1364 pci_domain_nr(bus), bus->number, res);
1365 kfree(res);
1366 }
1367
1368 no_io:
1369
1370 offset = hose->pci_mem_offset;
1371 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1372 for (i = 0; i < 3; i++) {
1373 pres = &hose->mem_resources[i];
1374 if (!(pres->flags & IORESOURCE_MEM))
1375 continue;
1376 pr_debug("hose mem res: %pR\n", pres);
1377 if ((pres->start - offset) <= 0xa0000 &&
1378 (pres->end - offset) >= 0xbffff)
1379 break;
1380 }
1381 if (i >= 3)
1382 return;
1383 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1384 BUG_ON(res == NULL);
1385 res->name = "Legacy VGA memory";
1386 res->flags = IORESOURCE_MEM;
1387 res->start = 0xa0000 + offset;
1388 res->end = 0xbffff + offset;
1389 pr_debug("Candidate VGA memory: %pR\n", res);
1390 if (request_resource(pres, res)) {
1391 printk(KERN_DEBUG
1392 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1393 pci_domain_nr(bus), bus->number, res);
1394 kfree(res);
1395 }
1396}
1397
1398void __init pcibios_resource_survey(void)
1399{
1400 struct pci_bus *b;
1401
1402
1403 list_for_each_entry(b, &pci_root_buses, node)
1404 pcibios_allocate_bus_resources(b);
1405 pcibios_allocate_resources(0);
1406 pcibios_allocate_resources(1);
1407
1408
1409
1410
1411
1412 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1413 list_for_each_entry(b, &pci_root_buses, node)
1414 pcibios_reserve_legacy_regions(b);
1415 }
1416
1417
1418
1419
1420 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1421 pr_debug("PCI: Assigning unassigned resources...\n");
1422 pci_assign_unassigned_resources();
1423 }
1424
1425
1426 if (ppc_md.pcibios_fixup)
1427 ppc_md.pcibios_fixup();
1428}
1429
1430
1431
1432
1433
1434
1435void pcibios_claim_one_bus(struct pci_bus *bus)
1436{
1437 struct pci_dev *dev;
1438 struct pci_bus *child_bus;
1439
1440 list_for_each_entry(dev, &bus->devices, bus_list) {
1441 int i;
1442
1443 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1444 struct resource *r = &dev->resource[i];
1445
1446 if (r->parent || !r->start || !r->flags)
1447 continue;
1448
1449 pr_debug("PCI: Claiming %s: "
1450 "Resource %d: %016llx..%016llx [%x]\n",
1451 pci_name(dev), i,
1452 (unsigned long long)r->start,
1453 (unsigned long long)r->end,
1454 (unsigned int)r->flags);
1455
1456 pci_claim_resource(dev, i);
1457 }
1458 }
1459
1460 list_for_each_entry(child_bus, &bus->children, node)
1461 pcibios_claim_one_bus(child_bus);
1462}
1463
1464
1465
1466
1467
1468
1469
1470
1471void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1472{
1473 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1474 pci_domain_nr(bus), bus->number);
1475
1476
1477 pcibios_allocate_bus_resources(bus);
1478 pcibios_claim_one_bus(bus);
1479
1480
1481 pci_bus_add_devices(bus);
1482
1483
1484 eeh_add_device_tree_late(bus);
1485}
1486EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1487
1488int pcibios_enable_device(struct pci_dev *dev, int mask)
1489{
1490 if (ppc_md.pcibios_enable_device_hook)
1491 if (ppc_md.pcibios_enable_device_hook(dev))
1492 return -EINVAL;
1493
1494 return pci_enable_resources(dev, mask);
1495}
1496
1497resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1498{
1499 return (unsigned long) hose->io_base_virt - _IO_BASE;
1500}
1501
1502static void pcibios_setup_phb_resources(struct pci_controller *hose,
1503 struct list_head *resources)
1504{
1505 struct resource *res;
1506 int i;
1507
1508
1509 res = &hose->io_resource;
1510
1511 if (!res->flags) {
1512 printk(KERN_WARNING "PCI: I/O resource not set for host"
1513 " bridge %s (domain %d)\n",
1514 hose->dn->full_name, hose->global_number);
1515#ifdef CONFIG_PPC32
1516
1517 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1518 res->end = res->start + IO_SPACE_LIMIT;
1519 res->flags = IORESOURCE_IO;
1520#endif
1521 }
1522
1523 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1524 (unsigned long long)res->start,
1525 (unsigned long long)res->end,
1526 (unsigned long)res->flags);
1527 pci_add_resource_offset(resources, res, pcibios_io_space_offset(hose));
1528
1529
1530 for (i = 0; i < 3; ++i) {
1531 res = &hose->mem_resources[i];
1532 if (!res->flags) {
1533 if (i > 0)
1534 continue;
1535 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1536 "host bridge %s (domain %d)\n",
1537 hose->dn->full_name, hose->global_number);
1538#ifdef CONFIG_PPC32
1539
1540 res->start = hose->pci_mem_offset;
1541 res->end = (resource_size_t)-1LL;
1542 res->flags = IORESOURCE_MEM;
1543#endif
1544 }
1545
1546 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i,
1547 (unsigned long long)res->start,
1548 (unsigned long long)res->end,
1549 (unsigned long)res->flags);
1550 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1551 }
1552
1553 pr_debug("PCI: PHB MEM offset = %016llx\n",
1554 (unsigned long long)hose->pci_mem_offset);
1555 pr_debug("PCI: PHB IO offset = %08lx\n",
1556 (unsigned long)hose->io_base_virt - _IO_BASE);
1557
1558}
1559
1560
1561
1562
1563
1564#define NULL_PCI_OP(rw, size, type) \
1565static int \
1566null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1567{ \
1568 return PCIBIOS_DEVICE_NOT_FOUND; \
1569}
1570
1571static int
1572null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1573 int len, u32 *val)
1574{
1575 return PCIBIOS_DEVICE_NOT_FOUND;
1576}
1577
1578static int
1579null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1580 int len, u32 val)
1581{
1582 return PCIBIOS_DEVICE_NOT_FOUND;
1583}
1584
1585static struct pci_ops null_pci_ops =
1586{
1587 .read = null_read_config,
1588 .write = null_write_config,
1589};
1590
1591
1592
1593
1594
1595static struct pci_bus *
1596fake_pci_bus(struct pci_controller *hose, int busnr)
1597{
1598 static struct pci_bus bus;
1599
1600 if (hose == 0) {
1601 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1602 }
1603 bus.number = busnr;
1604 bus.sysdata = hose;
1605 bus.ops = hose? hose->ops: &null_pci_ops;
1606 return &bus;
1607}
1608
1609#define EARLY_PCI_OP(rw, size, type) \
1610int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1611 int devfn, int offset, type value) \
1612{ \
1613 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1614 devfn, offset, value); \
1615}
1616
1617EARLY_PCI_OP(read, byte, u8 *)
1618EARLY_PCI_OP(read, word, u16 *)
1619EARLY_PCI_OP(read, dword, u32 *)
1620EARLY_PCI_OP(write, byte, u8)
1621EARLY_PCI_OP(write, word, u16)
1622EARLY_PCI_OP(write, dword, u32)
1623
1624extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1625int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1626 int cap)
1627{
1628 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1629}
1630
1631struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1632{
1633 struct pci_controller *hose = bus->sysdata;
1634
1635 return of_node_get(hose->dn);
1636}
1637
1638
1639
1640
1641
1642void pcibios_scan_phb(struct pci_controller *hose)
1643{
1644 LIST_HEAD(resources);
1645 struct pci_bus *bus;
1646 struct device_node *node = hose->dn;
1647 int mode;
1648
1649 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1650
1651
1652 pcibios_setup_phb_io_space(hose);
1653
1654
1655 pcibios_setup_phb_resources(hose, &resources);
1656
1657 hose->busn.start = hose->first_busno;
1658 hose->busn.end = hose->last_busno;
1659 hose->busn.flags = IORESOURCE_BUS;
1660 pci_add_resource(&resources, &hose->busn);
1661
1662
1663 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1664 hose->ops, hose, &resources);
1665 if (bus == NULL) {
1666 pr_err("Failed to create bus for PCI domain %04x\n",
1667 hose->global_number);
1668 pci_free_resource_list(&resources);
1669 return;
1670 }
1671 hose->bus = bus;
1672
1673
1674 mode = PCI_PROBE_NORMAL;
1675 if (node && ppc_md.pci_probe_mode)
1676 mode = ppc_md.pci_probe_mode(bus);
1677 pr_debug(" probe mode: %d\n", mode);
1678 if (mode == PCI_PROBE_DEVTREE)
1679 of_scan_bus(node, bus);
1680
1681 if (mode == PCI_PROBE_NORMAL) {
1682 pci_bus_update_busn_res_end(bus, 255);
1683 hose->last_busno = pci_scan_child_bus(bus);
1684 pci_bus_update_busn_res_end(bus, hose->last_busno);
1685 }
1686
1687
1688
1689
1690 if (ppc_md.pcibios_fixup_phb)
1691 ppc_md.pcibios_fixup_phb(hose);
1692
1693
1694 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1695 struct pci_bus *child;
1696 list_for_each_entry(child, &bus->children, node) {
1697 struct pci_dev *self = child->self;
1698 if (!self)
1699 continue;
1700 pcie_bus_configure_settings(child, self->pcie_mpss);
1701 }
1702 }
1703}
1704
1705static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1706{
1707 int i, class = dev->class >> 8;
1708
1709 int prog_if = dev->class & 0xf;
1710
1711 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1712 class == PCI_CLASS_BRIDGE_OTHER) &&
1713 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1714 (prog_if == 0) &&
1715 (dev->bus->parent == NULL)) {
1716 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1717 dev->resource[i].start = 0;
1718 dev->resource[i].end = 0;
1719 dev->resource[i].flags = 0;
1720 }
1721 }
1722}
1723DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1724DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1725