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15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/amba/bus.h>
18#include <linux/atomic.h>
19#include <linux/slab.h>
20#include <linux/interrupt.h>
21#include <linux/i2c.h>
22#include <linux/err.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25#include <linux/pm_runtime.h>
26#include <linux/platform_data/i2c-nomadik.h>
27#include <linux/of.h>
28#include <linux/of_i2c.h>
29
30#define DRIVER_NAME "nmk-i2c"
31
32
33#define I2C_CR (0x000)
34#define I2C_SCR (0x004)
35#define I2C_HSMCR (0x008)
36#define I2C_MCR (0x00C)
37#define I2C_TFR (0x010)
38#define I2C_SR (0x014)
39#define I2C_RFR (0x018)
40#define I2C_TFTR (0x01C)
41#define I2C_RFTR (0x020)
42#define I2C_DMAR (0x024)
43#define I2C_BRCR (0x028)
44#define I2C_IMSCR (0x02C)
45#define I2C_RISR (0x030)
46#define I2C_MISR (0x034)
47#define I2C_ICR (0x038)
48
49
50#define I2C_CR_PE (0x1 << 0)
51#define I2C_CR_OM (0x3 << 1)
52#define I2C_CR_SAM (0x1 << 3)
53#define I2C_CR_SM (0x3 << 4)
54#define I2C_CR_SGCM (0x1 << 6)
55#define I2C_CR_FTX (0x1 << 7)
56#define I2C_CR_FRX (0x1 << 8)
57#define I2C_CR_DMA_TX_EN (0x1 << 9)
58#define I2C_CR_DMA_RX_EN (0x1 << 10)
59#define I2C_CR_DMA_SLE (0x1 << 11)
60#define I2C_CR_LM (0x1 << 12)
61#define I2C_CR_FON (0x3 << 13)
62#define I2C_CR_FS (0x3 << 15)
63
64
65#define I2C_MCR_OP (0x1 << 0)
66#define I2C_MCR_A7 (0x7f << 1)
67#define I2C_MCR_EA10 (0x7 << 8)
68#define I2C_MCR_SB (0x1 << 11)
69#define I2C_MCR_AM (0x3 << 12)
70#define I2C_MCR_STOP (0x1 << 14)
71#define I2C_MCR_LENGTH (0x7ff << 15)
72
73
74#define I2C_SR_OP (0x3 << 0)
75#define I2C_SR_STATUS (0x3 << 2)
76#define I2C_SR_CAUSE (0x7 << 4)
77#define I2C_SR_TYPE (0x3 << 7)
78#define I2C_SR_LENGTH (0x7ff << 9)
79
80
81#define I2C_IT_TXFE (0x1 << 0)
82#define I2C_IT_TXFNE (0x1 << 1)
83#define I2C_IT_TXFF (0x1 << 2)
84#define I2C_IT_TXFOVR (0x1 << 3)
85#define I2C_IT_RXFE (0x1 << 4)
86#define I2C_IT_RXFNF (0x1 << 5)
87#define I2C_IT_RXFF (0x1 << 6)
88#define I2C_IT_RFSR (0x1 << 16)
89#define I2C_IT_RFSE (0x1 << 17)
90#define I2C_IT_WTSR (0x1 << 18)
91#define I2C_IT_MTD (0x1 << 19)
92#define I2C_IT_STD (0x1 << 20)
93#define I2C_IT_MAL (0x1 << 24)
94#define I2C_IT_BERR (0x1 << 25)
95#define I2C_IT_MTDWS (0x1 << 28)
96
97#define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
98
99
100#define I2C_CLEAR_ALL_INTS 0x131f007f
101
102
103#define IRQ_MASK(mask) (mask & 0x1fffffff)
104
105
106#define MAX_I2C_FIFO_THRESHOLD 15
107
108enum i2c_status {
109 I2C_NOP,
110 I2C_ON_GOING,
111 I2C_OK,
112 I2C_ABORT
113};
114
115
116enum i2c_operation {
117 I2C_NO_OPERATION = 0xff,
118 I2C_WRITE = 0x00,
119 I2C_READ = 0x01
120};
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129
130struct i2c_nmk_client {
131 unsigned short slave_adr;
132 unsigned long count;
133 unsigned char *buffer;
134 unsigned long xfer_bytes;
135 enum i2c_operation operation;
136};
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151
152struct nmk_i2c_dev {
153 struct amba_device *adev;
154 struct i2c_adapter adap;
155 int irq;
156 void __iomem *virtbase;
157 struct clk *clk;
158 struct nmk_i2c_controller cfg;
159 struct i2c_nmk_client cli;
160 int stop;
161 struct completion xfer_complete;
162 int result;
163 bool busy;
164};
165
166
167static const char *abort_causes[] = {
168 "no ack received after address transmission",
169 "no ack received during data phase",
170 "ack received after xmission of master code",
171 "master lost arbitration",
172 "slave restarts",
173 "slave reset",
174 "overflow, maxsize is 2047 bytes",
175};
176
177static inline void i2c_set_bit(void __iomem *reg, u32 mask)
178{
179 writel(readl(reg) | mask, reg);
180}
181
182static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
183{
184 writel(readl(reg) & ~mask, reg);
185}
186
187
188
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190
191
192
193
194static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
195{
196#define LOOP_ATTEMPTS 10
197 int i;
198 unsigned long timeout;
199
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205
206
207 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
208
209 for (i = 0; i < LOOP_ATTEMPTS; i++) {
210 timeout = jiffies + dev->adap.timeout;
211
212 while (!time_after(jiffies, timeout)) {
213 if ((readl(dev->virtbase + I2C_CR) &
214 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
215 return 0;
216 }
217 }
218
219 dev_err(&dev->adev->dev,
220 "flushing operation timed out giving up after %d attempts",
221 LOOP_ATTEMPTS);
222
223 return -ETIMEDOUT;
224}
225
226
227
228
229
230static void disable_all_interrupts(struct nmk_i2c_dev *dev)
231{
232 u32 mask = IRQ_MASK(0);
233 writel(mask, dev->virtbase + I2C_IMSCR);
234}
235
236
237
238
239
240static void clear_all_interrupts(struct nmk_i2c_dev *dev)
241{
242 u32 mask;
243 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
244 writel(mask, dev->virtbase + I2C_ICR);
245}
246
247
248
249
250
251static int init_hw(struct nmk_i2c_dev *dev)
252{
253 int stat;
254
255 stat = flush_i2c_fifo(dev);
256 if (stat)
257 goto exit;
258
259
260 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
261
262 disable_all_interrupts(dev);
263
264 clear_all_interrupts(dev);
265
266 dev->cli.operation = I2C_NO_OPERATION;
267
268exit:
269 return stat;
270}
271
272
273#define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
274
275
276
277
278
279
280static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
281{
282 u32 mcr = 0;
283 unsigned short slave_adr_3msb_bits;
284
285 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
286
287 if (unlikely(flags & I2C_M_TEN)) {
288
289 mcr |= GEN_MASK(2, I2C_MCR_AM, 12);
290
291
292
293
294
295
296 slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7;
297
298 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8);
299 } else {
300
301 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
302 }
303
304
305 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
306
307
308 if (dev->cli.operation == I2C_WRITE)
309 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
310 else
311 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
312
313
314 if (dev->stop)
315 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
316 else
317 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
318
319 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
320
321 return mcr;
322}
323
324
325
326
327
328static void setup_i2c_controller(struct nmk_i2c_dev *dev)
329{
330 u32 brcr1, brcr2;
331 u32 i2c_clk, div;
332
333 writel(0x0, dev->virtbase + I2C_CR);
334 writel(0x0, dev->virtbase + I2C_HSMCR);
335 writel(0x0, dev->virtbase + I2C_TFTR);
336 writel(0x0, dev->virtbase + I2C_RFTR);
337 writel(0x0, dev->virtbase + I2C_DMAR);
338
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344
345
346
347
348 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR);
349
350 i2c_clk = clk_get_rate(dev->clk);
351
352
353
354
355
356
357 div = (dev->cfg.clk_freq > 100000) ? 3 : 2;
358
359
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361
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363
364
365
366 brcr1 = 0 << 16;
367 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff;
368
369
370 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
371
372
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375
376
377
378 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) {
379 dev_err(&dev->adev->dev,
380 "do not support this mode defaulting to std. mode\n");
381 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
382 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
383 writel(I2C_FREQ_MODE_STANDARD << 4,
384 dev->virtbase + I2C_CR);
385 }
386 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR);
387
388
389 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR);
390 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR);
391}
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401
402static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
403{
404 u32 status = 0;
405 u32 mcr;
406 u32 irq_mask = 0;
407 int timeout;
408
409 mcr = load_i2c_mcr_reg(dev, flags);
410 writel(mcr, dev->virtbase + I2C_MCR);
411
412
413 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
414 dev->virtbase + I2C_CR);
415
416
417 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
418
419 init_completion(&dev->xfer_complete);
420
421
422 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
423 I2C_IT_MAL | I2C_IT_BERR);
424
425 if (dev->stop)
426 irq_mask |= I2C_IT_MTD;
427 else
428 irq_mask |= I2C_IT_MTDWS;
429
430 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
431
432 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
433 dev->virtbase + I2C_IMSCR);
434
435 timeout = wait_for_completion_timeout(
436 &dev->xfer_complete, dev->adap.timeout);
437
438 if (timeout == 0) {
439
440 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",
441 dev->cli.slave_adr);
442 status = -ETIMEDOUT;
443 }
444 return status;
445}
446
447static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
448{
449 int count;
450
451 for (count = (no_bytes - 2);
452 (count > 0) &&
453 (dev->cli.count != 0);
454 count--) {
455
456 writeb(*dev->cli.buffer,
457 dev->virtbase + I2C_TFR);
458 dev->cli.buffer++;
459 dev->cli.count--;
460 dev->cli.xfer_bytes++;
461 }
462
463}
464
465
466
467
468
469
470
471
472static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
473{
474 u32 status = 0;
475 u32 mcr;
476 u32 irq_mask = 0;
477 int timeout;
478
479 mcr = load_i2c_mcr_reg(dev, flags);
480
481 writel(mcr, dev->virtbase + I2C_MCR);
482
483
484 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
485 dev->virtbase + I2C_CR);
486
487
488 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
489
490 init_completion(&dev->xfer_complete);
491
492
493 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
494
495
496 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
497
498 if (dev->cli.count != 0)
499 irq_mask |= I2C_IT_TXFNE;
500
501
502
503
504
505
506 if (dev->stop)
507 irq_mask |= I2C_IT_MTD;
508 else
509 irq_mask |= I2C_IT_MTDWS;
510
511 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
512
513 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
514 dev->virtbase + I2C_IMSCR);
515
516 timeout = wait_for_completion_timeout(
517 &dev->xfer_complete, dev->adap.timeout);
518
519 if (timeout == 0) {
520
521 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",
522 dev->cli.slave_adr);
523 status = -ETIMEDOUT;
524 }
525
526 return status;
527}
528
529
530
531
532
533
534static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
535{
536 int status;
537
538 if (flags & I2C_M_RD) {
539
540 dev->cli.operation = I2C_READ;
541 status = read_i2c(dev, flags);
542 } else {
543
544 dev->cli.operation = I2C_WRITE;
545 status = write_i2c(dev, flags);
546 }
547
548 if (status || (dev->result)) {
549 u32 i2c_sr;
550 u32 cause;
551
552 i2c_sr = readl(dev->virtbase + I2C_SR);
553
554
555
556
557 if (((i2c_sr >> 2) & 0x3) == 0x3) {
558
559 cause = (i2c_sr >> 4) & 0x7;
560 dev_err(&dev->adev->dev, "%s\n",
561 cause >= ARRAY_SIZE(abort_causes) ?
562 "unknown reason" :
563 abort_causes[cause]);
564 }
565
566 (void) init_hw(dev);
567
568 status = status ? status : dev->result;
569 }
570
571 return status;
572}
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621static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
622 struct i2c_msg msgs[], int num_msgs)
623{
624 int status;
625 int i;
626 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
627 int j;
628
629 dev->busy = true;
630
631 pm_runtime_get_sync(&dev->adev->dev);
632
633 status = clk_prepare_enable(dev->clk);
634 if (status) {
635 dev_err(&dev->adev->dev, "can't prepare_enable clock\n");
636 goto out_clk;
637 }
638
639 status = init_hw(dev);
640 if (status)
641 goto out;
642
643
644 for (j = 0; j < 3; j++) {
645
646 setup_i2c_controller(dev);
647
648 for (i = 0; i < num_msgs; i++) {
649 dev->cli.slave_adr = msgs[i].addr;
650 dev->cli.buffer = msgs[i].buf;
651 dev->cli.count = msgs[i].len;
652 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
653 dev->result = 0;
654
655 status = nmk_i2c_xfer_one(dev, msgs[i].flags);
656 if (status != 0)
657 break;
658 }
659 if (status == 0)
660 break;
661 }
662
663out:
664 clk_disable_unprepare(dev->clk);
665out_clk:
666 pm_runtime_put_sync(&dev->adev->dev);
667
668 dev->busy = false;
669
670
671 if (status)
672 return status;
673 else
674 return num_msgs;
675}
676
677
678
679
680
681
682static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
683{
684 irq = IRQ_MASK(irq);
685 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
686 dev->virtbase + I2C_IMSCR);
687 return 0;
688}
689
690
691
692
693
694
695
696
697
698
699
700
701static irqreturn_t i2c_irq_handler(int irq, void *arg)
702{
703 struct nmk_i2c_dev *dev = arg;
704 u32 tft, rft;
705 u32 count;
706 u32 misr;
707 u32 src = 0;
708
709
710 tft = readl(dev->virtbase + I2C_TFTR);
711 rft = readl(dev->virtbase + I2C_RFTR);
712
713
714 misr = readl(dev->virtbase + I2C_MISR);
715
716 src = __ffs(misr);
717 switch ((1 << src)) {
718
719
720 case I2C_IT_TXFNE:
721 {
722 if (dev->cli.operation == I2C_READ) {
723
724
725
726
727 disable_interrupts(dev, I2C_IT_TXFNE);
728 } else {
729 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
730
731
732
733
734 if (dev->cli.count == 0)
735 disable_interrupts(dev, I2C_IT_TXFNE);
736 }
737 }
738 break;
739
740
741
742
743
744
745
746 case I2C_IT_RXFNF:
747 for (count = rft; count > 0; count--) {
748
749 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
750 dev->cli.buffer++;
751 }
752 dev->cli.count -= rft;
753 dev->cli.xfer_bytes += rft;
754 break;
755
756
757 case I2C_IT_RXFF:
758 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
759 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
760 dev->cli.buffer++;
761 }
762 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
763 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
764 break;
765
766
767 case I2C_IT_MTD:
768 case I2C_IT_MTDWS:
769 if (dev->cli.operation == I2C_READ) {
770 while (!(readl(dev->virtbase + I2C_RISR)
771 & I2C_IT_RXFE)) {
772 if (dev->cli.count == 0)
773 break;
774 *dev->cli.buffer =
775 readb(dev->virtbase + I2C_RFR);
776 dev->cli.buffer++;
777 dev->cli.count--;
778 dev->cli.xfer_bytes++;
779 }
780 }
781
782 disable_all_interrupts(dev);
783 clear_all_interrupts(dev);
784
785 if (dev->cli.count) {
786 dev->result = -EIO;
787 dev_err(&dev->adev->dev,
788 "%lu bytes still remain to be xfered\n",
789 dev->cli.count);
790 (void) init_hw(dev);
791 }
792 complete(&dev->xfer_complete);
793
794 break;
795
796
797 case I2C_IT_MAL:
798 dev->result = -EIO;
799 (void) init_hw(dev);
800
801 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
802 complete(&dev->xfer_complete);
803
804 break;
805
806
807
808
809
810
811 case I2C_IT_BERR:
812 dev->result = -EIO;
813
814 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
815 (void) init_hw(dev);
816
817 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
818 complete(&dev->xfer_complete);
819
820 break;
821
822
823
824
825
826
827 case I2C_IT_TXFOVR:
828 dev->result = -EIO;
829 (void) init_hw(dev);
830
831 dev_err(&dev->adev->dev, "Tx Fifo Over run\n");
832 complete(&dev->xfer_complete);
833
834 break;
835
836
837 case I2C_IT_TXFE:
838 case I2C_IT_TXFF:
839 case I2C_IT_RXFE:
840 case I2C_IT_RFSR:
841 case I2C_IT_RFSE:
842 case I2C_IT_WTSR:
843 case I2C_IT_STD:
844 dev_err(&dev->adev->dev, "unhandled Interrupt\n");
845 break;
846 default:
847 dev_err(&dev->adev->dev, "spurious Interrupt..\n");
848 break;
849 }
850
851 return IRQ_HANDLED;
852}
853
854
855#ifdef CONFIG_PM
856static int nmk_i2c_suspend(struct device *dev)
857{
858 struct amba_device *adev = to_amba_device(dev);
859 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
860
861 if (nmk_i2c->busy)
862 return -EBUSY;
863
864 return 0;
865}
866
867static int nmk_i2c_resume(struct device *dev)
868{
869 return 0;
870}
871#else
872#define nmk_i2c_suspend NULL
873#define nmk_i2c_resume NULL
874#endif
875
876
877
878
879
880
881static const struct dev_pm_ops nmk_i2c_pm = {
882 .suspend_noirq = nmk_i2c_suspend,
883 .resume_noirq = nmk_i2c_resume,
884};
885
886static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
887{
888 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
889}
890
891static const struct i2c_algorithm nmk_i2c_algo = {
892 .master_xfer = nmk_i2c_xfer,
893 .functionality = nmk_i2c_functionality
894};
895
896static struct nmk_i2c_controller u8500_i2c = {
897
898
899
900
901 .slsu = 0xe,
902 .tft = 1,
903 .rft = 8,
904 .clk_freq = 400000,
905 .timeout = 200,
906 .sm = I2C_FREQ_MODE_FAST,
907};
908
909static void nmk_i2c_of_probe(struct device_node *np,
910 struct nmk_i2c_controller *pdata)
911{
912 of_property_read_u32(np, "clock-frequency", &pdata->clk_freq);
913
914
915 if (pdata->clk_freq <= 100000)
916 pdata->sm = I2C_FREQ_MODE_STANDARD;
917 else
918 pdata->sm = I2C_FREQ_MODE_FAST;
919}
920
921static atomic_t adapter_id = ATOMIC_INIT(0);
922
923static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
924{
925 int ret = 0;
926 struct nmk_i2c_controller *pdata = adev->dev.platform_data;
927 struct device_node *np = adev->dev.of_node;
928 struct nmk_i2c_dev *dev;
929 struct i2c_adapter *adap;
930
931 if (!pdata) {
932 if (np) {
933 pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL);
934 if (!pdata) {
935 ret = -ENOMEM;
936 goto err_no_mem;
937 }
938
939 memcpy(pdata, &u8500_i2c, sizeof(struct nmk_i2c_controller));
940 nmk_i2c_of_probe(np, pdata);
941 } else
942
943 pdata = &u8500_i2c;
944 }
945
946 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
947 if (!dev) {
948 dev_err(&adev->dev, "cannot allocate memory\n");
949 ret = -ENOMEM;
950 goto err_no_mem;
951 }
952 dev->busy = false;
953 dev->adev = adev;
954 amba_set_drvdata(adev, dev);
955
956 dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
957 if (!dev->virtbase) {
958 ret = -ENOMEM;
959 goto err_no_ioremap;
960 }
961
962 dev->irq = adev->irq[0];
963 ret = request_irq(dev->irq, i2c_irq_handler, 0,
964 DRIVER_NAME, dev);
965 if (ret) {
966 dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq);
967 goto err_irq;
968 }
969
970 pm_suspend_ignore_children(&adev->dev, true);
971
972 dev->clk = clk_get(&adev->dev, NULL);
973 if (IS_ERR(dev->clk)) {
974 dev_err(&adev->dev, "could not get i2c clock\n");
975 ret = PTR_ERR(dev->clk);
976 goto err_no_clk;
977 }
978
979 adap = &dev->adap;
980 adap->dev.of_node = np;
981 adap->dev.parent = &adev->dev;
982 adap->owner = THIS_MODULE;
983 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
984 adap->algo = &nmk_i2c_algo;
985 adap->timeout = msecs_to_jiffies(pdata->timeout);
986 adap->nr = atomic_read(&adapter_id);
987 snprintf(adap->name, sizeof(adap->name),
988 "Nomadik I2C%d at %pR", adap->nr, &adev->res);
989 atomic_inc(&adapter_id);
990
991
992 dev->cfg.clk_freq = pdata->clk_freq;
993 dev->cfg.slsu = pdata->slsu;
994 dev->cfg.tft = pdata->tft;
995 dev->cfg.rft = pdata->rft;
996 dev->cfg.sm = pdata->sm;
997
998 i2c_set_adapdata(adap, dev);
999
1000 dev_info(&adev->dev,
1001 "initialize %s on virtual base %p\n",
1002 adap->name, dev->virtbase);
1003
1004 ret = i2c_add_numbered_adapter(adap);
1005 if (ret) {
1006 dev_err(&adev->dev, "failed to add adapter\n");
1007 goto err_add_adap;
1008 }
1009
1010 of_i2c_register_devices(adap);
1011
1012 pm_runtime_put(&adev->dev);
1013
1014 return 0;
1015
1016 err_add_adap:
1017 clk_put(dev->clk);
1018 err_no_clk:
1019 free_irq(dev->irq, dev);
1020 err_irq:
1021 iounmap(dev->virtbase);
1022 err_no_ioremap:
1023 amba_set_drvdata(adev, NULL);
1024 kfree(dev);
1025 err_no_mem:
1026
1027 return ret;
1028}
1029
1030static int nmk_i2c_remove(struct amba_device *adev)
1031{
1032 struct resource *res = &adev->res;
1033 struct nmk_i2c_dev *dev = amba_get_drvdata(adev);
1034
1035 i2c_del_adapter(&dev->adap);
1036 flush_i2c_fifo(dev);
1037 disable_all_interrupts(dev);
1038 clear_all_interrupts(dev);
1039
1040 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
1041 free_irq(dev->irq, dev);
1042 iounmap(dev->virtbase);
1043 if (res)
1044 release_mem_region(res->start, resource_size(res));
1045 clk_put(dev->clk);
1046 pm_runtime_disable(&adev->dev);
1047 amba_set_drvdata(adev, NULL);
1048 kfree(dev);
1049
1050 return 0;
1051}
1052
1053static struct amba_id nmk_i2c_ids[] = {
1054 {
1055 .id = 0x00180024,
1056 .mask = 0x00ffffff,
1057 },
1058 {
1059 .id = 0x00380024,
1060 .mask = 0x00ffffff,
1061 },
1062 {},
1063};
1064
1065MODULE_DEVICE_TABLE(amba, nmk_i2c_ids);
1066
1067static struct amba_driver nmk_i2c_driver = {
1068 .drv = {
1069 .owner = THIS_MODULE,
1070 .name = DRIVER_NAME,
1071 .pm = &nmk_i2c_pm,
1072 },
1073 .id_table = nmk_i2c_ids,
1074 .probe = nmk_i2c_probe,
1075 .remove = nmk_i2c_remove,
1076};
1077
1078static int __init nmk_i2c_init(void)
1079{
1080 return amba_driver_register(&nmk_i2c_driver);
1081}
1082
1083static void __exit nmk_i2c_exit(void)
1084{
1085 amba_driver_unregister(&nmk_i2c_driver);
1086}
1087
1088subsys_initcall(nmk_i2c_init);
1089module_exit(nmk_i2c_exit);
1090
1091MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
1092MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1093MODULE_LICENSE("GPL");
1094