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12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/types.h>
16#include <linux/delay.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19#include <linux/ioport.h>
20#include <linux/init.h>
21#include <linux/serio.h>
22#include <linux/err.h>
23#include <linux/rcupdate.h>
24#include <linux/platform_device.h>
25#include <linux/i8042.h>
26#include <linux/slab.h>
27
28#include <asm/io.h>
29
30MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
31MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
32MODULE_LICENSE("GPL");
33
34static bool i8042_nokbd;
35module_param_named(nokbd, i8042_nokbd, bool, 0);
36MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
37
38static bool i8042_noaux;
39module_param_named(noaux, i8042_noaux, bool, 0);
40MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
41
42static bool i8042_nomux;
43module_param_named(nomux, i8042_nomux, bool, 0);
44MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present.");
45
46static bool i8042_unlock;
47module_param_named(unlock, i8042_unlock, bool, 0);
48MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
49
50static bool i8042_reset;
51module_param_named(reset, i8042_reset, bool, 0);
52MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
53
54static bool i8042_direct;
55module_param_named(direct, i8042_direct, bool, 0);
56MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
57
58static bool i8042_dumbkbd;
59module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
60MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
61
62static bool i8042_noloop;
63module_param_named(noloop, i8042_noloop, bool, 0);
64MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
65
66static bool i8042_notimeout;
67module_param_named(notimeout, i8042_notimeout, bool, 0);
68MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042");
69
70#ifdef CONFIG_X86
71static bool i8042_dritek;
72module_param_named(dritek, i8042_dritek, bool, 0);
73MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension");
74#endif
75
76#ifdef CONFIG_PNP
77static bool i8042_nopnp;
78module_param_named(nopnp, i8042_nopnp, bool, 0);
79MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
80#endif
81
82#define DEBUG
83#ifdef DEBUG
84static bool i8042_debug;
85module_param_named(debug, i8042_debug, bool, 0600);
86MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
87#endif
88
89static bool i8042_bypass_aux_irq_test;
90
91#include "i8042.h"
92
93
94
95
96
97static DEFINE_SPINLOCK(i8042_lock);
98
99
100
101
102
103
104
105
106
107static DEFINE_MUTEX(i8042_mutex);
108
109struct i8042_port {
110 struct serio *serio;
111 int irq;
112 bool exists;
113 signed char mux;
114};
115
116#define I8042_KBD_PORT_NO 0
117#define I8042_AUX_PORT_NO 1
118#define I8042_MUX_PORT_NO 2
119#define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
120
121static struct i8042_port i8042_ports[I8042_NUM_PORTS];
122
123static unsigned char i8042_initial_ctr;
124static unsigned char i8042_ctr;
125static bool i8042_mux_present;
126static bool i8042_kbd_irq_registered;
127static bool i8042_aux_irq_registered;
128static unsigned char i8042_suppress_kbd_ack;
129static struct platform_device *i8042_platform_device;
130
131static irqreturn_t i8042_interrupt(int irq, void *dev_id);
132static bool (*i8042_platform_filter)(unsigned char data, unsigned char str,
133 struct serio *serio);
134
135void i8042_lock_chip(void)
136{
137 mutex_lock(&i8042_mutex);
138}
139EXPORT_SYMBOL(i8042_lock_chip);
140
141void i8042_unlock_chip(void)
142{
143 mutex_unlock(&i8042_mutex);
144}
145EXPORT_SYMBOL(i8042_unlock_chip);
146
147int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str,
148 struct serio *serio))
149{
150 unsigned long flags;
151 int ret = 0;
152
153 spin_lock_irqsave(&i8042_lock, flags);
154
155 if (i8042_platform_filter) {
156 ret = -EBUSY;
157 goto out;
158 }
159
160 i8042_platform_filter = filter;
161
162out:
163 spin_unlock_irqrestore(&i8042_lock, flags);
164 return ret;
165}
166EXPORT_SYMBOL(i8042_install_filter);
167
168int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str,
169 struct serio *port))
170{
171 unsigned long flags;
172 int ret = 0;
173
174 spin_lock_irqsave(&i8042_lock, flags);
175
176 if (i8042_platform_filter != filter) {
177 ret = -EINVAL;
178 goto out;
179 }
180
181 i8042_platform_filter = NULL;
182
183out:
184 spin_unlock_irqrestore(&i8042_lock, flags);
185 return ret;
186}
187EXPORT_SYMBOL(i8042_remove_filter);
188
189
190
191
192
193
194
195static int i8042_wait_read(void)
196{
197 int i = 0;
198
199 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
200 udelay(50);
201 i++;
202 }
203 return -(i == I8042_CTL_TIMEOUT);
204}
205
206static int i8042_wait_write(void)
207{
208 int i = 0;
209
210 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
211 udelay(50);
212 i++;
213 }
214 return -(i == I8042_CTL_TIMEOUT);
215}
216
217
218
219
220
221
222static int i8042_flush(void)
223{
224 unsigned long flags;
225 unsigned char data, str;
226 int i = 0;
227
228 spin_lock_irqsave(&i8042_lock, flags);
229
230 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) {
231 udelay(50);
232 data = i8042_read_data();
233 i++;
234 dbg("%02x <- i8042 (flush, %s)\n",
235 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
236 }
237
238 spin_unlock_irqrestore(&i8042_lock, flags);
239
240 return i;
241}
242
243
244
245
246
247
248
249
250
251static int __i8042_command(unsigned char *param, int command)
252{
253 int i, error;
254
255 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
256 return -1;
257
258 error = i8042_wait_write();
259 if (error)
260 return error;
261
262 dbg("%02x -> i8042 (command)\n", command & 0xff);
263 i8042_write_command(command & 0xff);
264
265 for (i = 0; i < ((command >> 12) & 0xf); i++) {
266 error = i8042_wait_write();
267 if (error)
268 return error;
269 dbg("%02x -> i8042 (parameter)\n", param[i]);
270 i8042_write_data(param[i]);
271 }
272
273 for (i = 0; i < ((command >> 8) & 0xf); i++) {
274 error = i8042_wait_read();
275 if (error) {
276 dbg(" -- i8042 (timeout)\n");
277 return error;
278 }
279
280 if (command == I8042_CMD_AUX_LOOP &&
281 !(i8042_read_status() & I8042_STR_AUXDATA)) {
282 dbg(" -- i8042 (auxerr)\n");
283 return -1;
284 }
285
286 param[i] = i8042_read_data();
287 dbg("%02x <- i8042 (return)\n", param[i]);
288 }
289
290 return 0;
291}
292
293int i8042_command(unsigned char *param, int command)
294{
295 unsigned long flags;
296 int retval;
297
298 spin_lock_irqsave(&i8042_lock, flags);
299 retval = __i8042_command(param, command);
300 spin_unlock_irqrestore(&i8042_lock, flags);
301
302 return retval;
303}
304EXPORT_SYMBOL(i8042_command);
305
306
307
308
309
310static int i8042_kbd_write(struct serio *port, unsigned char c)
311{
312 unsigned long flags;
313 int retval = 0;
314
315 spin_lock_irqsave(&i8042_lock, flags);
316
317 if (!(retval = i8042_wait_write())) {
318 dbg("%02x -> i8042 (kbd-data)\n", c);
319 i8042_write_data(c);
320 }
321
322 spin_unlock_irqrestore(&i8042_lock, flags);
323
324 return retval;
325}
326
327
328
329
330
331static int i8042_aux_write(struct serio *serio, unsigned char c)
332{
333 struct i8042_port *port = serio->port_data;
334
335 return i8042_command(&c, port->mux == -1 ?
336 I8042_CMD_AUX_SEND :
337 I8042_CMD_MUX_SEND + port->mux);
338}
339
340
341
342
343
344
345
346static void i8042_port_close(struct serio *serio)
347{
348 int irq_bit;
349 int disable_bit;
350 const char *port_name;
351
352 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) {
353 irq_bit = I8042_CTR_AUXINT;
354 disable_bit = I8042_CTR_AUXDIS;
355 port_name = "AUX";
356 } else {
357 irq_bit = I8042_CTR_KBDINT;
358 disable_bit = I8042_CTR_KBDDIS;
359 port_name = "KBD";
360 }
361
362 i8042_ctr &= ~irq_bit;
363 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
364 pr_warn("Can't write CTR while closing %s port\n", port_name);
365
366 udelay(50);
367
368 i8042_ctr &= ~disable_bit;
369 i8042_ctr |= irq_bit;
370 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
371 pr_err("Can't reactivate %s port\n", port_name);
372
373
374
375
376
377 i8042_interrupt(0, NULL);
378}
379
380
381
382
383
384
385static int i8042_start(struct serio *serio)
386{
387 struct i8042_port *port = serio->port_data;
388
389 port->exists = true;
390 mb();
391 return 0;
392}
393
394
395
396
397
398
399static void i8042_stop(struct serio *serio)
400{
401 struct i8042_port *port = serio->port_data;
402
403 port->exists = false;
404
405
406
407
408
409
410 synchronize_irq(I8042_AUX_IRQ);
411 synchronize_irq(I8042_KBD_IRQ);
412 port->serio = NULL;
413}
414
415
416
417
418
419
420static bool i8042_filter(unsigned char data, unsigned char str,
421 struct serio *serio)
422{
423 if (unlikely(i8042_suppress_kbd_ack)) {
424 if ((~str & I8042_STR_AUXDATA) &&
425 (data == 0xfa || data == 0xfe)) {
426 i8042_suppress_kbd_ack--;
427 dbg("Extra keyboard ACK - filtered out\n");
428 return true;
429 }
430 }
431
432 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) {
433 dbg("Filtered out by platform filter\n");
434 return true;
435 }
436
437 return false;
438}
439
440
441
442
443
444
445
446static irqreturn_t i8042_interrupt(int irq, void *dev_id)
447{
448 struct i8042_port *port;
449 struct serio *serio;
450 unsigned long flags;
451 unsigned char str, data;
452 unsigned int dfl;
453 unsigned int port_no;
454 bool filtered;
455 int ret = 1;
456
457 spin_lock_irqsave(&i8042_lock, flags);
458
459 str = i8042_read_status();
460 if (unlikely(~str & I8042_STR_OBF)) {
461 spin_unlock_irqrestore(&i8042_lock, flags);
462 if (irq)
463 dbg("Interrupt %d, without any data\n", irq);
464 ret = 0;
465 goto out;
466 }
467
468 data = i8042_read_data();
469
470 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
471 static unsigned long last_transmit;
472 static unsigned char last_str;
473
474 dfl = 0;
475 if (str & I8042_STR_MUXERR) {
476 dbg("MUX error, status is %02x, data is %02x\n",
477 str, data);
478
479
480
481
482
483
484
485
486
487
488
489
490
491 switch (data) {
492 default:
493 if (time_before(jiffies, last_transmit + HZ/10)) {
494 str = last_str;
495 break;
496 }
497
498 case 0xfc:
499 case 0xfd:
500 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
501 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
502 }
503 }
504
505 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
506 last_str = str;
507 last_transmit = jiffies;
508 } else {
509
510 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
511 ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0);
512
513 port_no = (str & I8042_STR_AUXDATA) ?
514 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
515 }
516
517 port = &i8042_ports[port_no];
518 serio = port->exists ? port->serio : NULL;
519
520 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)\n",
521 data, port_no, irq,
522 dfl & SERIO_PARITY ? ", bad parity" : "",
523 dfl & SERIO_TIMEOUT ? ", timeout" : "");
524
525 filtered = i8042_filter(data, str, serio);
526
527 spin_unlock_irqrestore(&i8042_lock, flags);
528
529 if (likely(port->exists && !filtered))
530 serio_interrupt(serio, data, dfl);
531
532 out:
533 return IRQ_RETVAL(ret);
534}
535
536
537
538
539
540static int i8042_enable_kbd_port(void)
541{
542 i8042_ctr &= ~I8042_CTR_KBDDIS;
543 i8042_ctr |= I8042_CTR_KBDINT;
544
545 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
546 i8042_ctr &= ~I8042_CTR_KBDINT;
547 i8042_ctr |= I8042_CTR_KBDDIS;
548 pr_err("Failed to enable KBD port\n");
549 return -EIO;
550 }
551
552 return 0;
553}
554
555
556
557
558
559static int i8042_enable_aux_port(void)
560{
561 i8042_ctr &= ~I8042_CTR_AUXDIS;
562 i8042_ctr |= I8042_CTR_AUXINT;
563
564 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
565 i8042_ctr &= ~I8042_CTR_AUXINT;
566 i8042_ctr |= I8042_CTR_AUXDIS;
567 pr_err("Failed to enable AUX port\n");
568 return -EIO;
569 }
570
571 return 0;
572}
573
574
575
576
577
578
579static int i8042_enable_mux_ports(void)
580{
581 unsigned char param;
582 int i;
583
584 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
585 i8042_command(¶m, I8042_CMD_MUX_PFX + i);
586 i8042_command(¶m, I8042_CMD_AUX_ENABLE);
587 }
588
589 return i8042_enable_aux_port();
590}
591
592
593
594
595
596
597
598static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version)
599{
600
601 unsigned char param, val;
602
603
604
605
606 i8042_flush();
607
608
609
610
611
612
613 param = val = 0xf0;
614 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
615 return -1;
616 param = val = multiplex ? 0x56 : 0xf6;
617 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
618 return -1;
619 param = val = multiplex ? 0xa4 : 0xa5;
620 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val)
621 return -1;
622
623
624
625
626
627 if (param == 0xac)
628 return -1;
629
630 if (mux_version)
631 *mux_version = param;
632
633 return 0;
634}
635
636
637
638
639
640
641
642static int __init i8042_check_mux(void)
643{
644 unsigned char mux_version;
645
646 if (i8042_set_mux_mode(true, &mux_version))
647 return -1;
648
649 pr_info("Detected active multiplexing controller, rev %d.%d\n",
650 (mux_version >> 4) & 0xf, mux_version & 0xf);
651
652
653
654
655 i8042_ctr |= I8042_CTR_AUXDIS;
656 i8042_ctr &= ~I8042_CTR_AUXINT;
657
658 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
659 pr_err("Failed to disable AUX port, can't use MUX\n");
660 return -EIO;
661 }
662
663 i8042_mux_present = true;
664
665 return 0;
666}
667
668
669
670
671static struct completion i8042_aux_irq_delivered __initdata;
672static bool i8042_irq_being_tested __initdata;
673
674static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id)
675{
676 unsigned long flags;
677 unsigned char str, data;
678 int ret = 0;
679
680 spin_lock_irqsave(&i8042_lock, flags);
681 str = i8042_read_status();
682 if (str & I8042_STR_OBF) {
683 data = i8042_read_data();
684 dbg("%02x <- i8042 (aux_test_irq, %s)\n",
685 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
686 if (i8042_irq_being_tested &&
687 data == 0xa5 && (str & I8042_STR_AUXDATA))
688 complete(&i8042_aux_irq_delivered);
689 ret = 1;
690 }
691 spin_unlock_irqrestore(&i8042_lock, flags);
692
693 return IRQ_RETVAL(ret);
694}
695
696
697
698
699
700
701static int __init i8042_toggle_aux(bool on)
702{
703 unsigned char param;
704 int i;
705
706 if (i8042_command(¶m,
707 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
708 return -1;
709
710
711 for (i = 0; i < 100; i++) {
712 udelay(50);
713
714 if (i8042_command(¶m, I8042_CMD_CTL_RCTR))
715 return -1;
716
717 if (!(param & I8042_CTR_AUXDIS) == on)
718 return 0;
719 }
720
721 return -1;
722}
723
724
725
726
727
728
729static int __init i8042_check_aux(void)
730{
731 int retval = -1;
732 bool irq_registered = false;
733 bool aux_loop_broken = false;
734 unsigned long flags;
735 unsigned char param;
736
737
738
739
740
741 i8042_flush();
742
743
744
745
746
747
748
749 param = 0x5a;
750 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP);
751 if (retval || param != 0x5a) {
752
753
754
755
756
757
758
759
760
761 if (i8042_command(¶m, I8042_CMD_AUX_TEST) ||
762 (param && param != 0xfa && param != 0xff))
763 return -1;
764
765
766
767
768
769 if (!retval)
770 aux_loop_broken = true;
771 }
772
773
774
775
776
777 if (i8042_toggle_aux(false)) {
778 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
779 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n");
780 }
781
782 if (i8042_toggle_aux(true))
783 return -1;
784
785
786
787
788
789
790 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) {
791
792
793
794
795 retval = 0;
796 goto out;
797 }
798
799 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
800 "i8042", i8042_platform_device))
801 goto out;
802
803 irq_registered = true;
804
805 if (i8042_enable_aux_port())
806 goto out;
807
808 spin_lock_irqsave(&i8042_lock, flags);
809
810 init_completion(&i8042_aux_irq_delivered);
811 i8042_irq_being_tested = true;
812
813 param = 0xa5;
814 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff);
815
816 spin_unlock_irqrestore(&i8042_lock, flags);
817
818 if (retval)
819 goto out;
820
821 if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
822 msecs_to_jiffies(250)) == 0) {
823
824
825
826
827 dbg(" -- i8042 (aux irq test timeout)\n");
828 i8042_flush();
829 retval = -1;
830 }
831
832 out:
833
834
835
836
837
838 i8042_ctr |= I8042_CTR_AUXDIS;
839 i8042_ctr &= ~I8042_CTR_AUXINT;
840
841 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
842 retval = -1;
843
844 if (irq_registered)
845 free_irq(I8042_AUX_IRQ, i8042_platform_device);
846
847 return retval;
848}
849
850static int i8042_controller_check(void)
851{
852 if (i8042_flush() == I8042_BUFFER_SIZE) {
853 pr_err("No controller found\n");
854 return -ENODEV;
855 }
856
857 return 0;
858}
859
860static int i8042_controller_selftest(void)
861{
862 unsigned char param;
863 int i = 0;
864
865
866
867
868
869 do {
870
871 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
872 pr_err("i8042 controller selftest timeout\n");
873 return -ENODEV;
874 }
875
876 if (param == I8042_RET_CTL_TEST)
877 return 0;
878
879 dbg("i8042 controller selftest: %#x != %#x\n",
880 param, I8042_RET_CTL_TEST);
881 msleep(50);
882 } while (i++ < 5);
883
884#ifdef CONFIG_X86
885
886
887
888
889
890
891 pr_info("giving up on controller selftest, continuing anyway...\n");
892 return 0;
893#else
894 pr_err("i8042 controller selftest failed\n");
895 return -EIO;
896#endif
897}
898
899
900
901
902
903
904
905static int i8042_controller_init(void)
906{
907 unsigned long flags;
908 int n = 0;
909 unsigned char ctr[2];
910
911
912
913
914
915 do {
916 if (n >= 10) {
917 pr_err("Unable to get stable CTR read\n");
918 return -EIO;
919 }
920
921 if (n != 0)
922 udelay(50);
923
924 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) {
925 pr_err("Can't read CTR while initializing i8042\n");
926 return -EIO;
927 }
928
929 } while (n < 2 || ctr[0] != ctr[1]);
930
931 i8042_initial_ctr = i8042_ctr = ctr[0];
932
933
934
935
936
937 i8042_ctr |= I8042_CTR_KBDDIS;
938 i8042_ctr &= ~I8042_CTR_KBDINT;
939
940
941
942
943
944 spin_lock_irqsave(&i8042_lock, flags);
945 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
946 if (i8042_unlock)
947 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
948 else
949 pr_warn("Warning: Keylock active\n");
950 }
951 spin_unlock_irqrestore(&i8042_lock, flags);
952
953
954
955
956
957
958 if (~i8042_ctr & I8042_CTR_XLATE)
959 i8042_direct = true;
960
961
962
963
964
965
966
967
968 if (i8042_direct)
969 i8042_ctr &= ~I8042_CTR_XLATE;
970
971
972
973
974
975 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
976 pr_err("Can't write CTR while initializing i8042\n");
977 return -EIO;
978 }
979
980
981
982
983
984 i8042_flush();
985
986 return 0;
987}
988
989
990
991
992
993
994static void i8042_controller_reset(bool force_reset)
995{
996 i8042_flush();
997
998
999
1000
1001
1002 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
1003 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
1004
1005 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
1006 pr_warn("Can't write CTR while resetting\n");
1007
1008
1009
1010
1011
1012 if (i8042_mux_present)
1013 i8042_set_mux_mode(false, NULL);
1014
1015
1016
1017
1018
1019 if (i8042_reset || force_reset)
1020 i8042_controller_selftest();
1021
1022
1023
1024
1025
1026 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
1027 pr_warn("Can't restore CTR\n");
1028}
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041#define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
1042
1043static long i8042_panic_blink(int state)
1044{
1045 long delay = 0;
1046 char led;
1047
1048 led = (state) ? 0x01 | 0x04 : 0;
1049 while (i8042_read_status() & I8042_STR_IBF)
1050 DELAY;
1051 dbg("%02x -> i8042 (panic blink)\n", 0xed);
1052 i8042_suppress_kbd_ack = 2;
1053 i8042_write_data(0xed);
1054 DELAY;
1055 while (i8042_read_status() & I8042_STR_IBF)
1056 DELAY;
1057 DELAY;
1058 dbg("%02x -> i8042 (panic blink)\n", led);
1059 i8042_write_data(led);
1060 DELAY;
1061 return delay;
1062}
1063
1064#undef DELAY
1065
1066#ifdef CONFIG_X86
1067static void i8042_dritek_enable(void)
1068{
1069 unsigned char param = 0x90;
1070 int error;
1071
1072 error = i8042_command(¶m, 0x1059);
1073 if (error)
1074 pr_warn("Failed to enable DRITEK extension: %d\n", error);
1075}
1076#endif
1077
1078#ifdef CONFIG_PM
1079
1080
1081
1082
1083
1084
1085static int i8042_controller_resume(bool force_reset)
1086{
1087 int error;
1088
1089 error = i8042_controller_check();
1090 if (error)
1091 return error;
1092
1093 if (i8042_reset || force_reset) {
1094 error = i8042_controller_selftest();
1095 if (error)
1096 return error;
1097 }
1098
1099
1100
1101
1102
1103 i8042_ctr = i8042_initial_ctr;
1104 if (i8042_direct)
1105 i8042_ctr &= ~I8042_CTR_XLATE;
1106 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
1107 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
1108 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1109 pr_warn("Can't write CTR to resume, retrying...\n");
1110 msleep(50);
1111 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1112 pr_err("CTR write retry failed\n");
1113 return -EIO;
1114 }
1115 }
1116
1117
1118#ifdef CONFIG_X86
1119 if (i8042_dritek)
1120 i8042_dritek_enable();
1121#endif
1122
1123 if (i8042_mux_present) {
1124 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports())
1125 pr_warn("failed to resume active multiplexor, mouse won't work\n");
1126 } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
1127 i8042_enable_aux_port();
1128
1129 if (i8042_ports[I8042_KBD_PORT_NO].serio)
1130 i8042_enable_kbd_port();
1131
1132 i8042_interrupt(0, NULL);
1133
1134 return 0;
1135}
1136
1137
1138
1139
1140
1141
1142static int i8042_pm_suspend(struct device *dev)
1143{
1144 i8042_controller_reset(true);
1145
1146 return 0;
1147}
1148
1149static int i8042_pm_resume(struct device *dev)
1150{
1151
1152
1153
1154
1155
1156 return i8042_controller_resume(true);
1157}
1158
1159static int i8042_pm_thaw(struct device *dev)
1160{
1161 i8042_interrupt(0, NULL);
1162
1163 return 0;
1164}
1165
1166static int i8042_pm_reset(struct device *dev)
1167{
1168 i8042_controller_reset(false);
1169
1170 return 0;
1171}
1172
1173static int i8042_pm_restore(struct device *dev)
1174{
1175 return i8042_controller_resume(false);
1176}
1177
1178static const struct dev_pm_ops i8042_pm_ops = {
1179 .suspend = i8042_pm_suspend,
1180 .resume = i8042_pm_resume,
1181 .thaw = i8042_pm_thaw,
1182 .poweroff = i8042_pm_reset,
1183 .restore = i8042_pm_restore,
1184};
1185
1186#endif
1187
1188
1189
1190
1191
1192
1193static void i8042_shutdown(struct platform_device *dev)
1194{
1195 i8042_controller_reset(false);
1196}
1197
1198static int __init i8042_create_kbd_port(void)
1199{
1200 struct serio *serio;
1201 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
1202
1203 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1204 if (!serio)
1205 return -ENOMEM;
1206
1207 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
1208 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
1209 serio->start = i8042_start;
1210 serio->stop = i8042_stop;
1211 serio->close = i8042_port_close;
1212 serio->port_data = port;
1213 serio->dev.parent = &i8042_platform_device->dev;
1214 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
1215 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
1216
1217 port->serio = serio;
1218 port->irq = I8042_KBD_IRQ;
1219
1220 return 0;
1221}
1222
1223static int __init i8042_create_aux_port(int idx)
1224{
1225 struct serio *serio;
1226 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
1227 struct i8042_port *port = &i8042_ports[port_no];
1228
1229 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1230 if (!serio)
1231 return -ENOMEM;
1232
1233 serio->id.type = SERIO_8042;
1234 serio->write = i8042_aux_write;
1235 serio->start = i8042_start;
1236 serio->stop = i8042_stop;
1237 serio->port_data = port;
1238 serio->dev.parent = &i8042_platform_device->dev;
1239 if (idx < 0) {
1240 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
1241 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
1242 serio->close = i8042_port_close;
1243 } else {
1244 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
1245 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
1246 }
1247
1248 port->serio = serio;
1249 port->mux = idx;
1250 port->irq = I8042_AUX_IRQ;
1251
1252 return 0;
1253}
1254
1255static void __init i8042_free_kbd_port(void)
1256{
1257 kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
1258 i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
1259}
1260
1261static void __init i8042_free_aux_ports(void)
1262{
1263 int i;
1264
1265 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
1266 kfree(i8042_ports[i].serio);
1267 i8042_ports[i].serio = NULL;
1268 }
1269}
1270
1271static void __init i8042_register_ports(void)
1272{
1273 int i;
1274
1275 for (i = 0; i < I8042_NUM_PORTS; i++) {
1276 if (i8042_ports[i].serio) {
1277 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
1278 i8042_ports[i].serio->name,
1279 (unsigned long) I8042_DATA_REG,
1280 (unsigned long) I8042_COMMAND_REG,
1281 i8042_ports[i].irq);
1282 serio_register_port(i8042_ports[i].serio);
1283 }
1284 }
1285}
1286
1287static void i8042_unregister_ports(void)
1288{
1289 int i;
1290
1291 for (i = 0; i < I8042_NUM_PORTS; i++) {
1292 if (i8042_ports[i].serio) {
1293 serio_unregister_port(i8042_ports[i].serio);
1294 i8042_ports[i].serio = NULL;
1295 }
1296 }
1297}
1298
1299
1300
1301
1302bool i8042_check_port_owner(const struct serio *port)
1303{
1304 int i;
1305
1306 for (i = 0; i < I8042_NUM_PORTS; i++)
1307 if (i8042_ports[i].serio == port)
1308 return true;
1309
1310 return false;
1311}
1312EXPORT_SYMBOL(i8042_check_port_owner);
1313
1314static void i8042_free_irqs(void)
1315{
1316 if (i8042_aux_irq_registered)
1317 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1318 if (i8042_kbd_irq_registered)
1319 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1320
1321 i8042_aux_irq_registered = i8042_kbd_irq_registered = false;
1322}
1323
1324static int __init i8042_setup_aux(void)
1325{
1326 int (*aux_enable)(void);
1327 int error;
1328 int i;
1329
1330 if (i8042_check_aux())
1331 return -ENODEV;
1332
1333 if (i8042_nomux || i8042_check_mux()) {
1334 error = i8042_create_aux_port(-1);
1335 if (error)
1336 goto err_free_ports;
1337 aux_enable = i8042_enable_aux_port;
1338 } else {
1339 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
1340 error = i8042_create_aux_port(i);
1341 if (error)
1342 goto err_free_ports;
1343 }
1344 aux_enable = i8042_enable_mux_ports;
1345 }
1346
1347 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
1348 "i8042", i8042_platform_device);
1349 if (error)
1350 goto err_free_ports;
1351
1352 if (aux_enable())
1353 goto err_free_irq;
1354
1355 i8042_aux_irq_registered = true;
1356 return 0;
1357
1358 err_free_irq:
1359 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1360 err_free_ports:
1361 i8042_free_aux_ports();
1362 return error;
1363}
1364
1365static int __init i8042_setup_kbd(void)
1366{
1367 int error;
1368
1369 error = i8042_create_kbd_port();
1370 if (error)
1371 return error;
1372
1373 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
1374 "i8042", i8042_platform_device);
1375 if (error)
1376 goto err_free_port;
1377
1378 error = i8042_enable_kbd_port();
1379 if (error)
1380 goto err_free_irq;
1381
1382 i8042_kbd_irq_registered = true;
1383 return 0;
1384
1385 err_free_irq:
1386 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1387 err_free_port:
1388 i8042_free_kbd_port();
1389 return error;
1390}
1391
1392static int __init i8042_probe(struct platform_device *dev)
1393{
1394 int error;
1395
1396 i8042_platform_device = dev;
1397
1398 if (i8042_reset) {
1399 error = i8042_controller_selftest();
1400 if (error)
1401 return error;
1402 }
1403
1404 error = i8042_controller_init();
1405 if (error)
1406 return error;
1407
1408#ifdef CONFIG_X86
1409 if (i8042_dritek)
1410 i8042_dritek_enable();
1411#endif
1412
1413 if (!i8042_noaux) {
1414 error = i8042_setup_aux();
1415 if (error && error != -ENODEV && error != -EBUSY)
1416 goto out_fail;
1417 }
1418
1419 if (!i8042_nokbd) {
1420 error = i8042_setup_kbd();
1421 if (error)
1422 goto out_fail;
1423 }
1424
1425
1426
1427 i8042_register_ports();
1428
1429 return 0;
1430
1431 out_fail:
1432 i8042_free_aux_ports();
1433 i8042_free_irqs();
1434 i8042_controller_reset(false);
1435 i8042_platform_device = NULL;
1436
1437 return error;
1438}
1439
1440static int i8042_remove(struct platform_device *dev)
1441{
1442 i8042_unregister_ports();
1443 i8042_free_irqs();
1444 i8042_controller_reset(false);
1445 i8042_platform_device = NULL;
1446
1447 return 0;
1448}
1449
1450static struct platform_driver i8042_driver = {
1451 .driver = {
1452 .name = "i8042",
1453 .owner = THIS_MODULE,
1454#ifdef CONFIG_PM
1455 .pm = &i8042_pm_ops,
1456#endif
1457 },
1458 .remove = i8042_remove,
1459 .shutdown = i8042_shutdown,
1460};
1461
1462static int __init i8042_init(void)
1463{
1464 struct platform_device *pdev;
1465 int err;
1466
1467 dbg_init();
1468
1469 err = i8042_platform_init();
1470 if (err)
1471 return err;
1472
1473 err = i8042_controller_check();
1474 if (err)
1475 goto err_platform_exit;
1476
1477 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0);
1478 if (IS_ERR(pdev)) {
1479 err = PTR_ERR(pdev);
1480 goto err_platform_exit;
1481 }
1482
1483 panic_blink = i8042_panic_blink;
1484
1485 return 0;
1486
1487 err_platform_exit:
1488 i8042_platform_exit();
1489 return err;
1490}
1491
1492static void __exit i8042_exit(void)
1493{
1494 platform_device_unregister(i8042_platform_device);
1495 platform_driver_unregister(&i8042_driver);
1496 i8042_platform_exit();
1497
1498 panic_blink = NULL;
1499}
1500
1501module_init(i8042_init);
1502module_exit(i8042_exit);
1503