LXR linux/drivers/media/platform/omap3isp/isp.h

   1/*
   2 * isp.h
   3 *
   4 * TI OMAP3 ISP - Core
   5 *
   6 * Copyright (C) 2009-2010 Nokia Corporation
   7 * Copyright (C) 2009 Texas Instruments, Inc.
   8 *
   9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10 *           Sakari Ailus <sakari.ailus@iki.fi>
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License version 2 as
  14 * published by the Free Software Foundation.
  15 *
  16 * This program is distributed in the hope that it will be useful, but
  17 * WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19 * General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  24 * 02110-1301 USA
  25 */
  26
  27#ifndef OMAP3_ISP_CORE_H
  28#define OMAP3_ISP_CORE_H
  29
  30#include <media/omap3isp.h>
  31#include <media/v4l2-device.h>
  32#include <linux/device.h>
  33#include <linux/io.h>
  34#include <linux/iommu.h>
  35#include <linux/platform_device.h>
  36#include <linux/wait.h>
  37
  38#include "ispstat.h"
  39#include "ispccdc.h"
  40#include "ispreg.h"
  41#include "ispresizer.h"
  42#include "isppreview.h"
  43#include "ispcsiphy.h"
  44#include "ispcsi2.h"
  45#include "ispccp2.h"
  46
  47#define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8)
  48
  49#define ISP_TOK_TERM            0xFFFFFFFF      /*
  50                                                 * terminating token for ISP
  51                                                 * modules reg list
  52                                                 */
  53#define to_isp_device(ptr_module)                               \
  54        container_of(ptr_module, struct isp_device, isp_##ptr_module)
  55#define to_device(ptr_module)                                           \
  56        (to_isp_device(ptr_module)->dev)
  57
  58enum isp_mem_resources {
  59        OMAP3_ISP_IOMEM_MAIN,
  60        OMAP3_ISP_IOMEM_CCP2,
  61        OMAP3_ISP_IOMEM_CCDC,
  62        OMAP3_ISP_IOMEM_HIST,
  63        OMAP3_ISP_IOMEM_H3A,
  64        OMAP3_ISP_IOMEM_PREV,
  65        OMAP3_ISP_IOMEM_RESZ,
  66        OMAP3_ISP_IOMEM_SBL,
  67        OMAP3_ISP_IOMEM_CSI2A_REGS1,
  68        OMAP3_ISP_IOMEM_CSIPHY2,
  69        OMAP3_ISP_IOMEM_CSI2A_REGS2,
  70        OMAP3_ISP_IOMEM_CSI2C_REGS1,
  71        OMAP3_ISP_IOMEM_CSIPHY1,
  72        OMAP3_ISP_IOMEM_CSI2C_REGS2,
  73        OMAP3_ISP_IOMEM_343X_CONTROL_CSIRXFE,
  74        OMAP3_ISP_IOMEM_3630_CONTROL_CAMERA_PHY_CTRL,
  75        OMAP3_ISP_IOMEM_LAST
  76};
  77
  78enum isp_sbl_resource {
  79        OMAP3_ISP_SBL_CSI1_READ         = 0x1,
  80        OMAP3_ISP_SBL_CSI1_WRITE        = 0x2,
  81        OMAP3_ISP_SBL_CSI2A_WRITE       = 0x4,
  82        OMAP3_ISP_SBL_CSI2C_WRITE       = 0x8,
  83        OMAP3_ISP_SBL_CCDC_LSC_READ     = 0x10,
  84        OMAP3_ISP_SBL_CCDC_WRITE        = 0x20,
  85        OMAP3_ISP_SBL_PREVIEW_READ      = 0x40,
  86        OMAP3_ISP_SBL_PREVIEW_WRITE     = 0x80,
  87        OMAP3_ISP_SBL_RESIZER_READ      = 0x100,
  88        OMAP3_ISP_SBL_RESIZER_WRITE     = 0x200,
  89};
  90
  91enum isp_subclk_resource {
  92        OMAP3_ISP_SUBCLK_CCDC           = (1 << 0),
  93        OMAP3_ISP_SUBCLK_AEWB           = (1 << 1),
  94        OMAP3_ISP_SUBCLK_AF             = (1 << 2),
  95        OMAP3_ISP_SUBCLK_HIST           = (1 << 3),
  96        OMAP3_ISP_SUBCLK_PREVIEW        = (1 << 4),
  97        OMAP3_ISP_SUBCLK_RESIZER        = (1 << 5),
  98};
  99
 100/* ISP: OMAP 34xx ES 1.0 */
 101#define ISP_REVISION_1_0                0x10
 102/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
 103#define ISP_REVISION_2_0                0x20
 104/* ISP2P: OMAP 36xx */
 105#define ISP_REVISION_15_0               0xF0
 106
 107/*
 108 * struct isp_res_mapping - Map ISP io resources to ISP revision.
 109 * @isp_rev: ISP_REVISION_x_x
 110 * @map: bitmap for enum isp_mem_resources
 111 */
 112struct isp_res_mapping {
 113        u32 isp_rev;
 114        u32 map;
 115};
 116
 117/*
 118 * struct isp_reg - Structure for ISP register values.
 119 * @reg: 32-bit Register address.
 120 * @val: 32-bit Register value.
 121 */
 122struct isp_reg {
 123        enum isp_mem_resources mmio_range;
 124        u32 reg;
 125        u32 val;
 126};
 127
 128struct isp_platform_callback {
 129        u32 (*set_xclk)(struct isp_device *isp, u32 xclk, u8 xclksel);
 130};
 131
 132/*
 133 * struct isp_device - ISP device structure.
 134 * @dev: Device pointer specific to the OMAP3 ISP.
 135 * @revision: Stores current ISP module revision.
 136 * @irq_num: Currently used IRQ number.
 137 * @mmio_base: Array with kernel base addresses for ioremapped ISP register
 138 *             regions.
 139 * @mmio_base_phys: Array with physical L4 bus addresses for ISP register
 140 *                  regions.
 141 * @mmio_size: Array with ISP register regions size in bytes.
 142 * @raw_dmamask: Raw DMA mask
 143 * @stat_lock: Spinlock for handling statistics
 144 * @isp_mutex: Mutex for serializing requests to ISP.
 145 * @crashed: Bitmask of crashed entities (indexed by entity ID)
 146 * @has_context: Context has been saved at least once and can be restored.
 147 * @ref_count: Reference count for handling multiple ISP requests.
 148 * @cam_ick: Pointer to camera interface clock structure.
 149 * @cam_mclk: Pointer to camera functional clock structure.
 150 * @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
 151 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
 152 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
 153 * @irq: Currently attached ISP ISR callbacks information structure.
 154 * @isp_af: Pointer to current settings for ISP AutoFocus SCM.
 155 * @isp_hist: Pointer to current settings for ISP Histogram SCM.
 156 * @isp_h3a: Pointer to current settings for ISP Auto Exposure and
 157 *           White Balance SCM.
 158 * @isp_res: Pointer to current settings for ISP Resizer.
 159 * @isp_prev: Pointer to current settings for ISP Preview.
 160 * @isp_ccdc: Pointer to current settings for ISP CCDC.
 161 * @iommu: Pointer to requested IOMMU instance for ISP.
 162 * @platform_cb: ISP driver callback function pointers for platform code
 163 *
 164 * This structure is used to store the OMAP ISP Information.
 165 */
 166struct isp_device {
 167        struct v4l2_device v4l2_dev;
 168        struct media_device media_dev;
 169        struct device *dev;
 170        u32 revision;
 171
 172        /* platform HW resources */
 173        struct isp_platform_data *pdata;
 174        unsigned int irq_num;
 175
 176        void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
 177        unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST];
 178        resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST];
 179
 180        u64 raw_dmamask;
 181
 182        /* ISP Obj */
 183        spinlock_t stat_lock;   /* common lock for statistic drivers */
 184        struct mutex isp_mutex; /* For handling ref_count field */
 185        u32 crashed;
 186        int has_context;
 187        int ref_count;
 188        unsigned int autoidle;
 189        u32 xclk_divisor[2];    /* Two clocks, a and b. */
 190#define ISP_CLK_CAM_ICK         0
 191#define ISP_CLK_CAM_MCLK        1
 192#define ISP_CLK_DPLL4_M5_CK     2
 193#define ISP_CLK_CSI2_FCK        3
 194#define ISP_CLK_L3_ICK          4
 195        struct clk *clock[5];
 196
 197        /* ISP modules */
 198        struct ispstat isp_af;
 199        struct ispstat isp_aewb;
 200        struct ispstat isp_hist;
 201        struct isp_res_device isp_res;
 202        struct isp_prev_device isp_prev;
 203        struct isp_ccdc_device isp_ccdc;
 204        struct isp_csi2_device isp_csi2a;
 205        struct isp_csi2_device isp_csi2c;
 206        struct isp_ccp2_device isp_ccp2;
 207        struct isp_csiphy isp_csiphy1;
 208        struct isp_csiphy isp_csiphy2;
 209
 210        unsigned int sbl_resources;
 211        unsigned int subclk_resources;
 212
 213        struct iommu_domain *domain;
 214
 215        struct isp_platform_callback platform_cb;
 216};
 217
 218#define v4l2_dev_to_isp_device(dev) \
 219        container_of(dev, struct isp_device, v4l2_dev)
 220
 221void omap3isp_hist_dma_done(struct isp_device *isp);
 222
 223void omap3isp_flush(struct isp_device *isp);
 224
 225int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
 226                              atomic_t *stopping);
 227
 228int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
 229                                     atomic_t *stopping);
 230
 231int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
 232                                 enum isp_pipeline_stream_state state);
 233void omap3isp_configure_bridge(struct isp_device *isp,
 234                               enum ccdc_input_entity input,
 235                               const struct isp_parallel_platform_data *pdata,
 236                               unsigned int shift, unsigned int bridge);
 237
 238struct isp_device *omap3isp_get(struct isp_device *isp);
 239void omap3isp_put(struct isp_device *isp);
 240
 241void omap3isp_print_status(struct isp_device *isp);
 242
 243void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
 244void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
 245
 246void omap3isp_subclk_enable(struct isp_device *isp,
 247                            enum isp_subclk_resource res);
 248void omap3isp_subclk_disable(struct isp_device *isp,
 249                             enum isp_subclk_resource res);
 250
 251int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);
 252
 253int omap3isp_register_entities(struct platform_device *pdev,
 254                               struct v4l2_device *v4l2_dev);
 255void omap3isp_unregister_entities(struct platform_device *pdev);
 256
 257/*
 258 * isp_reg_readl - Read value of an OMAP3 ISP register
 259 * @dev: Device pointer specific to the OMAP3 ISP.
 260 * @isp_mmio_range: Range to which the register offset refers to.
 261 * @reg_offset: Register offset to read from.
 262 *
 263 * Returns an unsigned 32 bit value with the required register contents.
 264 */
 265static inline
 266u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
 267                  u32 reg_offset)
 268{
 269        return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
 270}
 271
 272/*
 273 * isp_reg_writel - Write value to an OMAP3 ISP register
 274 * @dev: Device pointer specific to the OMAP3 ISP.
 275 * @reg_value: 32 bit value to write to the register.
 276 * @isp_mmio_range: Range to which the register offset refers to.
 277 * @reg_offset: Register offset to write into.
 278 */
 279static inline
 280void isp_reg_writel(struct isp_device *isp, u32 reg_value,
 281                    enum isp_mem_resources isp_mmio_range, u32 reg_offset)
 282{
 283        __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
 284}
 285
 286/*
 287 * isp_reg_and - Clear individual bits in an OMAP3 ISP register
 288 * @dev: Device pointer specific to the OMAP3 ISP.
 289 * @mmio_range: Range to which the register offset refers to.
 290 * @reg: Register offset to work on.
 291 * @clr_bits: 32 bit value which would be cleared in the register.
 292 */
 293static inline
 294void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
 295                 u32 reg, u32 clr_bits)
 296{
 297        u32 v = isp_reg_readl(isp, mmio_range, reg);
 298
 299        isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
 300}
 301
 302/*
 303 * isp_reg_set - Set individual bits in an OMAP3 ISP register
 304 * @dev: Device pointer specific to the OMAP3 ISP.
 305 * @mmio_range: Range to which the register offset refers to.
 306 * @reg: Register offset to work on.
 307 * @set_bits: 32 bit value which would be set in the register.
 308 */
 309static inline
 310void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
 311                 u32 reg, u32 set_bits)
 312{
 313        u32 v = isp_reg_readl(isp, mmio_range, reg);
 314
 315        isp_reg_writel(isp, v | set_bits, mmio_range, reg);
 316}
 317
 318/*
 319 * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
 320 * @dev: Device pointer specific to the OMAP3 ISP.
 321 * @mmio_range: Range to which the register offset refers to.
 322 * @reg: Register offset to work on.
 323 * @clr_bits: 32 bit value which would be cleared in the register.
 324 * @set_bits: 32 bit value which would be set in the register.
 325 *
 326 * The clear operation is done first, and then the set operation.
 327 */
 328static inline
 329void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
 330                     u32 reg, u32 clr_bits, u32 set_bits)
 331{
 332        u32 v = isp_reg_readl(isp, mmio_range, reg);
 333
 334        isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
 335}
 336
 337static inline enum v4l2_buf_type
 338isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
 339{
 340        if (pad >= subdev->entity.num_pads)
 341                return 0;
 342
 343        if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
 344                return V4L2_BUF_TYPE_VIDEO_OUTPUT;
 345        else
 346                return V4L2_BUF_TYPE_VIDEO_CAPTURE;
 347}
 348
 349#endif  /* OMAP3_ISP_CORE_H */
 350