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38#ifndef _AMD811E_H
39#define _AMD811E_H
40
41
42
43
44
45
46
47
48
49
50
51
52#define ASF_STAT 0x00
53#define CHIPID 0x04
54#define MIB_DATA 0x10
55#define MIB_ADDR 0x14
56#define STAT0 0x30
57#define INT0 0x38
58#define INTEN0 0x40
59#define CMD0 0x48
60#define CMD2 0x50
61#define CMD3 0x54
62#define CMD7 0x64
63
64#define CTRL1 0x6C
65#define CTRL2 0x70
66
67#define XMT_RING_LIMIT 0x7C
68
69#define AUTOPOLL0 0x88
70#define AUTOPOLL1 0x8A
71#define AUTOPOLL2 0x8C
72#define AUTOPOLL3 0x8E
73#define AUTOPOLL4 0x90
74#define AUTOPOLL5 0x92
75
76#define AP_VALUE 0x98
77#define DLY_INT_A 0xA8
78#define DLY_INT_B 0xAC
79
80#define FLOW_CONTROL 0xC8
81#define PHY_ACCESS 0xD0
82
83#define STVAL 0xD8
84
85#define XMT_RING_BASE_ADDR0 0x100
86#define XMT_RING_BASE_ADDR1 0x108
87#define XMT_RING_BASE_ADDR2 0x110
88#define XMT_RING_BASE_ADDR3 0x118
89
90#define RCV_RING_BASE_ADDR0 0x120
91
92#define PMAT0 0x190
93#define PMAT1 0x194
94
95
96
97#define XMT_RING_LEN0 0x140
98#define XMT_RING_LEN1 0x144
99#define XMT_RING_LEN2 0x148
100#define XMT_RING_LEN3 0x14C
101
102#define RCV_RING_LEN0 0x150
103
104#define SRAM_SIZE 0x178
105#define SRAM_BOUNDARY 0x17A
106
107
108
109#define PADR 0x160
110
111#define IFS1 0x18C
112#define IFS 0x18D
113#define IPG 0x18E
114
115
116#define LADRF 0x168
117
118
119
120typedef enum {
121
122 ASF_INIT_DONE = (1 << 1),
123 ASF_INIT_PRESENT = (1 << 0),
124
125}STAT_ASF_BITS;
126
127typedef enum {
128
129 MIB_CMD_ACTIVE = (1 << 15 ),
130 MIB_RD_CMD = (1 << 13 ),
131 MIB_CLEAR = (1 << 12 ),
132 MIB_ADDRESS = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
133 (1 << 4) | (1 << 5),
134}MIB_ADDR_BITS;
135
136
137typedef enum {
138
139 PMAT_DET = (1 << 12),
140 MP_DET = (1 << 11),
141 LC_DET = (1 << 10),
142 SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7),
143 FULL_DPLX = (1 << 6),
144 LINK_STATS = (1 << 5),
145 AUTONEG_COMPLETE = (1 << 4),
146 MIIPD = (1 << 3),
147 RX_SUSPENDED = (1 << 2),
148 TX_SUSPENDED = (1 << 1),
149 RUNNING = (1 << 0),
150
151}STAT0_BITS;
152
153#define PHY_SPEED_10 0x2
154#define PHY_SPEED_100 0x3
155
156
157typedef enum {
158
159 INTR = (1 << 31),
160 PCSINT = (1 << 28),
161 LCINT = (1 << 27),
162 APINT5 = (1 << 26),
163 APINT4 = (1 << 25),
164 APINT3 = (1 << 24),
165 TINT_SUM = (1 << 23),
166 APINT2 = (1 << 22),
167 APINT1 = (1 << 21),
168 APINT0 = (1 << 20),
169 MIIPDTINT = (1 << 19),
170 MCCINT = (1 << 17),
171 MREINT = (1 << 16),
172 RINT_SUM = (1 << 15),
173 SPNDINT = (1 << 14),
174 MPINT = (1 << 13),
175 SINT = (1 << 12),
176 TINT3 = (1 << 11),
177 TINT2 = (1 << 10),
178 TINT1 = (1 << 9),
179 TINT0 = (1 << 8),
180 UINT = (1 << 7),
181 STINT = (1 << 4),
182 RINT0 = (1 << 0),
183
184}INT0_BITS;
185
186typedef enum {
187
188 VAL3 = (1 << 31),
189 VAL2 = (1 << 23),
190 VAL1 = (1 << 15),
191 VAL0 = (1 << 7),
192
193}VAL_BITS;
194
195typedef enum {
196
197
198 LCINTEN = (1 << 27),
199 APINT5EN = (1 << 26),
200 APINT4EN = (1 << 25),
201 APINT3EN = (1 << 24),
202
203 APINT2EN = (1 << 22),
204 APINT1EN = (1 << 21),
205 APINT0EN = (1 << 20),
206 MIIPDTINTEN = (1 << 19),
207 MCCIINTEN = (1 << 18),
208 MCCINTEN = (1 << 17),
209 MREINTEN = (1 << 16),
210
211 SPNDINTEN = (1 << 14),
212 MPINTEN = (1 << 13),
213 TINTEN3 = (1 << 11),
214 SINTEN = (1 << 12),
215 TINTEN2 = (1 << 10),
216 TINTEN1 = (1 << 9),
217 TINTEN0 = (1 << 8),
218
219 STINTEN = (1 << 4),
220 RINTEN0 = (1 << 0),
221
222 INTEN0_CLEAR = 0x1F7F7F1F,
223
224}INTEN0_BITS;
225
226typedef enum {
227
228 RDMD0 = (1 << 16),
229
230 TDMD3 = (1 << 11),
231 TDMD2 = (1 << 10),
232 TDMD1 = (1 << 9),
233 TDMD0 = (1 << 8),
234
235 UINTCMD = (1 << 6),
236 RX_FAST_SPND = (1 << 5),
237 TX_FAST_SPND = (1 << 4),
238 RX_SPND = (1 << 3),
239 TX_SPND = (1 << 2),
240 INTREN = (1 << 1),
241 RUN = (1 << 0),
242
243 CMD0_CLEAR = 0x000F0F7F,
244
245}CMD0_BITS;
246
247typedef enum {
248
249
250 CONDUIT_MODE = (1 << 29),
251
252 RPA = (1 << 19),
253 DRCVPA = (1 << 18),
254 DRCVBC = (1 << 17),
255 PROM = (1 << 16),
256
257 ASTRP_RCV = (1 << 13),
258 RCV_DROP0 = (1 << 12),
259 EMBA = (1 << 11),
260 DXMT2PD = (1 << 10),
261 LTINTEN = (1 << 9),
262 DXMTFCS = (1 << 8),
263
264 APAD_XMT = (1 << 6),
265 DRTY = (1 << 5),
266 INLOOP = (1 << 4),
267 EXLOOP = (1 << 3),
268 REX_RTRY = (1 << 2),
269 REX_UFLO = (1 << 1),
270 REX_LCOL = (1 << 0),
271
272 CMD2_CLEAR = 0x3F7F3F7F,
273
274}CMD2_BITS;
275
276typedef enum {
277
278
279 ASF_INIT_DONE_ALIAS = (1 << 29),
280
281 JUMBO = (1 << 21),
282 VSIZE = (1 << 20),
283 VLONLY = (1 << 19),
284 VL_TAG_DEL = (1 << 18),
285
286 EN_PMGR = (1 << 14),
287 INTLEVEL = (1 << 13),
288 FORCE_FULL_DUPLEX = (1 << 12),
289 FORCE_LINK_STATUS = (1 << 11),
290 APEP = (1 << 10),
291 MPPLBA = (1 << 9),
292
293 RESET_PHY_PULSE = (1 << 2),
294 RESET_PHY = (1 << 1),
295 PHY_RST_POL = (1 << 0),
296
297}CMD3_BITS;
298
299
300typedef enum {
301
302
303 PMAT_SAVE_MATCH = (1 << 4),
304 PMAT_MODE = (1 << 3),
305 MPEN_SW = (1 << 1),
306 LCMODE_SW = (1 << 0),
307
308 CMD7_CLEAR = 0x0000001B
309
310}CMD7_BITS;
311
312
313typedef enum {
314
315 RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20),
316 XMTSP_MASK = (1 << 9) | (1 << 8),
317 XMTSP_128 = (1 << 9),
318 XMTSP_64 = (1 << 8),
319 CACHE_ALIGN = (1 << 4),
320 BURST_LIMIT_MASK = (0xF << 0 ),
321 CTRL1_DEFAULT = 0x00010111,
322
323}CTRL1_BITS;
324
325typedef enum {
326
327 FMDC_MASK = (1 << 9)|(1 << 8),
328 XPHYRST = (1 << 7),
329 XPHYANE = (1 << 6),
330 XPHYFD = (1 << 5),
331 XPHYSP = (1 << 4) | (1 << 3),
332 APDW_MASK = (1 << 2) | (1 << 1) | (1 << 0),
333
334}CTRL2_BITS;
335
336
337typedef enum {
338
339 XMT_RING2_LIMIT = (0xFF << 16),
340 XMT_RING1_LIMIT = (0xFF << 8),
341 XMT_RING0_LIMIT = (0xFF << 0),
342
343}XMT_RING_LIMIT_BITS;
344
345typedef enum {
346
347 AP_REG0_EN = (1 << 15),
348 AP_REG0_ADDR_MASK = (0xF << 8) |(1 << 12),
349 AP_PHY0_ADDR_MASK = (0xF << 0) |(1 << 4),
350
351}AUTOPOLL0_BITS;
352
353
354typedef enum {
355
356 AP_REG1_EN = (1 << 15),
357 AP_REG1_ADDR_MASK = (0xF << 8) |(1 << 12),
358 AP_PRE_SUP1 = (1 << 6),
359 AP_PHY1_DFLT = (1 << 5),
360 AP_PHY1_ADDR_MASK = (0xF << 0) |(1 << 4),
361
362}AUTOPOLL1_BITS;
363
364
365typedef enum {
366
367 AP_REG2_EN = (1 << 15),
368 AP_REG2_ADDR_MASK = (0xF << 8) |(1 << 12),
369 AP_PRE_SUP2 = (1 << 6),
370 AP_PHY2_DFLT = (1 << 5),
371 AP_PHY2_ADDR_MASK = (0xF << 0) |(1 << 4),
372
373}AUTOPOLL2_BITS;
374
375typedef enum {
376
377 AP_REG3_EN = (1 << 15),
378 AP_REG3_ADDR_MASK = (0xF << 8) |(1 << 12),
379 AP_PRE_SUP3 = (1 << 6),
380 AP_PHY3_DFLT = (1 << 5),
381 AP_PHY3_ADDR_MASK = (0xF << 0) |(1 << 4),
382
383}AUTOPOLL3_BITS;
384
385
386typedef enum {
387
388 AP_REG4_EN = (1 << 15),
389 AP_REG4_ADDR_MASK = (0xF << 8) |(1 << 12),
390 AP_PRE_SUP4 = (1 << 6),
391 AP_PHY4_DFLT = (1 << 5),
392 AP_PHY4_ADDR_MASK = (0xF << 0) |(1 << 4),
393
394}AUTOPOLL4_BITS;
395
396
397typedef enum {
398
399 AP_REG5_EN = (1 << 15),
400 AP_REG5_ADDR_MASK = (0xF << 8) |(1 << 12),
401 AP_PRE_SUP5 = (1 << 6),
402 AP_PHY5_DFLT = (1 << 5),
403 AP_PHY5_ADDR_MASK = (0xF << 0) |(1 << 4),
404
405}AUTOPOLL5_BITS;
406
407
408
409
410
411typedef enum {
412
413 AP_VAL_ACTIVE = (1 << 31),
414 AP_VAL_RD_CMD = ( 1 << 29),
415 AP_ADDR = (1 << 18)|(1 << 17)|(1 << 16),
416 AP_VAL = (0xF << 0) | (0xF << 4) |( 0xF << 8) |
417 (0xF << 12),
418
419}AP_VALUE_BITS;
420
421typedef enum {
422
423 DLY_INT_A_R3 = (1 << 31),
424 DLY_INT_A_R2 = (1 << 30),
425 DLY_INT_A_R1 = (1 << 29),
426 DLY_INT_A_R0 = (1 << 28),
427 DLY_INT_A_T3 = (1 << 27),
428 DLY_INT_A_T2 = (1 << 26),
429 DLY_INT_A_T1 = (1 << 25),
430 DLY_INT_A_T0 = ( 1 << 24),
431 EVENT_COUNT_A = (0xF << 16) | (0x1 << 20),
432 MAX_DELAY_TIME_A = (0xF << 0) | (0xF << 4) | (1 << 8)|
433 (1 << 9) | (1 << 10),
434
435}DLY_INT_A_BITS;
436
437typedef enum {
438
439 DLY_INT_B_R3 = (1 << 31),
440 DLY_INT_B_R2 = (1 << 30),
441 DLY_INT_B_R1 = (1 << 29),
442 DLY_INT_B_R0 = (1 << 28),
443 DLY_INT_B_T3 = (1 << 27),
444 DLY_INT_B_T2 = (1 << 26),
445 DLY_INT_B_T1 = (1 << 25),
446 DLY_INT_B_T0 = ( 1 << 24),
447 EVENT_COUNT_B = (0xF << 16) | (0x1 << 20),
448 MAX_DELAY_TIME_B = (0xF << 0) | (0xF << 4) | (1 << 8)|
449 (1 << 9) | (1 << 10),
450}DLY_INT_B_BITS;
451
452
453
454typedef enum {
455
456 PAUSE_LEN_CHG = (1 << 30),
457 FTPE = (1 << 22),
458 FRPE = (1 << 21),
459 NAPA = (1 << 20),
460 NPA = (1 << 19),
461 FIXP = ( 1 << 18),
462 FCCMD = ( 1 << 16),
463 PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12),
464
465}FLOW_CONTROL_BITS;
466
467
468typedef enum {
469
470 PHY_CMD_ACTIVE = (1 << 31),
471 PHY_WR_CMD = (1 << 30),
472 PHY_RD_CMD = (1 << 29),
473 PHY_RD_ERR = (1 << 28),
474 PHY_PRE_SUP = (1 << 27),
475 PHY_ADDR = (1 << 21) | (1 << 22) | (1 << 23)|
476 (1 << 24) |(1 << 25),
477 PHY_REG_ADDR = (1 << 16) | (1 << 17) | (1 << 18)| (1 << 19) | (1 << 20),
478 PHY_DATA = (0xF << 0)|(0xF << 4) |(0xF << 8)|
479 (0xF << 12),
480
481}PHY_ACCESS_BITS;
482
483
484
485typedef enum {
486 PMR_ACTIVE = (1 << 31),
487 PMR_WR_CMD = (1 << 30),
488 PMR_RD_CMD = (1 << 29),
489 PMR_BANK = (1 <<28),
490 PMR_ADDR = (0xF << 16)|(1 << 20)|(1 << 21)|
491 (1 << 22),
492 PMR_B4 = (0xF << 0) | (0xF << 4),
493}PMAT0_BITS;
494
495
496
497typedef enum {
498 PMR_B3 = (0xF << 24) | (0xF <<28),
499 PMR_B2 = (0xF << 16) |(0xF << 20),
500 PMR_B1 = (0xF << 8) | (0xF <<12),
501 PMR_B0 = (0xF << 0)|(0xF << 4),
502}PMAT1_BITS;
503
504
505
506
507
508
509
510#define rcv_miss_pkts 0x00
511#define rcv_octets 0x01
512#define rcv_broadcast_pkts 0x02
513#define rcv_multicast_pkts 0x03
514#define rcv_undersize_pkts 0x04
515#define rcv_oversize_pkts 0x05
516#define rcv_fragments 0x06
517#define rcv_jabbers 0x07
518#define rcv_unicast_pkts 0x08
519#define rcv_alignment_errors 0x09
520#define rcv_fcs_errors 0x0A
521#define rcv_good_octets 0x0B
522#define rcv_mac_ctrl 0x0C
523#define rcv_flow_ctrl 0x0D
524#define rcv_pkts_64_octets 0x0E
525#define rcv_pkts_65to127_octets 0x0F
526#define rcv_pkts_128to255_octets 0x10
527#define rcv_pkts_256to511_octets 0x11
528#define rcv_pkts_512to1023_octets 0x12
529#define rcv_pkts_1024to1518_octets 0x13
530#define rcv_unsupported_opcode 0x14
531#define rcv_symbol_errors 0x15
532#define rcv_drop_pkts_ring1 0x16
533#define rcv_drop_pkts_ring2 0x17
534#define rcv_drop_pkts_ring3 0x18
535#define rcv_drop_pkts_ring4 0x19
536#define rcv_jumbo_pkts 0x1A
537
538#define xmt_underrun_pkts 0x20
539#define xmt_octets 0x21
540#define xmt_packets 0x22
541#define xmt_broadcast_pkts 0x23
542#define xmt_multicast_pkts 0x24
543#define xmt_collisions 0x25
544#define xmt_unicast_pkts 0x26
545#define xmt_one_collision 0x27
546#define xmt_multiple_collision 0x28
547#define xmt_deferred_transmit 0x29
548#define xmt_late_collision 0x2A
549#define xmt_excessive_defer 0x2B
550#define xmt_loss_carrier 0x2C
551#define xmt_excessive_collision 0x2D
552#define xmt_back_pressure 0x2E
553#define xmt_flow_ctrl 0x2F
554#define xmt_pkts_64_octets 0x30
555#define xmt_pkts_65to127_octets 0x31
556#define xmt_pkts_128to255_octets 0x32
557#define xmt_pkts_256to511_octets 0x33
558#define xmt_pkts_512to1023_octets 0x34
559#define xmt_pkts_1024to1518_octet 0x35
560#define xmt_oversize_pkts 0x36
561#define xmt_jumbo_pkts 0x37
562
563
564
565
566#define PCI_VENDOR_ID_AMD 0x1022
567#define PCI_DEVICE_ID_AMD8111E_7462 0x7462
568
569#define MAX_UNITS 8
570
571#define NUM_TX_BUFFERS 32
572#define NUM_RX_BUFFERS 32
573
574#define TX_BUFF_MOD_MASK 31
575#define RX_BUFF_MOD_MASK 31
576
577#define NUM_TX_RING_DR 32
578#define NUM_RX_RING_DR 32
579
580#define TX_RING_DR_MOD_MASK 31
581#define RX_RING_DR_MOD_MASK 31
582
583#define MAX_FILTER_SIZE 64
584#define AMD8111E_MIN_MTU 60
585#define AMD8111E_MAX_MTU 9000
586
587#define PKT_BUFF_SZ 1536
588#define MIN_PKT_LEN 60
589
590#define AMD8111E_TX_TIMEOUT (3 * HZ)
591#define SOFT_TIMER_FREQ 0xBEBC
592#define DELAY_TIMER_CONV 50
593
594#define OPTION_VLAN_ENABLE 0x0001
595#define OPTION_JUMBO_ENABLE 0x0002
596#define OPTION_MULTICAST_ENABLE 0x0004
597#define OPTION_WOL_ENABLE 0x0008
598#define OPTION_WAKE_MAGIC_ENABLE 0x0010
599#define OPTION_WAKE_PHY_ENABLE 0x0020
600#define OPTION_INTR_COAL_ENABLE 0x0040
601#define OPTION_DYN_IPG_ENABLE 0x0080
602
603#define PHY_REG_ADDR_MASK 0x1f
604
605
606#define DEFAULT_IPG 0x60
607#define IFS1_DELTA 36
608#define IPG_CONVERGE_JIFFIES (HZ/2)
609#define IPG_STABLE_TIME 5
610#define MIN_IPG 96
611#define MAX_IPG 255
612#define IPG_STEP 16
613#define CSTATE 1
614#define SSTATE 2
615
616
617#define REPEAT_CNT 10
618
619
620typedef enum {
621
622 OWN_BIT = (1 << 15),
623 ADD_FCS_BIT = (1 << 13),
624 LTINT_BIT = (1 << 12),
625 STP_BIT = (1 << 9),
626 ENP_BIT = (1 << 8),
627 KILL_BIT = (1 << 6),
628 TCC_VLAN_INSERT = (1 << 1),
629 TCC_VLAN_REPLACE = (1 << 1) |( 1<< 0),
630
631}TX_FLAG_BITS;
632
633typedef enum {
634 ERR_BIT = (1 << 14),
635 FRAM_BIT = (1 << 13),
636 OFLO_BIT = (1 << 12),
637 CRC_BIT = (1 << 11),
638 PAM_BIT = (1 << 6),
639 LAFM_BIT = (1 << 5),
640 BAM_BIT = (1 << 4),
641 TT_VLAN_TAGGED = (1 << 3) |(1 << 2),
642 TT_PRTY_TAGGED = (1 << 3),
643
644}RX_FLAG_BITS;
645
646#define RESET_RX_FLAGS 0x0000
647#define TT_MASK 0x000c
648#define TCC_MASK 0x0003
649
650
651#define AMD8111E_REG_DUMP_LEN 13*sizeof(u32)
652
653
654
655struct amd8111e_tx_dr{
656
657 __le16 buff_count;
658
659 __le16 tx_flags;
660
661 __le16 tag_ctrl_info;
662
663 __le16 tag_ctrl_cmd;
664
665 __le32 buff_phy_addr;
666
667 __le32 reserved;
668};
669
670struct amd8111e_rx_dr{
671
672 __le32 reserved;
673
674 __le16 msg_count;
675
676 __le16 tag_ctrl_info;
677
678 __le16 buff_count;
679
680 __le16 rx_flags;
681
682 __le32 buff_phy_addr;
683
684};
685struct amd8111e_link_config{
686
687#define SPEED_INVALID 0xffff
688#define DUPLEX_INVALID 0xff
689#define AUTONEG_INVALID 0xff
690
691 unsigned long orig_phy_option;
692 u16 speed;
693 u8 duplex;
694 u8 autoneg;
695 u8 reserved;
696};
697
698enum coal_type{
699
700 NO_COALESCE,
701 LOW_COALESCE,
702 MEDIUM_COALESCE,
703 HIGH_COALESCE,
704
705};
706
707enum coal_mode{
708 RX_INTR_COAL,
709 TX_INTR_COAL,
710 DISABLE_COAL,
711 ENABLE_COAL,
712
713};
714#define MAX_TIMEOUT 40
715#define MAX_EVENT_COUNT 31
716struct amd8111e_coalesce_conf{
717
718 unsigned int rx_timeout;
719 unsigned int rx_event_count;
720 unsigned long rx_packets;
721 unsigned long rx_prev_packets;
722 unsigned long rx_bytes;
723 unsigned long rx_prev_bytes;
724 unsigned int rx_coal_type;
725
726 unsigned int tx_timeout;
727 unsigned int tx_event_count;
728 unsigned long tx_packets;
729 unsigned long tx_prev_packets;
730 unsigned long tx_bytes;
731 unsigned long tx_prev_bytes;
732 unsigned int tx_coal_type;
733
734};
735struct ipg_info{
736
737 unsigned int ipg_state;
738 unsigned int ipg;
739 unsigned int current_ipg;
740 unsigned int col_cnt;
741 unsigned int diff_col_cnt;
742 unsigned int timer_tick;
743 unsigned int prev_ipg;
744 struct timer_list ipg_timer;
745};
746
747struct amd8111e_priv{
748
749 struct amd8111e_tx_dr* tx_ring;
750 struct amd8111e_rx_dr* rx_ring;
751 dma_addr_t tx_ring_dma_addr;
752 dma_addr_t rx_ring_dma_addr;
753 const char *name;
754 struct pci_dev *pci_dev;
755 struct net_device* amd8111e_net_dev;
756
757 struct sk_buff *tx_skbuff[NUM_TX_BUFFERS];
758 struct sk_buff *rx_skbuff[NUM_RX_BUFFERS];
759
760 dma_addr_t tx_dma_addr[NUM_TX_BUFFERS];
761 dma_addr_t rx_dma_addr[NUM_RX_BUFFERS];
762
763 void __iomem *mmio;
764
765 struct napi_struct napi;
766
767 spinlock_t lock;
768 unsigned long rx_idx, tx_idx;
769 unsigned long tx_complete_idx;
770 unsigned long tx_ring_complete_idx;
771 unsigned long tx_ring_idx;
772 unsigned int rx_buff_len;
773 int options;
774
775 unsigned long ext_phy_option;
776 int ext_phy_addr;
777 u32 ext_phy_id;
778
779 struct amd8111e_link_config link_config;
780 int pm_cap;
781
782 struct net_device *next;
783 int mii;
784 struct mii_if_info mii_if;
785 char opened;
786 unsigned int drv_rx_errors;
787 struct amd8111e_coalesce_conf coal_conf;
788
789 struct ipg_info ipg_data;
790
791};
792
793
794
795#define amd8111e_writeq(_UlData,_memMap) \
796 writel(*(u32*)(&_UlData), _memMap); \
797 writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
798
799
800typedef enum {
801 SPEED_AUTONEG,
802 SPEED10_HALF,
803 SPEED10_FULL,
804 SPEED100_HALF,
805 SPEED100_FULL,
806}EXT_PHY_OPTION;
807
808static int card_idx;
809static int speed_duplex[MAX_UNITS] = { 0, };
810static bool coalesce[MAX_UNITS] = { [ 0 ... MAX_UNITS-1] = true };
811static bool dynamic_ipg[MAX_UNITS] = { [ 0 ... MAX_UNITS-1] = false };
812static unsigned int chip_version;
813
814#endif
815
816