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17#ifndef DEBUG_H
18#define DEBUG_H
19
20#include "hw.h"
21#include "rc.h"
22#include "dfs_debug.h"
23
24struct ath_txq;
25struct ath_buf;
26
27#ifdef CONFIG_ATH9K_DEBUGFS
28#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
29#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
30#else
31#define TX_STAT_INC(q, c) do { } while (0)
32#define RESET_STAT_INC(sc, type) do { } while (0)
33#endif
34
35enum ath_reset_type {
36 RESET_TYPE_BB_HANG,
37 RESET_TYPE_BB_WATCHDOG,
38 RESET_TYPE_FATAL_INT,
39 RESET_TYPE_TX_ERROR,
40 RESET_TYPE_TX_HANG,
41 RESET_TYPE_PLL_HANG,
42 RESET_TYPE_MAC_HANG,
43 RESET_TYPE_BEACON_STUCK,
44 RESET_TYPE_MCI,
45 __RESET_TYPE_MAX
46};
47
48#ifdef CONFIG_ATH9K_DEBUGFS
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80struct ath_interrupt_stats {
81 u32 total;
82 u32 rxok;
83 u32 rxlp;
84 u32 rxhp;
85 u32 rxeol;
86 u32 rxorn;
87 u32 txok;
88 u32 txeol;
89 u32 txurn;
90 u32 mib;
91 u32 rxphyerr;
92 u32 rx_keycache_miss;
93 u32 swba;
94 u32 bmiss;
95 u32 bnr;
96 u32 cst;
97 u32 gtt;
98 u32 tim;
99 u32 cabend;
100 u32 dtimsync;
101 u32 dtim;
102 u32 bb_watchdog;
103 u32 tsfoor;
104 u32 mci;
105 u32 gen_timer;
106
107
108 u32 sync_cause_all;
109 u32 sync_rtc_irq;
110 u32 sync_mac_irq;
111 u32 eeprom_illegal_access;
112 u32 apb_timeout;
113 u32 pci_mode_conflict;
114 u32 host1_fatal;
115 u32 host1_perr;
116 u32 trcv_fifo_perr;
117 u32 radm_cpl_ep;
118 u32 radm_cpl_dllp_abort;
119 u32 radm_cpl_tlp_abort;
120 u32 radm_cpl_ecrc_err;
121 u32 radm_cpl_timeout;
122 u32 local_timeout;
123 u32 pm_access;
124 u32 mac_awake;
125 u32 mac_asleep;
126 u32 mac_sleep_access;
127};
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158struct ath_tx_stats {
159 u32 tx_pkts_all;
160 u32 tx_bytes_all;
161 u32 queued;
162 u32 completed;
163 u32 xretries;
164 u32 a_aggr;
165 u32 a_queued_hw;
166 u32 a_queued_sw;
167 u32 a_completed;
168 u32 a_retries;
169 u32 a_xretries;
170 u32 fifo_underrun;
171 u32 xtxop;
172 u32 timer_exp;
173 u32 desc_cfg_err;
174 u32 data_underrun;
175 u32 delim_underrun;
176 u32 puttxbuf;
177 u32 txstart;
178 u32 txprocdesc;
179 u32 txfailed;
180};
181
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184
185#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
186#define TXSTATS sc->debug.stats.txstats
187#define PR(str, elem) \
188 do { \
189 len += snprintf(buf + len, size - len, \
190 "%s%13u%11u%10u%10u\n", str, \
191 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem, \
192 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem, \
193 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem, \
194 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
195 } while(0)
196
197#define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
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222struct ath_rx_stats {
223 u32 rx_pkts_all;
224 u32 rx_bytes_all;
225 u32 crc_err;
226 u32 decrypt_crc_err;
227 u32 phy_err;
228 u32 mic_err;
229 u32 pre_delim_crc_err;
230 u32 post_delim_crc_err;
231 u32 decrypt_busy_err;
232 u32 phy_err_stats[ATH9K_PHYERR_MAX];
233 u32 rx_len_err;
234 u32 rx_oom_err;
235 u32 rx_rate_err;
236 u32 rx_too_many_frags_err;
237 u32 rx_beacons;
238 u32 rx_frags;
239};
240
241struct ath_stats {
242 struct ath_interrupt_stats istats;
243 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
244 struct ath_rx_stats rxstats;
245 struct ath_dfs_stats dfs_stats;
246 u32 reset[__RESET_TYPE_MAX];
247};
248
249#define ATH_DBG_MAX_SAMPLES 10
250struct ath_dbg_bb_mac_samp {
251 u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
252 u32 pcu_obs, pcu_cr, noise;
253 struct {
254 u64 jiffies;
255 int8_t rssi_ctl0;
256 int8_t rssi_ctl1;
257 int8_t rssi_ctl2;
258 int8_t rssi_ext0;
259 int8_t rssi_ext1;
260 int8_t rssi_ext2;
261 int8_t rssi;
262 bool isok;
263 u8 rts_fail_cnt;
264 u8 data_fail_cnt;
265 u8 rateindex;
266 u8 qid;
267 u8 tid;
268 u32 ba_low;
269 u32 ba_high;
270 } ts[ATH_DBG_MAX_SAMPLES];
271 struct {
272 u64 jiffies;
273 int8_t rssi_ctl0;
274 int8_t rssi_ctl1;
275 int8_t rssi_ctl2;
276 int8_t rssi_ext0;
277 int8_t rssi_ext1;
278 int8_t rssi_ext2;
279 int8_t rssi;
280 bool is_mybeacon;
281 u8 antenna;
282 u8 rate;
283 } rs[ATH_DBG_MAX_SAMPLES];
284 struct ath_cycle_counters cc;
285 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
286};
287
288struct ath9k_debug {
289 struct dentry *debugfs_phy;
290 u32 regidx;
291 struct ath_stats stats;
292#ifdef CONFIG_ATH9K_MAC_DEBUG
293 spinlock_t samp_lock;
294 struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
295 u8 sampidx;
296 u8 tsidx;
297 u8 rsidx;
298#endif
299};
300
301int ath9k_init_debug(struct ath_hw *ah);
302
303void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
304void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
305 struct ath_tx_status *ts, struct ath_txq *txq,
306 unsigned int flags);
307void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
308int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
309 struct ieee80211_vif *vif, int sset);
310void ath9k_get_et_stats(struct ieee80211_hw *hw,
311 struct ieee80211_vif *vif,
312 struct ethtool_stats *stats, u64 *data);
313void ath9k_get_et_strings(struct ieee80211_hw *hw,
314 struct ieee80211_vif *vif,
315 u32 sset, u8 *data);
316void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
317 struct ieee80211_vif *vif,
318 struct ieee80211_sta *sta,
319 struct dentry *dir);
320void ath9k_sta_remove_debugfs(struct ieee80211_hw *hw,
321 struct ieee80211_vif *vif,
322 struct ieee80211_sta *sta,
323 struct dentry *dir);
324#else
325
326#define RX_STAT_INC(c)
327
328static inline int ath9k_init_debug(struct ath_hw *ah)
329{
330 return 0;
331}
332
333static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
334 enum ath9k_int status)
335{
336}
337
338static inline void ath_debug_stat_tx(struct ath_softc *sc,
339 struct ath_buf *bf,
340 struct ath_tx_status *ts,
341 struct ath_txq *txq,
342 unsigned int flags)
343{
344}
345
346static inline void ath_debug_stat_rx(struct ath_softc *sc,
347 struct ath_rx_status *rs)
348{
349}
350
351#endif
352
353#ifdef CONFIG_ATH9K_MAC_DEBUG
354
355void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
356
357#else
358
359static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
360{
361}
362
363#endif
364
365
366#endif
367