LXR linux/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2009-2012  Realtek Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program; if not, write to the Free Software Foundation, Inc.,
  16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17 *
  18 * The full GNU General Public License is included in this distribution in the
  19 * file called LICENSE.
  20 *
  21 * Contact Information:
  22 * wlanfae <wlanfae@realtek.com>
  23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24 * Hsinchu 300, Taiwan.
  25 *
  26 * Larry Finger <Larry.Finger@lwfinger.net>
  27 *
  28 *****************************************************************************/
  29
  30#ifndef __RTL8723E_PWRSEQ_H__
  31#define __RTL8723E_PWRSEQ_H__
  32
  33#include "pwrseqcmd.h"
  34/*
  35        Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
  36        There are 6 HW Power States:
  37        0: POFF--Power Off
  38        1: PDN--Power Down
  39        2: CARDEMU--Card Emulation
  40        3: ACT--Active Mode
  41        4: LPS--Low Power State
  42        5: SUS--Suspend
  43
  44        The transision from different states are defined below
  45        TRANS_CARDEMU_TO_ACT
  46        TRANS_ACT_TO_CARDEMU
  47        TRANS_CARDEMU_TO_SUS
  48        TRANS_SUS_TO_CARDEMU
  49        TRANS_CARDEMU_TO_PDN
  50        TRANS_ACT_TO_LPS
  51        TRANS_LPS_TO_ACT
  52
  53        TRANS_END
  54*/
  55
  56#define RTL8723A_TRANS_CARDEMU_TO_ACT_STPS      10
  57#define RTL8723A_TRANS_ACT_TO_CARDEMU_STPS      10
  58#define RTL8723A_TRANS_CARDEMU_TO_SUS_STPS      10
  59#define RTL8723A_TRANS_SUS_TO_CARDEMU_STPS      10
  60#define RTL8723A_TRANS_CARDEMU_TO_PDN_STPS      10
  61#define RTL8723A_TRANS_PDN_TO_CARDEMU_STPS      10
  62#define RTL8723A_TRANS_ACT_TO_LPS_STPS          15
  63#define RTL8723A_TRANS_LPS_TO_ACT_STPS          15
  64#define RTL8723A_TRANS_END_STPS                 1
  65
  66
  67#define RTL8723A_TRANS_CARDEMU_TO_ACT                                   \
  68        /* format */                                                    \
  69        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, \
  70         *  comments here*/                                             \
  71        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  72                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},            \
  73                /* disable SW LPS 0x04[10]=0*/                          \
  74        {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  75                PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},     \
  76                /* wait till 0x04[17] = 1    power ready*/              \
  77        {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  78                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},       \
  79                /* release WLON reset  0x04[16]=1*/                     \
  80        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  81                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},            \
  82                /* disable HWPDN 0x04[15]=0*/                           \
  83        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  84                PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},   \
  85        /* disable WL suspend*/                                         \
  86        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  87                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},       \
  88                /* polling until return 0*/                             \
  89        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  90                PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}
  91
  92#define RTL8723A_TRANS_ACT_TO_CARDEMU                                   \
  93        /* format */                                                    \
  94        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, \
  95         *  comments here*/                                             \
  96        {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  97                PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},              \
  98                /*0x1F[7:0] = 0 turn off RF*/                           \
  99        {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 100                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},            \
 101        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 102                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},       \
 103        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 104                PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}
 105
 106#define RTL8723A_TRANS_CARDEMU_TO_SUS                                   \
 107        /* format */                                                    \
 108        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, \
 109         *  comments here*/                                             \
 110        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 111                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3),         \
 112                (BIT(4)|BIT(3))},                                       \
 113                /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/      \
 114        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK |   \
 115                PWR_INTF_SDIO_MSK,                                      \
 116                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},\
 117                 /*0x04[12:11] = 2b'01 enable WL suspend*/              \
 118        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 119                PWR_BASEADDR_MAC,                                       \
 120                PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)},           \
 121                 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/     \
 122        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 123                PWR_BASEADDR_SDIO,                                      \
 124                PWR_CMD_WRITE, BIT(0), BIT(0)},                         \
 125                /*Set SDIO suspend local register*/                     \
 126        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 127                PWR_BASEADDR_SDIO,                                      \
 128                PWR_CMD_POLLING, BIT(1), 0}                             \
 129                /*wait power state to suspend*/
 130
 131#define RTL8723A_TRANS_SUS_TO_CARDEMU                                   \
 132        /* format */                                                    \
 133        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 134        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 135                PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},           \
 136                /*Set SDIO suspend local register*/                     \
 137        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 138                PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},    \
 139                /*wait power state to suspend*/                         \
 140        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 141                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}      \
 142                /*0x04[12:11] = 2b'01enable WL suspend*/
 143
 144#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS                               \
 145        /* format */                                                    \
 146        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 147        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 148        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 149                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},\
 150                /*0x04[12:11] = 2b'01 enable WL suspend*/               \
 151        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 152                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)},       \
 153                /*0x04[10] = 1, enable SW LPS*/                         \
 154        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 155                PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},      \
 156                /*Set SDIO suspend local register*/                     \
 157        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 158                PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}          \
 159                /*wait power state to suspend*/
 160
 161#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU                               \
 162        /* format */                                                    \
 163        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 164        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 165                PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},           \
 166                /*Set SDIO suspend local register*/                     \
 167        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 168                PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},    \
 169                /*wait power state to suspend*/                         \
 170        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 171                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},     \
 172                /*0x04[12:11] = 2b'00enable WL suspend*/                \
 173        {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 174                PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}               \
 175                /*PCIe DMA start*/
 176
 177#define RTL8723A_TRANS_CARDEMU_TO_PDN                                   \
 178        /* format */                                                    \
 179        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 180        {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 181                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},            \
 182                /* 0x04[16] = 0*/\
 183        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 184                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}        \
 185                /* 0x04[15] = 1*/
 186
 187#define RTL8723A_TRANS_PDN_TO_CARDEMU                                   \
 188        /* format */                                                    \
 189        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 190        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 191                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}             \
 192                /* 0x04[15] = 0*/
 193
 194#define RTL8723A_TRANS_ACT_TO_LPS                                       \
 195        /* format */                                                    \
 196        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 197        {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 198                PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},           \
 199                /*PCIe DMA stop*/                                       \
 200        {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 201                PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},           \
 202                /*Tx Pause*/                                            \
 203        {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 204                PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},            \
 205                /*Should be zero if no packet is transmitting*/         \
 206        {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 207                PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},            \
 208                /*Should be zero if no packet is transmitting*/         \
 209        {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 210                PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},            \
 211                /*Should be zero if no packet is transmitting*/         \
 212        {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 213                PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},            \
 214                /*Should be zero if no packet is transmitting*/         \
 215        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 216                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},            \
 217                /*CCK and OFDM are disabled,and clock are gated*/       \
 218        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 219                PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},   \
 220                /*Delay 1us*/                                           \
 221        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 222                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},            \
 223                /*Whole BB is reset*/                                   \
 224        {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 225                PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},           \
 226                /*Reset MAC TRX*/                                       \
 227        {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 228                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},            \
 229                /*check if removed later*/                              \
 230        {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 231                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}        \
 232                /*Respond TxOK to scheduler*/
 233
 234#define RTL8723A_TRANS_LPS_TO_ACT                                       \
 235        /* format */                                                    \
 236        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 237        {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 238                 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84},         \
 239                 /*SDIO RPWM*/                                          \
 240        {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
 241                PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84},           \
 242                /*USB RPWM*/                                            \
 243        {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 244                PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84},           \
 245                /*PCIe RPWM*/                                           \
 246        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 247                 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS},  \
 248                /*Delay*/                                               \
 249        {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 250                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},            \
 251                /* 0x08[4] = 0 switch TSF to 40M*/                      \
 252        {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 253                PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0},          \
 254                /*Polling 0x109[7]=0  TSF in 40M*/                      \
 255        {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 256                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0},     \
 257                /*.     0x29[7:6] = 2b'00        enable BB clock*/      \
 258        {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 259                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},       \
 260                /*.     0x101[1] = 1*/                                  \
 261        {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 262                PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},           \
 263                /* 0x100[7:0] = 0xFF enable WMAC TRX*/                  \
 264        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 265                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0),         \
 266                BIT(1)|BIT(0)},                                         \
 267                /* 0x02[1:0] = 2b'11  enable BB macro*/                 \
 268        {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 269                PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}               \
 270                /*.     0x522 = 0*/
 271
 272#define RTL8723A_TRANS_END                                              \
 273        /* format */                                                    \
 274        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 275        {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 276        0, PWR_CMD_END, 0, 0}
 277
 278extern struct
 279wlan_pwr_cfg rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STPS
 280                                    + RTL8723A_TRANS_END_STPS];
 281extern struct
 282wlan_pwr_cfg rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
 283                                     + RTL8723A_TRANS_END_STPS];
 284extern struct
 285wlan_pwr_cfg rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
 286                                        + RTL8723A_TRANS_CARDEMU_TO_PDN_STPS
 287                                        + RTL8723A_TRANS_END_STPS];
 288extern struct
 289wlan_pwr_cfg rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
 290                                       + RTL8723A_TRANS_CARDEMU_TO_PDN_STPS
 291                                       + RTL8723A_TRANS_END_STPS];
 292extern struct
 293wlan_pwr_cfg rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
 294                                   + RTL8723A_TRANS_CARDEMU_TO_SUS_STPS
 295                                   + RTL8723A_TRANS_END_STPS];
 296extern struct
 297wlan_pwr_cfg rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
 298                                  + RTL8723A_TRANS_CARDEMU_TO_SUS_STPS
 299                                  + RTL8723A_TRANS_END_STPS];
 300extern struct
 301wlan_pwr_cfg rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
 302                                 + RTL8723A_TRANS_CARDEMU_TO_PDN_STPS
 303                                 + RTL8723A_TRANS_END_STPS];
 304extern struct
 305wlan_pwr_cfg rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STPS
 306                                     + RTL8723A_TRANS_END_STPS];
 307extern struct
 308wlan_pwr_cfg rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STPS
 309                                     + RTL8723A_TRANS_END_STPS];
 310
 311/* RTL8723 Power Configuration CMDs for PCIe interface */
 312#define Rtl8723_NIC_PWR_ON_FLOW         rtl8723A_power_on_flow
 313#define Rtl8723_NIC_RF_OFF_FLOW         rtl8723A_radio_off_flow
 314#define Rtl8723_NIC_DISABLE_FLOW        rtl8723A_card_disable_flow
 315#define Rtl8723_NIC_ENABLE_FLOW         rtl8723A_card_enable_flow
 316#define Rtl8723_NIC_SUSPEND_FLOW        rtl8723A_suspend_flow
 317#define Rtl8723_NIC_RESUME_FLOW         rtl8723A_resume_flow
 318#define Rtl8723_NIC_PDN_FLOW            rtl8723A_hwpdn_flow
 319#define Rtl8723_NIC_LPS_ENTER_FLOW      rtl8723A_enter_lps_flow
 320#define Rtl8723_NIC_LPS_LEAVE_FLOW      rtl8723A_leave_lps_flow
 321
 322#endif
 323