1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#include <linux/delay.h>
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/device.h>
23#include <linux/pm.h>
24#include <linux/pci.h>
25#include <linux/interrupt.h>
26#include <linux/sfi.h>
27#include <linux/module.h>
28#include <asm/mrst.h>
29#include <asm/intel_scu_ipc.h>
30
31
32#define IPCMSG_WATCHDOG_TIMER 0xF8
33#define IPCMSG_BATTERY 0xEF
34#define IPCMSG_FW_UPDATE 0xFE
35#define IPCMSG_PCNTRL 0xFF
36#define IPCMSG_FW_REVISION 0xF4
37
38
39#define IPC_CMD_PCNTRL_W 0
40#define IPC_CMD_PCNTRL_R 1
41#define IPC_CMD_PCNTRL_M 2
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61#define IPC_BASE_ADDR 0xFF11C000
62#define IPC_MAX_ADDR 0x100
63#define IPC_WWBUF_SIZE 20
64#define IPC_RWBUF_SIZE 20
65#define IPC_I2C_BASE 0xFF12B000
66#define IPC_I2C_MAX_ADDR 0x10
67
68static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
69static void ipc_remove(struct pci_dev *pdev);
70
71struct intel_scu_ipc_dev {
72 struct pci_dev *pdev;
73 void __iomem *ipc_base;
74 void __iomem *i2c_base;
75};
76
77static struct intel_scu_ipc_dev ipcdev;
78
79static int platform;
80
81
82
83
84
85
86#define IPC_READ_BUFFER 0x90
87
88#define IPC_I2C_CNTRL_ADDR 0
89#define I2C_DATA_ADDR 0x04
90
91static DEFINE_MUTEX(ipclock);
92
93
94
95
96
97
98
99static inline void ipc_command(u32 cmd)
100{
101 writel(cmd, ipcdev.ipc_base);
102}
103
104
105
106
107
108
109static inline void ipc_data_writel(u32 data, u32 offset)
110{
111 writel(data, ipcdev.ipc_base + 0x80 + offset);
112}
113
114
115
116
117
118
119
120
121
122static inline u8 ipc_read_status(void)
123{
124 return __raw_readl(ipcdev.ipc_base + 0x04);
125}
126
127static inline u8 ipc_data_readb(u32 offset)
128{
129 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
130}
131
132static inline u32 ipc_data_readl(u32 offset)
133{
134 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
135}
136
137static inline int busy_loop(void)
138{
139 u32 status = 0;
140 u32 loop_count = 0;
141
142 status = ipc_read_status();
143 while (status & 1) {
144 udelay(1);
145 status = ipc_read_status();
146 loop_count++;
147
148 if (loop_count > 100000) {
149 dev_err(&ipcdev.pdev->dev, "IPC timed out");
150 return -ETIMEDOUT;
151 }
152 }
153 if ((status >> 1) & 1)
154 return -EIO;
155
156 return 0;
157}
158
159
160static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
161{
162 int nc;
163 u32 offset = 0;
164 int err;
165 u8 cbuf[IPC_WWBUF_SIZE] = { };
166 u32 *wbuf = (u32 *)&cbuf;
167
168 mutex_lock(&ipclock);
169
170 memset(cbuf, 0, sizeof(cbuf));
171
172 if (ipcdev.pdev == NULL) {
173 mutex_unlock(&ipclock);
174 return -ENODEV;
175 }
176
177 for (nc = 0; nc < count; nc++, offset += 2) {
178 cbuf[offset] = addr[nc];
179 cbuf[offset + 1] = addr[nc] >> 8;
180 }
181
182 if (id == IPC_CMD_PCNTRL_R) {
183 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
184 ipc_data_writel(wbuf[nc], offset);
185 ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op);
186 } else if (id == IPC_CMD_PCNTRL_W) {
187 for (nc = 0; nc < count; nc++, offset += 1)
188 cbuf[offset] = data[nc];
189 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
190 ipc_data_writel(wbuf[nc], offset);
191 ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op);
192 } else if (id == IPC_CMD_PCNTRL_M) {
193 cbuf[offset] = data[0];
194 cbuf[offset + 1] = data[1];
195 ipc_data_writel(wbuf[0], 0);
196 ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
197 }
198
199 err = busy_loop();
200 if (id == IPC_CMD_PCNTRL_R) {
201
202 memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
203 for (nc = 0; nc < count; nc++)
204 data[nc] = ipc_data_readb(nc);
205 }
206 mutex_unlock(&ipclock);
207 return err;
208}
209
210
211
212
213
214
215
216
217
218
219
220int intel_scu_ipc_ioread8(u16 addr, u8 *data)
221{
222 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
223}
224EXPORT_SYMBOL(intel_scu_ipc_ioread8);
225
226
227
228
229
230
231
232
233
234
235
236int intel_scu_ipc_ioread16(u16 addr, u16 *data)
237{
238 u16 x[2] = {addr, addr + 1 };
239 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
240}
241EXPORT_SYMBOL(intel_scu_ipc_ioread16);
242
243
244
245
246
247
248
249
250
251
252
253int intel_scu_ipc_ioread32(u16 addr, u32 *data)
254{
255 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
256 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
257}
258EXPORT_SYMBOL(intel_scu_ipc_ioread32);
259
260
261
262
263
264
265
266
267
268
269
270int intel_scu_ipc_iowrite8(u16 addr, u8 data)
271{
272 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
273}
274EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
275
276
277
278
279
280
281
282
283
284
285
286int intel_scu_ipc_iowrite16(u16 addr, u16 data)
287{
288 u16 x[2] = {addr, addr + 1 };
289 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
290}
291EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
292
293
294
295
296
297
298
299
300
301
302
303int intel_scu_ipc_iowrite32(u16 addr, u32 data)
304{
305 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
306 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
307}
308EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
324{
325 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
326}
327EXPORT_SYMBOL(intel_scu_ipc_readv);
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
344{
345 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
346}
347EXPORT_SYMBOL(intel_scu_ipc_writev);
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
366{
367 u8 data[2] = { bits, mask };
368 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
369}
370EXPORT_SYMBOL(intel_scu_ipc_update_register);
371
372
373
374
375
376
377
378
379
380
381
382
383
384int intel_scu_ipc_simple_command(int cmd, int sub)
385{
386 int err;
387
388 mutex_lock(&ipclock);
389 if (ipcdev.pdev == NULL) {
390 mutex_unlock(&ipclock);
391 return -ENODEV;
392 }
393 ipc_command(sub << 12 | cmd);
394 err = busy_loop();
395 mutex_unlock(&ipclock);
396 return err;
397}
398EXPORT_SYMBOL(intel_scu_ipc_simple_command);
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
414 u32 *out, int outlen)
415{
416 int i, err;
417
418 mutex_lock(&ipclock);
419 if (ipcdev.pdev == NULL) {
420 mutex_unlock(&ipclock);
421 return -ENODEV;
422 }
423
424 for (i = 0; i < inlen; i++)
425 ipc_data_writel(*in++, 4 * i);
426
427 ipc_command((inlen << 16) | (sub << 12) | cmd);
428 err = busy_loop();
429
430 for (i = 0; i < outlen; i++)
431 *out++ = ipc_data_readl(4 * i);
432
433 mutex_unlock(&ipclock);
434 return err;
435}
436EXPORT_SYMBOL(intel_scu_ipc_command);
437
438
439#define IPC_I2C_WRITE 1
440#define IPC_I2C_READ 2
441
442
443
444
445
446
447
448
449
450
451
452
453
454int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
455{
456 u32 cmd = 0;
457
458 mutex_lock(&ipclock);
459 if (ipcdev.pdev == NULL) {
460 mutex_unlock(&ipclock);
461 return -ENODEV;
462 }
463 cmd = (addr >> 24) & 0xFF;
464 if (cmd == IPC_I2C_READ) {
465 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
466
467 mdelay(1);
468 *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR);
469 } else if (cmd == IPC_I2C_WRITE) {
470 writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR);
471 mdelay(1);
472 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
473 } else {
474 dev_err(&ipcdev.pdev->dev,
475 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
476
477 mutex_unlock(&ipclock);
478 return -EIO;
479 }
480 mutex_unlock(&ipclock);
481 return 0;
482}
483EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
484
485
486
487
488
489
490
491
492static irqreturn_t ioc(int irq, void *dev_id)
493{
494 return IRQ_HANDLED;
495}
496
497
498
499
500
501
502
503
504
505static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
506{
507 int err;
508 resource_size_t pci_resource;
509
510 if (ipcdev.pdev)
511 return -EBUSY;
512
513 ipcdev.pdev = pci_dev_get(dev);
514
515 err = pci_enable_device(dev);
516 if (err)
517 return err;
518
519 err = pci_request_regions(dev, "intel_scu_ipc");
520 if (err)
521 return err;
522
523 pci_resource = pci_resource_start(dev, 0);
524 if (!pci_resource)
525 return -ENOMEM;
526
527 if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
528 return -EBUSY;
529
530 ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR);
531 if (!ipcdev.ipc_base)
532 return -ENOMEM;
533
534 ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR);
535 if (!ipcdev.i2c_base) {
536 iounmap(ipcdev.ipc_base);
537 return -ENOMEM;
538 }
539
540 intel_scu_devices_create();
541
542 return 0;
543}
544
545
546
547
548
549
550
551
552
553
554
555static void ipc_remove(struct pci_dev *pdev)
556{
557 free_irq(pdev->irq, &ipcdev);
558 pci_release_regions(pdev);
559 pci_dev_put(ipcdev.pdev);
560 iounmap(ipcdev.ipc_base);
561 iounmap(ipcdev.i2c_base);
562 ipcdev.pdev = NULL;
563 intel_scu_devices_destroy();
564}
565
566static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
567 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)},
568 { 0,}
569};
570MODULE_DEVICE_TABLE(pci, pci_ids);
571
572static struct pci_driver ipc_driver = {
573 .name = "intel_scu_ipc",
574 .id_table = pci_ids,
575 .probe = ipc_probe,
576 .remove = ipc_remove,
577};
578
579
580static int __init intel_scu_ipc_init(void)
581{
582 platform = mrst_identify_cpu();
583 if (platform == 0)
584 return -ENODEV;
585 return pci_register_driver(&ipc_driver);
586}
587
588static void __exit intel_scu_ipc_exit(void)
589{
590 pci_unregister_driver(&ipc_driver);
591}
592
593MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>");
594MODULE_DESCRIPTION("Intel SCU IPC driver");
595MODULE_LICENSE("GPL");
596
597module_init(intel_scu_ipc_init);
598module_exit(intel_scu_ipc_exit);
599