1/* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2012 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8#ifndef _QLA4X_FW_H 9#define _QLA4X_FW_H 10 11 12#define MAX_PRST_DEV_DB_ENTRIES 64 13#define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES 14#define MAX_DEV_DB_ENTRIES 512 15#define MAX_DEV_DB_ENTRIES_40XX 256 16 17/************************************************************************* 18 * 19 * ISP 4010 I/O Register Set Structure and Definitions 20 * 21 *************************************************************************/ 22 23struct port_ctrl_stat_regs { 24 __le32 ext_hw_conf; /* 0x50 R/W */ 25 __le32 rsrvd0; /* 0x54 */ 26 __le32 port_ctrl; /* 0x58 */ 27 __le32 port_status; /* 0x5c */ 28 __le32 rsrvd1[32]; /* 0x60-0xdf */ 29 __le32 gp_out; /* 0xe0 */ 30 __le32 gp_in; /* 0xe4 */ 31 __le32 rsrvd2[5]; /* 0xe8-0xfb */ 32 __le32 port_err_status; /* 0xfc */ 33}; 34 35struct host_mem_cfg_regs { 36 __le32 rsrvd0[12]; /* 0x50-0x79 */ 37 __le32 req_q_out; /* 0x80 */ 38 __le32 rsrvd1[31]; /* 0x84-0xFF */ 39}; 40 41/* 42 * ISP 82xx I/O Register Set structure definitions. 43 */ 44struct device_reg_82xx { 45 __le32 req_q_out; /* 0x0000 (R): Request Queue out-Pointer. */ 46 __le32 reserve1[63]; /* Request Queue out-Pointer. (64 * 4) */ 47 __le32 rsp_q_in; /* 0x0100 (R/W): Response Queue In-Pointer. */ 48 __le32 reserve2[63]; /* Response Queue In-Pointer. */ 49 __le32 rsp_q_out; /* 0x0200 (R/W): Response Queue Out-Pointer. */ 50 __le32 reserve3[63]; /* Response Queue Out-Pointer. */ 51 52 __le32 mailbox_in[8]; /* 0x0300 (R/W): Mail box In registers */ 53 __le32 reserve4[24]; 54 __le32 hint; /* 0x0380 (R/W): Host interrupt register */ 55#define HINT_MBX_INT_PENDING BIT_0 56 __le32 reserve5[31]; 57 __le32 mailbox_out[8]; /* 0x0400 (R): Mail box Out registers */ 58 __le32 reserve6[56]; 59 60 __le32 host_status; /* Offset 0x500 (R): host status */ 61#define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */ 62#define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */ 63 64 __le32 host_int; /* Offset 0x0504 (R/W): Interrupt status. */ 65#define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */ 66}; 67 68/* ISP 83xx I/O Register Set structure */ 69struct device_reg_83xx { 70 __le32 mailbox_in[16]; /* 0x0000 */ 71 __le32 reserve1[496]; /* 0x0040 */ 72 __le32 mailbox_out[16]; /* 0x0800 */ 73 __le32 reserve2[496]; 74 __le32 mbox_int; /* 0x1000 */ 75 __le32 reserve3[63]; 76 __le32 req_q_out; /* 0x1100 */ 77 __le32 reserve4[63]; 78 79 __le32 rsp_q_in; /* 0x1200 */ 80 __le32 reserve5[1919]; 81 82 __le32 req_q_in; /* 0x3000 */ 83 __le32 reserve6[3]; 84 __le32 iocb_int_mask; /* 0x3010 */ 85 __le32 reserve7[3]; 86 __le32 rsp_q_out; /* 0x3020 */ 87 __le32 reserve8[3]; 88 __le32 anonymousbuff; /* 0x3030 */ 89 __le32 mb_int_mask; /* 0x3034 */ 90 91 __le32 host_intr; /* 0x3038 - Host Interrupt Register */ 92 __le32 risc_intr; /* 0x303C - RISC Interrupt Register */ 93 __le32 reserve9[544]; 94 __le32 leg_int_ptr; /* 0x38C0 - Legacy Interrupt Pointer Register */ 95 __le32 leg_int_trig; /* 0x38C4 - Legacy Interrupt Trigger Control */ 96 __le32 leg_int_mask; /* 0x38C8 - Legacy Interrupt Mask Register */ 97}; 98 99#define INT_ENABLE_FW_MB (1 << 2) 100#define INT_MASK_FW_MB (1 << 2) 101 102/* remote register set (access via PCI memory read/write) */ 103struct isp_reg { 104#define MBOX_REG_COUNT 8 105 __le32 mailbox[MBOX_REG_COUNT]; 106 107 __le32 flash_address; /* 0x20 */ 108 __le32 flash_data; 109 __le32 ctrl_status; 110 111 union { 112 struct { 113 __le32 nvram; 114 __le32 reserved1[2]; /* 0x30 */ 115 } __attribute__ ((packed)) isp4010; 116 struct { 117 __le32 intr_mask; 118 __le32 nvram; /* 0x30 */ 119 __le32 semaphore; 120 } __attribute__ ((packed)) isp4022; 121 } u1; 122 123 __le32 req_q_in; /* SCSI Request Queue Producer Index */ 124 __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */ 125 126 __le32 reserved2[4]; /* 0x40 */ 127 128 union { 129 struct { 130 __le32 ext_hw_conf; /* 0x50 */ 131 __le32 flow_ctrl; 132 __le32 port_ctrl; 133 __le32 port_status; 134 135 __le32 reserved3[8]; /* 0x60 */ 136 137 __le32 req_q_out; /* 0x80 */ 138 139 __le32 reserved4[23]; /* 0x84 */ 140 141 __le32 gp_out; /* 0xe0 */ 142 __le32 gp_in; 143 144 __le32 reserved5[5]; 145 146 __le32 port_err_status; /* 0xfc */ 147 } __attribute__ ((packed)) isp4010; 148 struct { 149 union { 150 struct port_ctrl_stat_regs p0; 151 struct host_mem_cfg_regs p1; 152 }; 153 } __attribute__ ((packed)) isp4022; 154 } u2; 155}; /* 256 x100 */ 156 157 158/* Semaphore Defines for 4010 */ 159#define QL4010_DRVR_SEM_BITS 0x00000030 160#define QL4010_GPIO_SEM_BITS 0x000000c0 161#define QL4010_SDRAM_SEM_BITS 0x00000300 162#define QL4010_PHY_SEM_BITS 0x00000c00 163#define QL4010_NVRAM_SEM_BITS 0x00003000 164#define QL4010_FLASH_SEM_BITS 0x0000c000 165 166#define QL4010_DRVR_SEM_MASK 0x00300000 167#define QL4010_GPIO_SEM_MASK 0x00c00000 168#define QL4010_SDRAM_SEM_MASK 0x03000000 169#define QL4010_PHY_SEM_MASK 0x0c000000 170#define QL4010_NVRAM_SEM_MASK 0x30000000 171#define QL4010_FLASH_SEM_MASK 0xc0000000 172 173/* Semaphore Defines for 4022 */ 174#define QL4022_RESOURCE_MASK_BASE_CODE 0x7 175#define QL4022_RESOURCE_BITS_BASE_CODE 0x4 176 177 178#define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16)) 179#define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16)) 180#define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16)) 181#define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16)) 182#define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16)) 183 184/* nvram address for 4032 */ 185#define NVRAM_PORT0_BOOT_MODE 0x03b1 186#define NVRAM_PORT0_BOOT_PRI_TGT 0x03b2 187#define NVRAM_PORT0_BOOT_SEC_TGT 0x03bb 188#define NVRAM_PORT1_BOOT_MODE 0x07b1 189#define NVRAM_PORT1_BOOT_PRI_TGT 0x07b2 190#define NVRAM_PORT1_BOOT_SEC_TGT 0x07bb 191 192 193/* Page # defines for 4022 */ 194#define PORT_CTRL_STAT_PAGE 0 /* 4022 */ 195#define HOST_MEM_CFG_PAGE 1 /* 4022 */ 196#define LOCAL_RAM_CFG_PAGE 2 /* 4022 */ 197#define PROT_STAT_PAGE 3 /* 4022 */ 198 199/* Register Mask - sets corresponding mask bits in the upper word */ 200static inline uint32_t set_rmask(uint32_t val) 201{ 202 return (val & 0xffff) | (val << 16); 203} 204 205 206static inline uint32_t clr_rmask(uint32_t val) 207{ 208 return 0 | (val << 16); 209} 210 211/* ctrl_status definitions */ 212#define CSR_SCSI_PAGE_SELECT 0x00000003 213#define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */ 214#define CSR_SCSI_RESET_INTR 0x00000008 215#define CSR_SCSI_COMPLETION_INTR 0x00000010 216#define CSR_SCSI_PROCESSOR_INTR 0x00000020 217#define CSR_INTR_RISC 0x00000040 218#define CSR_BOOT_ENABLE 0x00000080 219#define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */ 220#define CSR_FUNC_NUM 0x00000700 /* 4022 */ 221#define CSR_NET_RESET_INTR 0x00000800 /* 4010 */ 222#define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */ 223#define CSR_FATAL_ERROR 0x00004000 224#define CSR_SOFT_RESET 0x00008000 225#define ISP_CONTROL_FN_MASK CSR_FUNC_NUM 226#define ISP_CONTROL_FN0_SCSI 0x0500 227#define ISP_CONTROL_FN1_SCSI 0x0700 228 229#define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\ 230 CSR_SCSI_PROCESSOR_INTR |\ 231 CSR_SCSI_RESET_INTR) 232 233/* ISP InterruptMask definitions */ 234#define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */ 235 236/* ISP 4022 nvram definitions */ 237#define NVR_WRITE_ENABLE 0x00000010 /* 4022 */ 238 239#define QL4010_NVRAM_SIZE 0x200 240#define QL40X2_NVRAM_SIZE 0x800 241 242/* ISP port_status definitions */ 243 244/* ISP Semaphore definitions */ 245 246/* ISP General Purpose Output definitions */ 247#define GPOR_TOPCAT_RESET 0x00000004 248 249/* shadow registers (DMA'd from HA to system memory. read only) */ 250struct shadow_regs { 251 /* SCSI Request Queue Consumer Index */ 252 __le32 req_q_out; /* 0 x0 R */ 253 254 /* SCSI Completion Queue Producer Index */ 255 __le32 rsp_q_in; /* 4 x4 R */ 256}; /* 8 x8 */ 257 258 259/* External hardware configuration register */ 260union external_hw_config_reg { 261 struct { 262 /* FIXME: Do we even need this? All values are 263 * referred to by 16 bit quantities. Platform and 264 * endianess issues. */ 265 __le32 bReserved0:1; 266 __le32 bSDRAMProtectionMethod:2; 267 __le32 bSDRAMBanks:1; 268 __le32 bSDRAMChipWidth:1; 269 __le32 bSDRAMChipSize:2; 270 __le32 bParityDisable:1; 271 __le32 bExternalMemoryType:1; 272 __le32 bFlashBIOSWriteEnable:1; 273 __le32 bFlashUpperBankSelect:1; 274 __le32 bWriteBurst:2; 275 __le32 bReserved1:3; 276 __le32 bMask:16; 277 }; 278 uint32_t Asuint32_t; 279}; 280 281/* 82XX Support start */ 282/* 82xx Default FLT Addresses */ 283#define FA_FLASH_LAYOUT_ADDR_82 0xFC400 284#define FA_FLASH_DESCR_ADDR_82 0xFC000 285#define FA_BOOT_LOAD_ADDR_82 0x04000 286#define FA_BOOT_CODE_ADDR_82 0x20000 287#define FA_RISC_CODE_ADDR_82 0x40000 288#define FA_GOLD_RISC_CODE_ADDR_82 0x80000 289#define FA_FLASH_ISCSI_CHAP 0x540000 290#define FA_FLASH_CHAP_SIZE 0xC0000 291 292/* Flash Description Table */ 293struct qla_fdt_layout { 294 uint8_t sig[4]; 295 uint16_t version; 296 uint16_t len; 297 uint16_t checksum; 298 uint8_t unused1[2]; 299 uint8_t model[16]; 300 uint16_t man_id; 301 uint16_t id; 302 uint8_t flags; 303 uint8_t erase_cmd; 304 uint8_t alt_erase_cmd; 305 uint8_t wrt_enable_cmd; 306 uint8_t wrt_enable_bits; 307 uint8_t wrt_sts_reg_cmd; 308 uint8_t unprotect_sec_cmd; 309 uint8_t read_man_id_cmd; 310 uint32_t block_size; 311 uint32_t alt_block_size; 312 uint32_t flash_size; 313 uint32_t wrt_enable_data; 314 uint8_t read_id_addr_len; 315 uint8_t wrt_disable_bits; 316 uint8_t read_dev_id_len; 317 uint8_t chip_erase_cmd; 318 uint16_t read_timeout; 319 uint8_t protect_sec_cmd; 320 uint8_t unused2[65]; 321}; 322 323/* Flash Layout Table */ 324 325struct qla_flt_location { 326 uint8_t sig[4]; 327 uint16_t start_lo; 328 uint16_t start_hi; 329 uint8_t version; 330 uint8_t unused[5]; 331 uint16_t checksum; 332}; 333 334struct qla_flt_header { 335 uint16_t version; 336 uint16_t length; 337 uint16_t checksum; 338 uint16_t unused; 339}; 340 341/* 82xx FLT Regions */ 342#define FLT_REG_FDT 0x1a 343#define FLT_REG_FLT 0x1c 344#define FLT_REG_BOOTLOAD_82 0x72 345#define FLT_REG_FW_82 0x74 346#define FLT_REG_FW_82_1 0x97 347#define FLT_REG_GOLD_FW_82 0x75 348#define FLT_REG_BOOT_CODE_82 0x78 349#define FLT_REG_ISCSI_PARAM 0x65 350#define FLT_REG_ISCSI_CHAP 0x63 351 352struct qla_flt_region { 353 uint32_t code; 354 uint32_t size; 355 uint32_t start; 356 uint32_t end; 357}; 358 359/************************************************************************* 360 * 361 * Mailbox Commands Structures and Definitions 362 * 363 *************************************************************************/ 364 365/* Mailbox command definitions */ 366#define MBOX_CMD_ABOUT_FW 0x0009 367#define MBOX_CMD_PING 0x000B 368#define PING_IPV6_PROTOCOL_ENABLE 0x1 369#define PING_IPV6_LINKLOCAL_ADDR 0x4 370#define PING_IPV6_ADDR0 0x8 371#define PING_IPV6_ADDR1 0xC 372#define MBOX_CMD_ENABLE_INTRS 0x0010 373#define INTR_DISABLE 0 374#define INTR_ENABLE 1 375#define MBOX_CMD_STOP_FW 0x0014 376#define MBOX_CMD_ABORT_TASK 0x0015 377#define MBOX_CMD_LUN_RESET 0x0016 378#define MBOX_CMD_TARGET_WARM_RESET 0x0017 379#define MBOX_CMD_GET_MANAGEMENT_DATA 0x001E 380#define MBOX_CMD_GET_FW_STATUS 0x001F 381#define MBOX_CMD_SET_ISNS_SERVICE 0x0021 382#define ISNS_DISABLE 0 383#define ISNS_ENABLE 1 384#define MBOX_CMD_COPY_FLASH 0x0024 385#define MBOX_CMD_WRITE_FLASH 0x0025 386#define MBOX_CMD_READ_FLASH 0x0026 387#define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031 388#define MBOX_CMD_CONN_OPEN 0x0074 389#define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056 390#define LOGOUT_OPTION_CLOSE_SESSION 0x0002 391#define LOGOUT_OPTION_RELOGIN 0x0004 392#define LOGOUT_OPTION_FREE_DDB 0x0008 393#define MBOX_CMD_SET_PARAM 0x0059 394#define SET_DRVR_VERSION 0x200 395#define MAX_DRVR_VER_LEN 24 396#define MBOX_CMD_EXECUTE_IOCB_A64 0x005A 397#define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060 398#define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061 399#define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062 400#define MBOX_CMD_SET_DATABASE_ENTRY 0x0063 401#define MBOX_CMD_GET_DATABASE_ENTRY 0x0064 402#define DDB_DS_UNASSIGNED 0x00 403#define DDB_DS_NO_CONNECTION_ACTIVE 0x01 404#define DDB_DS_DISCOVERY 0x02 405#define DDB_DS_SESSION_ACTIVE 0x04 406#define DDB_DS_SESSION_FAILED 0x06 407#define DDB_DS_LOGIN_IN_PROCESS 0x07 408#define MBOX_CMD_GET_FW_STATE 0x0069 409#define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A 410#define MBOX_CMD_GET_SYS_INFO 0x0078 411#define MBOX_CMD_GET_NVRAM 0x0078 /* For 40xx */ 412#define MBOX_CMD_SET_NVRAM 0x0079 /* For 40xx */ 413#define MBOX_CMD_RESTORE_FACTORY_DEFAULTS 0x0087 414#define MBOX_CMD_SET_ACB 0x0088 415#define MBOX_CMD_GET_ACB 0x0089 416#define MBOX_CMD_DISABLE_ACB 0x008A 417#define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE 0x008B 418#define MBOX_CMD_GET_IPV6_DEST_CACHE 0x008C 419#define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST 0x008D 420#define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST 0x008E 421#define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE 0x0090 422#define MBOX_CMD_GET_IP_ADDR_STATE 0x0091 423#define MBOX_CMD_SEND_IPV6_ROUTER_SOL 0x0092 424#define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR 0x0093 425#define MBOX_CMD_MINIDUMP 0x0129 426 427/* Minidump subcommand */ 428#define MINIDUMP_GET_SIZE_SUBCOMMAND 0x00 429#define MINIDUMP_GET_TMPLT_SUBCOMMAND 0x01 430 431/* Mailbox 1 */ 432#define FW_STATE_READY 0x0000 433#define FW_STATE_CONFIG_WAIT 0x0001 434#define FW_STATE_WAIT_AUTOCONNECT 0x0002 435#define FW_STATE_ERROR 0x0004 436#define FW_STATE_CONFIGURING_IP 0x0008 437 438/* Mailbox 3 */ 439#define FW_ADDSTATE_OPTICAL_MEDIA 0x0001 440#define FW_ADDSTATE_DHCPv4_ENABLED 0x0002 441#define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED 0x0004 442#define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED 0x0008 443#define FW_ADDSTATE_LINK_UP 0x0010 444#define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020 445#define FW_ADDSTATE_LINK_SPEED_10MBPS 0x0100 446#define FW_ADDSTATE_LINK_SPEED_100MBPS 0x0200 447#define FW_ADDSTATE_LINK_SPEED_1GBPS 0x0400 448#define FW_ADDSTATE_LINK_SPEED_10GBPS 0x0800 449 450#define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B 451#define IPV6_DEFAULT_DDB_ENTRY 0x0001 452 453#define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074 454#define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */ 455#define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077 456 457#define MBOX_CMD_IDC_ACK 0x0101 458#define MBOX_CMD_PORT_RESET 0x0120 459#define MBOX_CMD_SET_PORT_CONFIG 0x0122 460 461/* Mailbox status definitions */ 462#define MBOX_COMPLETION_STATUS 4 463#define MBOX_STS_BUSY 0x0007 464#define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000 465#define MBOX_STS_COMMAND_COMPLETE 0x4000 466#define MBOX_STS_COMMAND_ERROR 0x4005 467 468#define MBOX_ASYNC_EVENT_STATUS 8 469#define MBOX_ASTS_SYSTEM_ERROR 0x8002 470#define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003 471#define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004 472#define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005 473#define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006 474#define MBOX_ASTS_LINK_UP 0x8010 475#define MBOX_ASTS_LINK_DOWN 0x8011 476#define MBOX_ASTS_DATABASE_CHANGED 0x8014 477#define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015 478#define MBOX_ASTS_SELF_TEST_FAILED 0x8016 479#define MBOX_ASTS_LOGIN_FAILED 0x8017 480#define MBOX_ASTS_DNS 0x8018 481#define MBOX_ASTS_HEARTBEAT 0x8019 482#define MBOX_ASTS_NVRAM_INVALID 0x801A 483#define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B 484#define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C 485#define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D 486#define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F 487#define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021 488#define MBOX_ASTS_DUPLICATE_IP 0x8025 489#define MBOX_ASTS_ARP_COMPLETE 0x8026 490#define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 491#define MBOX_ASTS_RESPONSE_QUEUE_FULL 0x8028 492#define MBOX_ASTS_IP_ADDR_STATE_CHANGED 0x8029 493#define MBOX_ASTS_IPV6_PREFIX_EXPIRED 0x802B 494#define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED 0x802C 495#define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED 0x802D 496#define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD 0x802E 497#define MBOX_ASTS_IDC_COMPLETE 0x8100 498#define MBOX_ASTS_IDC_NOTIFY 0x8101 499#define MBOX_ASTS_TXSCVR_INSERTED 0x8130 500#define MBOX_ASTS_TXSCVR_REMOVED 0x8131 501 502#define ISNS_EVENT_DATA_RECEIVED 0x0000 503#define ISNS_EVENT_CONNECTION_OPENED 0x0001 504#define ISNS_EVENT_CONNECTION_FAILED 0x0002 505#define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022 506#define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 507 508/* ACB State Defines */ 509#define ACB_STATE_UNCONFIGURED 0x00 510#define ACB_STATE_INVALID 0x01 511#define ACB_STATE_ACQUIRING 0x02 512#define ACB_STATE_TENTATIVE 0x03 513#define ACB_STATE_DEPRICATED 0x04 514#define ACB_STATE_VALID 0x05 515#define ACB_STATE_DISABLING 0x06 516 517/* FLASH offsets */ 518#define FLASH_SEGMENT_IFCB 0x04000000 519 520#define FLASH_OPT_RMW_HOLD 0 521#define FLASH_OPT_RMW_INIT 1 522#define FLASH_OPT_COMMIT 2 523#define FLASH_OPT_RMW_COMMIT 3 524 525/*************************************************************************/ 526 527/* Host Adapter Initialization Control Block (from host) */ 528struct addr_ctrl_blk { 529 uint8_t version; /* 00 */ 530#define IFCB_VER_MIN 0x01 531#define IFCB_VER_MAX 0x02 532 uint8_t control; /* 01 */ 533 534 uint16_t fw_options; /* 02-03 */ 535#define FWOPT_HEARTBEAT_ENABLE 0x1000 536#define FWOPT_SESSION_MODE 0x0040 537#define FWOPT_INITIATOR_MODE 0x0020 538#define FWOPT_TARGET_MODE 0x0010 539#define FWOPT_ENABLE_CRBDB 0x8000 540 541 uint16_t exec_throttle; /* 04-05 */ 542 uint8_t zio_count; /* 06 */ 543 uint8_t res0; /* 07 */ 544 uint16_t eth_mtu_size; /* 08-09 */ 545 uint16_t add_fw_options; /* 0A-0B */ 546#define ADFWOPT_SERIALIZE_TASK_MGMT 0x0400 547#define ADFWOPT_AUTOCONN_DISABLE 0x0002 548 549 uint8_t hb_interval; /* 0C */ 550 uint8_t inst_num; /* 0D */ 551 uint16_t res1; /* 0E-0F */ 552 uint16_t rqq_consumer_idx; /* 10-11 */ 553 uint16_t compq_producer_idx; /* 12-13 */ 554 uint16_t rqq_len; /* 14-15 */ 555 uint16_t compq_len; /* 16-17 */ 556 uint32_t rqq_addr_lo; /* 18-1B */ 557 uint32_t rqq_addr_hi; /* 1C-1F */ 558 uint32_t compq_addr_lo; /* 20-23 */ 559 uint32_t compq_addr_hi; /* 24-27 */ 560 uint32_t shdwreg_addr_lo; /* 28-2B */ 561 uint32_t shdwreg_addr_hi; /* 2C-2F */ 562 563 uint16_t iscsi_opts; /* 30-31 */ 564 uint16_t ipv4_tcp_opts; /* 32-33 */ 565#define TCPOPT_DHCP_ENABLE 0x0200 566 uint16_t ipv4_ip_opts; /* 34-35 */ 567#define IPOPT_IPV4_PROTOCOL_ENABLE 0x8000 568#define IPOPT_VLAN_TAGGING_ENABLE 0x2000 569 570 uint16_t iscsi_max_pdu_size; /* 36-37 */ 571 uint8_t ipv4_tos; /* 38 */ 572 uint8_t ipv4_ttl; /* 39 */ 573 uint8_t acb_version; /* 3A */ 574#define ACB_NOT_SUPPORTED 0x00 575#define ACB_SUPPORTED 0x02 /* Capable of ACB Version 2 576 Features */ 577 578 uint8_t res2; /* 3B */ 579 uint16_t def_timeout; /* 3C-3D */ 580 uint16_t iscsi_fburst_len; /* 3E-3F */ 581 uint16_t iscsi_def_time2wait; /* 40-41 */ 582 uint16_t iscsi_def_time2retain; /* 42-43 */ 583 uint16_t iscsi_max_outstnd_r2t; /* 44-45 */ 584 uint16_t conn_ka_timeout; /* 46-47 */ 585 uint16_t ipv4_port; /* 48-49 */ 586 uint16_t iscsi_max_burst_len; /* 4A-4B */ 587 uint32_t res5; /* 4C-4F */ 588 uint8_t ipv4_addr[4]; /* 50-53 */ 589 uint16_t ipv4_vlan_tag; /* 54-55 */ 590 uint8_t ipv4_addr_state; /* 56 */ 591 uint8_t ipv4_cacheid; /* 57 */ 592 uint8_t res6[8]; /* 58-5F */ 593 uint8_t ipv4_subnet[4]; /* 60-63 */ 594 uint8_t res7[12]; /* 64-6F */ 595 uint8_t ipv4_gw_addr[4]; /* 70-73 */ 596 uint8_t res8[0xc]; /* 74-7F */ 597 uint8_t pri_dns_srvr_ip[4];/* 80-83 */ 598 uint8_t sec_dns_srvr_ip[4];/* 84-87 */ 599 uint16_t min_eph_port; /* 88-89 */ 600 uint16_t max_eph_port; /* 8A-8B */ 601 uint8_t res9[4]; /* 8C-8F */ 602 uint8_t iscsi_alias[32];/* 90-AF */ 603 uint8_t res9_1[0x16]; /* B0-C5 */ 604 uint16_t tgt_portal_grp;/* C6-C7 */ 605 uint8_t abort_timer; /* C8 */ 606 uint8_t ipv4_tcp_wsf; /* C9 */ 607 uint8_t res10[6]; /* CA-CF */ 608 uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */ 609 uint8_t ipv4_dhcp_vid_len; /* D4 */ 610 uint8_t ipv4_dhcp_vid[11]; /* D5-DF */ 611 uint8_t res11[20]; /* E0-F3 */ 612 uint8_t ipv4_dhcp_alt_cid_len; /* F4 */ 613 uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */ 614 uint8_t iscsi_name[224]; /* 100-1DF */ 615 uint8_t res12[32]; /* 1E0-1FF */ 616 uint32_t cookie; /* 200-203 */ 617 uint16_t ipv6_port; /* 204-205 */ 618 uint16_t ipv6_opts; /* 206-207 */ 619#define IPV6_OPT_IPV6_PROTOCOL_ENABLE 0x8000 620#define IPV6_OPT_VLAN_TAGGING_ENABLE 0x2000 621 622 uint16_t ipv6_addtl_opts; /* 208-209 */ 623#define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE 0x0002 /* Pri ACB 624 Only */ 625#define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR 0x0001 626 627 uint16_t ipv6_tcp_opts; /* 20A-20B */ 628 uint8_t ipv6_tcp_wsf; /* 20C */ 629 uint16_t ipv6_flow_lbl; /* 20D-20F */ 630 uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */ 631 uint16_t ipv6_vlan_tag; /* 220-221 */ 632 uint8_t ipv6_lnk_lcl_addr_state;/* 222 */ 633 uint8_t ipv6_addr0_state; /* 223 */ 634 uint8_t ipv6_addr1_state; /* 224 */ 635#define IP_ADDRSTATE_UNCONFIGURED 0 636#define IP_ADDRSTATE_INVALID 1 637#define IP_ADDRSTATE_ACQUIRING 2 638#define IP_ADDRSTATE_TENTATIVE 3 639#define IP_ADDRSTATE_DEPRICATED 4 640#define IP_ADDRSTATE_PREFERRED 5 641#define IP_ADDRSTATE_DISABLING 6 642 643 uint8_t ipv6_dflt_rtr_state; /* 225 */ 644#define IPV6_RTRSTATE_UNKNOWN 0 645#define IPV6_RTRSTATE_MANUAL 1 646#define IPV6_RTRSTATE_ADVERTISED 3 647#define IPV6_RTRSTATE_STALE 4 648 649 uint8_t ipv6_traffic_class; /* 226 */ 650 uint8_t ipv6_hop_limit; /* 227 */ 651 uint8_t ipv6_if_id[8]; /* 228-22F */ 652 uint8_t ipv6_addr0[16]; /* 230-23F */ 653 uint8_t ipv6_addr1[16]; /* 240-24F */ 654 uint32_t ipv6_nd_reach_time; /* 250-253 */ 655 uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ 656 uint32_t ipv6_nd_stale_timeout; /* 258-25B */ 657 uint8_t ipv6_dup_addr_detect_count; /* 25C */ 658 uint8_t ipv6_cache_id; /* 25D */ 659 uint8_t res13[18]; /* 25E-26F */ 660 uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ 661 uint8_t res14[140]; /* 274-2FF */ 662}; 663 664#define IP_ADDR_COUNT 4 /* Total 4 IP address supported in one interface 665 * One IPv4, one IPv6 link local and 2 IPv6 666 */ 667 668#define IP_STATE_MASK 0x0F000000 669#define IP_STATE_SHIFT 24 670 671struct init_fw_ctrl_blk { 672 struct addr_ctrl_blk pri; 673/* struct addr_ctrl_blk sec;*/ 674}; 675 676#define PRIMARI_ACB 0 677#define SECONDARY_ACB 1 678 679struct addr_ctrl_blk_def { 680 uint8_t reserved1[1]; /* 00 */ 681 uint8_t control; /* 01 */ 682 uint8_t reserved2[11]; /* 02-0C */ 683 uint8_t inst_num; /* 0D */ 684 uint8_t reserved3[34]; /* 0E-2F */ 685 uint16_t iscsi_opts; /* 30-31 */ 686 uint16_t ipv4_tcp_opts; /* 32-33 */ 687 uint16_t ipv4_ip_opts; /* 34-35 */ 688 uint16_t iscsi_max_pdu_size; /* 36-37 */ 689 uint8_t ipv4_tos; /* 38 */ 690 uint8_t ipv4_ttl; /* 39 */ 691 uint8_t reserved4[2]; /* 3A-3B */ 692 uint16_t def_timeout; /* 3C-3D */ 693 uint16_t iscsi_fburst_len; /* 3E-3F */ 694 uint8_t reserved5[4]; /* 40-43 */ 695 uint16_t iscsi_max_outstnd_r2t; /* 44-45 */ 696 uint8_t reserved6[2]; /* 46-47 */ 697 uint16_t ipv4_port; /* 48-49 */ 698 uint16_t iscsi_max_burst_len; /* 4A-4B */ 699 uint8_t reserved7[4]; /* 4C-4F */ 700 uint8_t ipv4_addr[4]; /* 50-53 */ 701 uint16_t ipv4_vlan_tag; /* 54-55 */ 702 uint8_t ipv4_addr_state; /* 56 */ 703 uint8_t ipv4_cacheid; /* 57 */ 704 uint8_t reserved8[8]; /* 58-5F */ 705 uint8_t ipv4_subnet[4]; /* 60-63 */ 706 uint8_t reserved9[12]; /* 64-6F */ 707 uint8_t ipv4_gw_addr[4]; /* 70-73 */ 708 uint8_t reserved10[84]; /* 74-C7 */ 709 uint8_t abort_timer; /* C8 */ 710 uint8_t ipv4_tcp_wsf; /* C9 */ 711 uint8_t reserved11[10]; /* CA-D3 */ 712 uint8_t ipv4_dhcp_vid_len; /* D4 */ 713 uint8_t ipv4_dhcp_vid[11]; /* D5-DF */ 714 uint8_t reserved12[20]; /* E0-F3 */ 715 uint8_t ipv4_dhcp_alt_cid_len; /* F4 */ 716 uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */ 717 uint8_t iscsi_name[224]; /* 100-1DF */ 718 uint8_t reserved13[32]; /* 1E0-1FF */ 719 uint32_t cookie; /* 200-203 */ 720 uint16_t ipv6_port; /* 204-205 */ 721 uint16_t ipv6_opts; /* 206-207 */ 722 uint16_t ipv6_addtl_opts; /* 208-209 */ 723 uint16_t ipv6_tcp_opts; /* 20A-20B */ 724 uint8_t ipv6_tcp_wsf; /* 20C */ 725 uint16_t ipv6_flow_lbl; /* 20D-20F */ 726 uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */ 727 uint16_t ipv6_vlan_tag; /* 220-221 */ 728 uint8_t ipv6_lnk_lcl_addr_state; /* 222 */ 729 uint8_t ipv6_addr0_state; /* 223 */ 730 uint8_t ipv6_addr1_state; /* 224 */ 731 uint8_t ipv6_dflt_rtr_state; /* 225 */ 732 uint8_t ipv6_traffic_class; /* 226 */ 733 uint8_t ipv6_hop_limit; /* 227 */ 734 uint8_t ipv6_if_id[8]; /* 228-22F */ 735 uint8_t ipv6_addr0[16]; /* 230-23F */ 736 uint8_t ipv6_addr1[16]; /* 240-24F */ 737 uint32_t ipv6_nd_reach_time; /* 250-253 */ 738 uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ 739 uint32_t ipv6_nd_stale_timeout; /* 258-25B */ 740 uint8_t ipv6_dup_addr_detect_count; /* 25C */ 741 uint8_t ipv6_cache_id; /* 25D */ 742 uint8_t reserved14[18]; /* 25E-26F */ 743 uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ 744 uint8_t reserved15[140]; /* 274-2FF */ 745}; 746 747/*************************************************************************/ 748 749#define MAX_CHAP_ENTRIES_40XX 128 750#define MAX_CHAP_ENTRIES_82XX 1024 751#define MAX_RESRV_CHAP_IDX 3 752#define FLASH_CHAP_OFFSET 0x06000000 753 754struct ql4_chap_table { 755 uint16_t link; 756 uint8_t flags; 757 uint8_t secret_len; 758#define MIN_CHAP_SECRET_LEN 12 759#define MAX_CHAP_SECRET_LEN 100 760 uint8_t secret[MAX_CHAP_SECRET_LEN]; 761#define MAX_CHAP_NAME_LEN 256 762 uint8_t name[MAX_CHAP_NAME_LEN]; 763 uint16_t reserved; 764#define CHAP_VALID_COOKIE 0x4092 765#define CHAP_INVALID_COOKIE 0xFFEE 766 uint16_t cookie; 767}; 768 769struct dev_db_entry { 770 uint16_t options; /* 00-01 */ 771#define DDB_OPT_DISC_SESSION 0x10 772#define DDB_OPT_TARGET 0x02 /* device is a target */ 773#define DDB_OPT_IPV6_DEVICE 0x100 774#define DDB_OPT_AUTO_SENDTGTS_DISABLE 0x40 775#define DDB_OPT_IPV6_NULL_LINK_LOCAL 0x800 /* post connection */ 776#define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL 0x800 /* pre connection */ 777 778 uint16_t exec_throttle; /* 02-03 */ 779 uint16_t exec_count; /* 04-05 */ 780 uint16_t res0; /* 06-07 */ 781 uint16_t iscsi_options; /* 08-09 */ 782 uint16_t tcp_options; /* 0A-0B */ 783 uint16_t ip_options; /* 0C-0D */ 784 uint16_t iscsi_max_rcv_data_seg_len; /* 0E-0F */ 785#define BYTE_UNITS 512 786 uint32_t res1; /* 10-13 */ 787 uint16_t iscsi_max_snd_data_seg_len; /* 14-15 */ 788 uint16_t iscsi_first_burst_len; /* 16-17 */ 789 uint16_t iscsi_def_time2wait; /* 18-19 */ 790 uint16_t iscsi_def_time2retain; /* 1A-1B */ 791 uint16_t iscsi_max_outsnd_r2t; /* 1C-1D */ 792 uint16_t ka_timeout; /* 1E-1F */ 793 uint8_t isid[6]; /* 20-25 big-endian, must be converted 794 * to little-endian */ 795 uint16_t tsid; /* 26-27 */ 796 uint16_t port; /* 28-29 */ 797 uint16_t iscsi_max_burst_len; /* 2A-2B */ 798 uint16_t def_timeout; /* 2C-2D */ 799 uint16_t res2; /* 2E-2F */ 800 uint8_t ip_addr[0x10]; /* 30-3F */ 801 uint8_t iscsi_alias[0x20]; /* 40-5F */ 802 uint8_t tgt_addr[0x20]; /* 60-7F */ 803 uint16_t mss; /* 80-81 */ 804 uint16_t res3; /* 82-83 */ 805 uint16_t lcl_port; /* 84-85 */ 806 uint8_t ipv4_tos; /* 86 */ 807 uint16_t ipv6_flow_lbl; /* 87-89 */ 808 uint8_t res4[0x36]; /* 8A-BF */ 809 uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a 810 * pointer to a string so we 811 * don't have to reserve so 812 * much RAM */ 813 uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */ 814 uint8_t res5[0x10]; /* 1B0-1BF */ 815 uint16_t ddb_link; /* 1C0-1C1 */ 816 uint16_t chap_tbl_idx; /* 1C2-1C3 */ 817 uint16_t tgt_portal_grp; /* 1C4-1C5 */ 818 uint8_t tcp_xmt_wsf; /* 1C6 */ 819 uint8_t tcp_rcv_wsf; /* 1C7 */ 820 uint32_t stat_sn; /* 1C8-1CB */ 821 uint32_t exp_stat_sn; /* 1CC-1CF */ 822 uint8_t res6[0x2b]; /* 1D0-1FB */ 823#define DDB_VALID_COOKIE 0x9034 824 uint16_t cookie; /* 1FC-1FD */ 825 uint16_t len; /* 1FE-1FF */ 826}; 827 828/*************************************************************************/ 829 830/* Flash definitions */ 831 832#define FLASH_OFFSET_SYS_INFO 0x02000000 833#define FLASH_DEFAULTBLOCKSIZE 0x20000 834#define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes 835 * for EOF 836 * signature */ 837#define FLASH_RAW_ACCESS_ADDR 0x8e000000 838 839#define BOOT_PARAM_OFFSET_PORT0 0x3b0 840#define BOOT_PARAM_OFFSET_PORT1 0x7b0 841 842#define FLASH_OFFSET_DB_INFO 0x05000000 843#define FLASH_OFFSET_DB_END (FLASH_OFFSET_DB_INFO + 0x7fff) 844 845 846struct sys_info_phys_addr { 847 uint8_t address[6]; /* 00-05 */ 848 uint8_t filler[2]; /* 06-07 */ 849}; 850 851struct flash_sys_info { 852 uint32_t cookie; /* 00-03 */ 853 uint32_t physAddrCount; /* 04-07 */ 854 struct sys_info_phys_addr physAddr[4]; /* 08-27 */ 855 uint8_t vendorId[128]; /* 28-A7 */ 856 uint8_t productId[128]; /* A8-127 */ 857 uint32_t serialNumber; /* 128-12B */ 858 859 /* PCI Configuration values */ 860 uint32_t pciDeviceVendor; /* 12C-12F */ 861 uint32_t pciDeviceId; /* 130-133 */ 862 uint32_t pciSubsysVendor; /* 134-137 */ 863 uint32_t pciSubsysId; /* 138-13B */ 864 865 /* This validates version 1. */ 866 uint32_t crumbs; /* 13C-13F */ 867 868 uint32_t enterpriseNumber; /* 140-143 */ 869 870 uint32_t mtu; /* 144-147 */ 871 uint32_t reserved0; /* 148-14b */ 872 uint32_t crumbs2; /* 14c-14f */ 873 uint8_t acSerialNumber[16]; /* 150-15f */ 874 uint32_t crumbs3; /* 160-16f */ 875 876 /* Leave this last in the struct so it is declared invalid if 877 * any new items are added. 878 */ 879 uint32_t reserved1[39]; /* 170-1ff */ 880}; /* 200 */ 881 882struct mbx_sys_info { 883 uint8_t board_id_str[16]; /* 0-f Keep board ID string first */ 884 /* in this structure for GUI. */ 885 uint16_t board_id; /* 10-11 board ID code */ 886 uint16_t phys_port_cnt; /* 12-13 number of physical network ports */ 887 uint16_t port_num; /* 14-15 network port for this PCI function */ 888 /* (port 0 is first port) */ 889 uint8_t mac_addr[6]; /* 16-1b MAC address for this PCI function */ 890 uint32_t iscsi_pci_func_cnt; /* 1c-1f number of iSCSI PCI functions */ 891 uint32_t pci_func; /* 20-23 this PCI function */ 892 unsigned char serial_number[16]; /* 24-33 serial number string */ 893 uint8_t reserved[12]; /* 34-3f */ 894}; 895 896struct about_fw_info { 897 uint16_t fw_major; /* 00 - 01 */ 898 uint16_t fw_minor; /* 02 - 03 */ 899 uint16_t fw_patch; /* 04 - 05 */ 900 uint16_t fw_build; /* 06 - 07 */ 901 uint8_t fw_build_date[16]; /* 08 - 17 ASCII String */ 902 uint8_t fw_build_time[16]; /* 18 - 27 ASCII String */ 903 uint8_t fw_build_user[16]; /* 28 - 37 ASCII String */ 904 uint16_t fw_load_source; /* 38 - 39 */ 905 /* 1 = Flash Primary, 906 2 = Flash Secondary, 907 3 = Host Download 908 */ 909 uint8_t reserved1[6]; /* 3A - 3F */ 910 uint16_t iscsi_major; /* 40 - 41 */ 911 uint16_t iscsi_minor; /* 42 - 43 */ 912 uint16_t bootload_major; /* 44 - 45 */ 913 uint16_t bootload_minor; /* 46 - 47 */ 914 uint16_t bootload_patch; /* 48 - 49 */ 915 uint16_t bootload_build; /* 4A - 4B */ 916 uint8_t reserved2[180]; /* 4C - FF */ 917}; 918 919struct crash_record { 920 uint16_t fw_major_version; /* 00 - 01 */ 921 uint16_t fw_minor_version; /* 02 - 03 */ 922 uint16_t fw_patch_version; /* 04 - 05 */ 923 uint16_t fw_build_version; /* 06 - 07 */ 924 925 uint8_t build_date[16]; /* 08 - 17 */ 926 uint8_t build_time[16]; /* 18 - 27 */ 927 uint8_t build_user[16]; /* 28 - 37 */ 928 uint8_t card_serial_num[16]; /* 38 - 47 */ 929 930 uint32_t time_of_crash_in_secs; /* 48 - 4B */ 931 uint32_t time_of_crash_in_ms; /* 4C - 4F */ 932 933 uint16_t out_RISC_sd_num_frames; /* 50 - 51 */ 934 uint16_t OAP_sd_num_words; /* 52 - 53 */ 935 uint16_t IAP_sd_num_frames; /* 54 - 55 */ 936 uint16_t in_RISC_sd_num_words; /* 56 - 57 */ 937 938 uint8_t reserved1[28]; /* 58 - 7F */ 939 940 uint8_t out_RISC_reg_dump[256]; /* 80 -17F */ 941 uint8_t in_RISC_reg_dump[256]; /*180 -27F */ 942 uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */ 943}; 944 945struct conn_event_log_entry { 946#define MAX_CONN_EVENT_LOG_ENTRIES 100 947 uint32_t timestamp_sec; /* 00 - 03 seconds since boot */ 948 uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */ 949 uint16_t device_index; /* 08 - 09 */ 950 uint16_t fw_conn_state; /* 0A - 0B */ 951 uint8_t event_type; /* 0C - 0C */ 952 uint8_t error_code; /* 0D - 0D */ 953 uint16_t error_code_detail; /* 0E - 0F */ 954 uint8_t num_consecutive_events; /* 10 - 10 */ 955 uint8_t rsvd[3]; /* 11 - 13 */ 956}; 957 958/************************************************************************* 959 * 960 * IOCB Commands Structures and Definitions 961 * 962 *************************************************************************/ 963#define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */ 964#define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */ 965#define IOCB_MAX_EXT_SENSEDATA_LEN 60 /* Bytes of extended sense data */ 966 967/* IOCB header structure */ 968struct qla4_header { 969 uint8_t entryType; 970#define ET_STATUS 0x03 971#define ET_MARKER 0x04 972#define ET_CONT_T1 0x0A 973#define ET_STATUS_CONTINUATION 0x10 974#define ET_CMND_T3 0x19 975#define ET_PASSTHRU0 0x3A 976#define ET_PASSTHRU_STATUS 0x3C 977#define ET_MBOX_CMD 0x38 978#define ET_MBOX_STATUS 0x39 979 980 uint8_t entryStatus; 981 uint8_t systemDefined; 982#define SD_ISCSI_PDU 0x01 983 uint8_t entryCount; 984 985 /* SyetemDefined definition */ 986}; 987 988/* Generic queue entry structure*/ 989struct queue_entry { 990 uint8_t data[60]; 991 uint32_t signature; 992 993}; 994 995/* 64 bit addressing segment counts*/ 996 997#define COMMAND_SEG_A64 1 998#define CONTINUE_SEG_A64 5 999 1000/* 64 bit addressing segment definition*/
1001 1002struct data_seg_a64 { 1003 struct { 1004 uint32_t addrLow; 1005 uint32_t addrHigh; 1006 1007 } base; 1008 1009 uint32_t count; 1010 1011}; 1012 1013/* Command Type 3 entry structure*/ 1014 1015struct command_t3_entry { 1016 struct qla4_header hdr; /* 00-03 */ 1017 1018 uint32_t handle; /* 04-07 */ 1019 uint16_t target; /* 08-09 */ 1020 uint16_t connection_id; /* 0A-0B */ 1021 1022 uint8_t control_flags; /* 0C */ 1023 1024 /* data direction (bits 5-6) */ 1025#define CF_WRITE 0x20 1026#define CF_READ 0x40 1027#define CF_NO_DATA 0x00 1028 1029 /* task attributes (bits 2-0) */ 1030#define CF_HEAD_TAG 0x03 1031#define CF_ORDERED_TAG 0x02 1032#define CF_SIMPLE_TAG 0x01 1033 1034 /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS 1035 * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS 1036 * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET 1037 * PROPERLY. 1038 */ 1039 uint8_t state_flags; /* 0D */ 1040 uint8_t cmdRefNum; /* 0E */ 1041 uint8_t reserved1; /* 0F */ 1042 uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */ 1043 struct scsi_lun lun; /* FCP LUN (BE). */ 1044 uint32_t cmdSeqNum; /* 28-2B */ 1045 uint16_t timeout; /* 2C-2D */ 1046 uint16_t dataSegCnt; /* 2E-2F */ 1047 uint32_t ttlByteCnt; /* 30-33 */ 1048 struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */ 1049 1050}; 1051 1052 1053/* Continuation Type 1 entry structure*/ 1054struct continuation_t1_entry { 1055 struct qla4_header hdr; 1056 1057 struct data_seg_a64 dataseg[CONTINUE_SEG_A64]; 1058 1059}; 1060 1061/* Parameterize for 64 or 32 bits */ 1062#define COMMAND_SEG COMMAND_SEG_A64 1063#define CONTINUE_SEG CONTINUE_SEG_A64 1064 1065#define ET_COMMAND ET_CMND_T3 1066#define ET_CONTINUE ET_CONT_T1 1067 1068/* Marker entry structure*/ 1069struct qla4_marker_entry { 1070 struct qla4_header hdr; /* 00-03 */ 1071 1072 uint32_t system_defined; /* 04-07 */ 1073 uint16_t target; /* 08-09 */ 1074 uint16_t modifier; /* 0A-0B */ 1075#define MM_LUN_RESET 0 1076#define MM_TGT_WARM_RESET 1 1077 1078 uint16_t flags; /* 0C-0D */ 1079 uint16_t reserved1; /* 0E-0F */ 1080 struct scsi_lun lun; /* FCP LUN (BE). */ 1081 uint64_t reserved2; /* 18-1F */ 1082 uint64_t reserved3; /* 20-27 */ 1083 uint64_t reserved4; /* 28-2F */ 1084 uint64_t reserved5; /* 30-37 */ 1085 uint64_t reserved6; /* 38-3F */ 1086}; 1087 1088/* Status entry structure*/ 1089struct status_entry { 1090 struct qla4_header hdr; /* 00-03 */ 1091 1092 uint32_t handle; /* 04-07 */ 1093 1094 uint8_t scsiStatus; /* 08 */ 1095#define SCSI_CHECK_CONDITION 0x02 1096 1097 uint8_t iscsiFlags; /* 09 */ 1098#define ISCSI_FLAG_RESIDUAL_UNDER 0x02 1099#define ISCSI_FLAG_RESIDUAL_OVER 0x04 1100 1101 uint8_t iscsiResponse; /* 0A */ 1102 1103 uint8_t completionStatus; /* 0B */ 1104#define SCS_COMPLETE 0x00 1105#define SCS_INCOMPLETE 0x01 1106#define SCS_RESET_OCCURRED 0x04 1107#define SCS_ABORTED 0x05 1108#define SCS_TIMEOUT 0x06 1109#define SCS_DATA_OVERRUN 0x07 1110#define SCS_DATA_UNDERRUN 0x15 1111#define SCS_QUEUE_FULL 0x1C 1112#define SCS_DEVICE_UNAVAILABLE 0x28 1113#define SCS_DEVICE_LOGGED_OUT 0x29 1114 1115 uint8_t reserved1; /* 0C */ 1116 1117 /* state_flags MUST be at the same location as state_flags in 1118 * the Command_T3/4_Entry */ 1119 uint8_t state_flags; /* 0D */ 1120 1121 uint16_t senseDataByteCnt; /* 0E-0F */ 1122 uint32_t residualByteCnt; /* 10-13 */ 1123 uint32_t bidiResidualByteCnt; /* 14-17 */ 1124 uint32_t expSeqNum; /* 18-1B */ 1125 uint32_t maxCmdSeqNum; /* 1C-1F */ 1126 uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */ 1127 1128}; 1129 1130/* Status Continuation entry */ 1131struct status_cont_entry { 1132 struct qla4_header hdr; /* 00-03 */ 1133 uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */ 1134}; 1135 1136struct passthru0 { 1137 struct qla4_header hdr; /* 00-03 */ 1138 uint32_t handle; /* 04-07 */ 1139 uint16_t target; /* 08-09 */ 1140 uint16_t connection_id; /* 0A-0B */ 1141#define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000) 1142 1143 uint16_t control_flags; /* 0C-0D */ 1144#define PT_FLAG_ETHERNET_FRAME 0x8000 1145#define PT_FLAG_ISNS_PDU 0x8000 1146#define PT_FLAG_SEND_BUFFER 0x0200 1147#define PT_FLAG_WAIT_4_RESPONSE 0x0100 1148#define PT_FLAG_ISCSI_PDU 0x1000 1149 1150 uint16_t timeout; /* 0E-0F */ 1151#define PT_DEFAULT_TIMEOUT 30 /* seconds */ 1152 1153 struct data_seg_a64 out_dsd; /* 10-1B */ 1154 uint32_t res1; /* 1C-1F */ 1155 struct data_seg_a64 in_dsd; /* 20-2B */ 1156 uint8_t res2[20]; /* 2C-3F */ 1157}; 1158 1159struct passthru_status { 1160 struct qla4_header hdr; /* 00-03 */ 1161 uint32_t handle; /* 04-07 */ 1162 uint16_t target; /* 08-09 */ 1163 uint16_t connectionID; /* 0A-0B */ 1164 1165 uint8_t completionStatus; /* 0C */ 1166#define PASSTHRU_STATUS_COMPLETE 0x01 1167 1168 uint8_t residualFlags; /* 0D */ 1169 1170 uint16_t timeout; /* 0E-0F */ 1171 uint16_t portNumber; /* 10-11 */ 1172 uint8_t res1[10]; /* 12-1B */ 1173 uint32_t outResidual; /* 1C-1F */ 1174 uint8_t res2[12]; /* 20-2B */ 1175 uint32_t inResidual; /* 2C-2F */ 1176 uint8_t res4[16]; /* 30-3F */ 1177}; 1178 1179struct mbox_cmd_iocb { 1180 struct qla4_header hdr; /* 00-03 */ 1181 uint32_t handle; /* 04-07 */ 1182 uint32_t in_mbox[8]; /* 08-25 */ 1183 uint32_t res1[6]; /* 26-3F */ 1184}; 1185 1186struct mbox_status_iocb { 1187 struct qla4_header hdr; /* 00-03 */ 1188 uint32_t handle; /* 04-07 */ 1189 uint32_t out_mbox[8]; /* 08-25 */ 1190 uint32_t res1[6]; /* 26-3F */ 1191}; 1192 1193/* 1194 * ISP queue - response queue entry definition. 1195 */ 1196struct response { 1197 uint8_t data[60]; 1198 uint32_t signature; 1199#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1200}; 1201 1202struct ql_iscsi_stats { 1203 uint8_t reserved1[656]; /* 0000-028F */ 1204 uint32_t tx_cmd_pdu; /* 0290-0293 */ 1205 uint32_t tx_resp_pdu; /* 0294-0297 */ 1206 uint32_t rx_cmd_pdu; /* 0298-029B */ 1207 uint32_t rx_resp_pdu; /* 029C-029F */ 1208 1209 uint64_t tx_data_octets; /* 02A0-02A7 */ 1210 uint64_t rx_data_octets; /* 02A8-02AF */ 1211 1212 uint32_t hdr_digest_err; /* 02B0–02B3 */ 1213 uint32_t data_digest_err; /* 02B4–02B7 */ 1214 uint32_t conn_timeout_err; /* 02B8–02BB */ 1215 uint32_t framing_err; /* 02BC–02BF */ 1216 1217 uint32_t tx_nopout_pdus; /* 02C0–02C3 */ 1218 uint32_t tx_scsi_cmd_pdus; /* 02C4–02C7 */ 1219 uint32_t tx_tmf_cmd_pdus; /* 02C8–02CB */ 1220 uint32_t tx_login_cmd_pdus; /* 02CC–02CF */ 1221 uint32_t tx_text_cmd_pdus; /* 02D0–02D3 */ 1222 uint32_t tx_scsi_write_pdus; /* 02D4–02D7 */ 1223 uint32_t tx_logout_cmd_pdus; /* 02D8–02DB */ 1224 uint32_t tx_snack_req_pdus; /* 02DC–02DF */ 1225 1226 uint32_t rx_nopin_pdus; /* 02E0–02E3 */ 1227 uint32_t rx_scsi_resp_pdus; /* 02E4–02E7 */ 1228 uint32_t rx_tmf_resp_pdus; /* 02E8–02EB */ 1229 uint32_t rx_login_resp_pdus; /* 02EC–02EF */ 1230 uint32_t rx_text_resp_pdus; /* 02F0–02F3 */ 1231 uint32_t rx_scsi_read_pdus; /* 02F4–02F7 */ 1232 uint32_t rx_logout_resp_pdus; /* 02F8–02FB */ 1233 1234 uint32_t rx_r2t_pdus; /* 02FC–02FF */ 1235 uint32_t rx_async_pdus; /* 0300–0303 */ 1236 uint32_t rx_reject_pdus; /* 0304–0307 */ 1237 1238 uint8_t reserved2[264]; /* 0x0308 - 0x040F */ 1239}; 1240 1241#define QLA8XXX_DBG_STATE_ARRAY_LEN 16 1242#define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN 8 1243#define QLA8XXX_DBG_RSVD_ARRAY_LEN 8 1244#define QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN 16 1245#define QLA83XX_SS_OCM_WNDREG_INDEX 3 1246#define QLA83XX_SS_PCI_INDEX 0 1247 1248struct qla4_8xxx_minidump_template_hdr { 1249 uint32_t entry_type; 1250 uint32_t first_entry_offset; 1251 uint32_t size_of_template; 1252 uint32_t capture_debug_level; 1253 uint32_t num_of_entries; 1254 uint32_t version; 1255 uint32_t driver_timestamp; 1256 uint32_t checksum; 1257 1258 uint32_t driver_capture_mask; 1259 uint32_t driver_info_word2; 1260 uint32_t driver_info_word3; 1261 uint32_t driver_info_word4; 1262 1263 uint32_t saved_state_array[QLA8XXX_DBG_STATE_ARRAY_LEN]; 1264 uint32_t capture_size_array[QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN]; 1265 uint32_t ocm_window_reg[QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN]; 1266}; 1267 1268#endif /* _QLA4X_FW_H */ 1269