1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29#ifndef _COMEDI_NI_STC_H
30#define _COMEDI_NI_STC_H
31
32#include "ni_tio.h"
33
34#define _bit15 0x8000
35#define _bit14 0x4000
36#define _bit13 0x2000
37#define _bit12 0x1000
38#define _bit11 0x0800
39#define _bit10 0x0400
40#define _bit9 0x0200
41#define _bit8 0x0100
42#define _bit7 0x0080
43#define _bit6 0x0040
44#define _bit5 0x0020
45#define _bit4 0x0010
46#define _bit3 0x0008
47#define _bit2 0x0004
48#define _bit1 0x0002
49#define _bit0 0x0001
50
51#define NUM_PFI_OUTPUT_SELECT_REGS 6
52
53
54
55#define Interrupt_A_Ack_Register 2
56#define G0_Gate_Interrupt_Ack _bit15
57#define G0_TC_Interrupt_Ack _bit14
58#define AI_Error_Interrupt_Ack _bit13
59#define AI_STOP_Interrupt_Ack _bit12
60#define AI_START_Interrupt_Ack _bit11
61#define AI_START2_Interrupt_Ack _bit10
62#define AI_START1_Interrupt_Ack _bit9
63#define AI_SC_TC_Interrupt_Ack _bit8
64#define AI_SC_TC_Error_Confirm _bit7
65#define G0_TC_Error_Confirm _bit6
66#define G0_Gate_Error_Confirm _bit5
67
68#define AI_Status_1_Register 2
69#define Interrupt_A_St 0x8000
70#define AI_FIFO_Full_St 0x4000
71#define AI_FIFO_Half_Full_St 0x2000
72#define AI_FIFO_Empty_St 0x1000
73#define AI_Overrun_St 0x0800
74#define AI_Overflow_St 0x0400
75#define AI_SC_TC_Error_St 0x0200
76#define AI_START2_St 0x0100
77#define AI_START1_St 0x0080
78#define AI_SC_TC_St 0x0040
79#define AI_START_St 0x0020
80#define AI_STOP_St 0x0010
81#define G0_TC_St 0x0008
82#define G0_Gate_Interrupt_St 0x0004
83#define AI_FIFO_Request_St 0x0002
84#define Pass_Thru_0_Interrupt_St 0x0001
85
86#define AI_Status_2_Register 5
87
88#define Interrupt_B_Ack_Register 3
89enum Interrupt_B_Ack_Bits {
90 G1_Gate_Error_Confirm = _bit1,
91 G1_TC_Error_Confirm = _bit2,
92 AO_BC_TC_Trigger_Error_Confirm = _bit3,
93 AO_BC_TC_Error_Confirm = _bit4,
94 AO_UI2_TC_Error_Confrim = _bit5,
95 AO_UI2_TC_Interrupt_Ack = _bit6,
96 AO_UC_TC_Interrupt_Ack = _bit7,
97 AO_BC_TC_Interrupt_Ack = _bit8,
98 AO_START1_Interrupt_Ack = _bit9,
99 AO_UPDATE_Interrupt_Ack = _bit10,
100 AO_START_Interrupt_Ack = _bit11,
101 AO_STOP_Interrupt_Ack = _bit12,
102 AO_Error_Interrupt_Ack = _bit13,
103 G1_TC_Interrupt_Ack = _bit14,
104 G1_Gate_Interrupt_Ack = _bit15
105};
106
107#define AO_Status_1_Register 3
108#define Interrupt_B_St _bit15
109#define AO_FIFO_Full_St _bit14
110#define AO_FIFO_Half_Full_St _bit13
111#define AO_FIFO_Empty_St _bit12
112#define AO_BC_TC_Error_St _bit11
113#define AO_START_St _bit10
114#define AO_Overrun_St _bit9
115#define AO_START1_St _bit8
116#define AO_BC_TC_St _bit7
117#define AO_UC_TC_St _bit6
118#define AO_UPDATE_St _bit5
119#define AO_UI2_TC_St _bit4
120#define G1_TC_St _bit3
121#define G1_Gate_Interrupt_St _bit2
122#define AO_FIFO_Request_St _bit1
123#define Pass_Thru_1_Interrupt_St _bit0
124
125#define AI_Command_2_Register 4
126#define AI_End_On_SC_TC _bit15
127#define AI_End_On_End_Of_Scan _bit14
128#define AI_START1_Disable _bit11
129#define AI_SC_Save_Trace _bit10
130#define AI_SI_Switch_Load_On_SC_TC _bit9
131#define AI_SI_Switch_Load_On_STOP _bit8
132#define AI_SI_Switch_Load_On_TC _bit7
133#define AI_SC_Switch_Load_On_TC _bit4
134#define AI_STOP_Pulse _bit3
135#define AI_START_Pulse _bit2
136#define AI_START2_Pulse _bit1
137#define AI_START1_Pulse _bit0
138
139#define AO_Command_2_Register 5
140#define AO_End_On_BC_TC(x) (((x) & 0x3) << 14)
141#define AO_Start_Stop_Gate_Enable _bit13
142#define AO_UC_Save_Trace _bit12
143#define AO_BC_Gate_Enable _bit11
144#define AO_BC_Save_Trace _bit10
145#define AO_UI_Switch_Load_On_BC_TC _bit9
146#define AO_UI_Switch_Load_On_Stop _bit8
147#define AO_UI_Switch_Load_On_TC _bit7
148#define AO_UC_Switch_Load_On_BC_TC _bit6
149#define AO_UC_Switch_Load_On_TC _bit5
150#define AO_BC_Switch_Load_On_TC _bit4
151#define AO_Mute_B _bit3
152#define AO_Mute_A _bit2
153#define AO_UPDATE2_Pulse _bit1
154#define AO_START1_Pulse _bit0
155
156#define AO_Status_2_Register 6
157
158#define DIO_Parallel_Input_Register 7
159
160#define AI_Command_1_Register 8
161#define AI_Analog_Trigger_Reset _bit14
162#define AI_Disarm _bit13
163#define AI_SI2_Arm _bit12
164#define AI_SI2_Load _bit11
165#define AI_SI_Arm _bit10
166#define AI_SI_Load _bit9
167#define AI_DIV_Arm _bit8
168#define AI_DIV_Load _bit7
169#define AI_SC_Arm _bit6
170#define AI_SC_Load _bit5
171#define AI_SCAN_IN_PROG_Pulse _bit4
172#define AI_EXTMUX_CLK_Pulse _bit3
173#define AI_LOCALMUX_CLK_Pulse _bit2
174#define AI_SC_TC_Pulse _bit1
175#define AI_CONVERT_Pulse _bit0
176
177#define AO_Command_1_Register 9
178#define AO_Analog_Trigger_Reset _bit15
179#define AO_START_Pulse _bit14
180#define AO_Disarm _bit13
181#define AO_UI2_Arm_Disarm _bit12
182#define AO_UI2_Load _bit11
183#define AO_UI_Arm _bit10
184#define AO_UI_Load _bit9
185#define AO_UC_Arm _bit8
186#define AO_UC_Load _bit7
187#define AO_BC_Arm _bit6
188#define AO_BC_Load _bit5
189#define AO_DAC1_Update_Mode _bit4
190#define AO_LDAC1_Source_Select _bit3
191#define AO_DAC0_Update_Mode _bit2
192#define AO_LDAC0_Source_Select _bit1
193#define AO_UPDATE_Pulse _bit0
194
195#define DIO_Output_Register 10
196#define DIO_Parallel_Data_Out(a) ((a)&0xff)
197#define DIO_Parallel_Data_Mask 0xff
198#define DIO_SDOUT _bit0
199#define DIO_SDIN _bit4
200#define DIO_Serial_Data_Out(a) (((a)&0xff)<<8)
201#define DIO_Serial_Data_Mask 0xff00
202
203#define DIO_Control_Register 11
204#define DIO_Software_Serial_Control _bit11
205#define DIO_HW_Serial_Timebase _bit10
206#define DIO_HW_Serial_Enable _bit9
207#define DIO_HW_Serial_Start _bit8
208#define DIO_Pins_Dir(a) ((a)&0xff)
209#define DIO_Pins_Dir_Mask 0xff
210
211#define AI_Mode_1_Register 12
212#define AI_CONVERT_Source_Select(a) (((a) & 0x1f) << 11)
213#define AI_SI_Source_select(a) (((a) & 0x1f) << 6)
214#define AI_CONVERT_Source_Polarity _bit5
215#define AI_SI_Source_Polarity _bit4
216#define AI_Start_Stop _bit3
217#define AI_Mode_1_Reserved _bit2
218#define AI_Continuous _bit1
219#define AI_Trigger_Once _bit0
220
221#define AI_Mode_2_Register 13
222#define AI_SC_Gate_Enable _bit15
223#define AI_Start_Stop_Gate_Enable _bit14
224#define AI_Pre_Trigger _bit13
225#define AI_External_MUX_Present _bit12
226#define AI_SI2_Initial_Load_Source _bit9
227#define AI_SI2_Reload_Mode _bit8
228#define AI_SI_Initial_Load_Source _bit7
229#define AI_SI_Reload_Mode(a) (((a) & 0x7)<<4)
230#define AI_SI_Write_Switch _bit3
231#define AI_SC_Initial_Load_Source _bit2
232#define AI_SC_Reload_Mode _bit1
233#define AI_SC_Write_Switch _bit0
234
235#define AI_SI_Load_A_Registers 14
236#define AI_SI_Load_B_Registers 16
237#define AI_SC_Load_A_Registers 18
238#define AI_SC_Load_B_Registers 20
239#define AI_SI_Save_Registers 64
240#define AI_SC_Save_Registers 66
241
242#define AI_SI2_Load_A_Register 23
243#define AI_SI2_Load_B_Register 25
244
245#define Joint_Status_1_Register 27
246#define DIO_Serial_IO_In_Progress_St _bit12
247
248#define DIO_Serial_Input_Register 28
249#define Joint_Status_2_Register 29
250enum Joint_Status_2_Bits {
251 AO_TMRDACWRs_In_Progress_St = 0x20,
252};
253
254#define AO_Mode_1_Register 38
255#define AO_UPDATE_Source_Select(x) (((x)&0x1f)<<11)
256#define AO_UI_Source_Select(x) (((x)&0x1f)<<6)
257#define AO_Multiple_Channels _bit5
258#define AO_UPDATE_Source_Polarity _bit4
259#define AO_UI_Source_Polarity _bit3
260#define AO_UC_Switch_Load_Every_TC _bit2
261#define AO_Continuous _bit1
262#define AO_Trigger_Once _bit0
263
264#define AO_Mode_2_Register 39
265#define AO_FIFO_Mode_Mask (0x3 << 14)
266enum AO_FIFO_Mode_Bits {
267 AO_FIFO_Mode_HF_to_F = (3 << 14),
268 AO_FIFO_Mode_F = (2 << 14),
269 AO_FIFO_Mode_HF = (1 << 14),
270 AO_FIFO_Mode_E = (0 << 14),
271};
272#define AO_FIFO_Retransmit_Enable _bit13
273#define AO_START1_Disable _bit12
274#define AO_UC_Initial_Load_Source _bit11
275#define AO_UC_Write_Switch _bit10
276#define AO_UI2_Initial_Load_Source _bit9
277#define AO_UI2_Reload_Mode _bit8
278#define AO_UI_Initial_Load_Source _bit7
279#define AO_UI_Reload_Mode(x) (((x) & 0x7) << 4)
280#define AO_UI_Write_Switch _bit3
281#define AO_BC_Initial_Load_Source _bit2
282#define AO_BC_Reload_Mode _bit1
283#define AO_BC_Write_Switch _bit0
284
285#define AO_UI_Load_A_Register 40
286#define AO_UI_Load_A_Register_High 40
287#define AO_UI_Load_A_Register_Low 41
288#define AO_UI_Load_B_Register 42
289#define AO_UI_Save_Registers 16
290#define AO_BC_Load_A_Register 44
291#define AO_BC_Load_A_Register_High 44
292#define AO_BC_Load_A_Register_Low 45
293#define AO_BC_Load_B_Register 46
294#define AO_BC_Load_B_Register_High 46
295#define AO_BC_Load_B_Register_Low 47
296#define AO_BC_Save_Registers 18
297#define AO_UC_Load_A_Register 48
298#define AO_UC_Load_A_Register_High 48
299#define AO_UC_Load_A_Register_Low 49
300#define AO_UC_Load_B_Register 50
301#define AO_UC_Save_Registers 20
302
303#define Clock_and_FOUT_Register 56
304enum Clock_and_FOUT_bits {
305 FOUT_Enable = _bit15,
306 FOUT_Timebase_Select = _bit14,
307 DIO_Serial_Out_Divide_By_2 = _bit13,
308 Slow_Internal_Time_Divide_By_2 = _bit12,
309 Slow_Internal_Timebase = _bit11,
310 G_Source_Divide_By_2 = _bit10,
311 Clock_To_Board_Divide_By_2 = _bit9,
312 Clock_To_Board = _bit8,
313 AI_Output_Divide_By_2 = _bit7,
314 AI_Source_Divide_By_2 = _bit6,
315 AO_Output_Divide_By_2 = _bit5,
316 AO_Source_Divide_By_2 = _bit4,
317 FOUT_Divider_mask = 0xf
318};
319static inline unsigned FOUT_Divider(unsigned divider)
320{
321 return divider & FOUT_Divider_mask;
322}
323
324#define IO_Bidirection_Pin_Register 57
325#define RTSI_Trig_Direction_Register 58
326enum RTSI_Trig_Direction_Bits {
327 Drive_RTSI_Clock_Bit = 0x1,
328 Use_RTSI_Clock_Bit = 0x2,
329};
330static inline unsigned RTSI_Output_Bit(unsigned channel, int is_mseries)
331{
332 unsigned max_channel;
333 unsigned base_bit_shift;
334 if (is_mseries) {
335 base_bit_shift = 8;
336 max_channel = 7;
337 } else {
338 base_bit_shift = 9;
339 max_channel = 6;
340 }
341 if (channel > max_channel) {
342 printk("%s: bug, invalid RTSI_channel=%i\n", __func__, channel);
343 return 0;
344 }
345 return 1 << (base_bit_shift + channel);
346}
347
348#define Interrupt_Control_Register 59
349#define Interrupt_B_Enable _bit15
350#define Interrupt_B_Output_Select(x) ((x)<<12)
351#define Interrupt_A_Enable _bit11
352#define Interrupt_A_Output_Select(x) ((x)<<8)
353#define Pass_Thru_0_Interrupt_Polarity _bit3
354#define Pass_Thru_1_Interrupt_Polarity _bit2
355#define Interrupt_Output_On_3_Pins _bit1
356#define Interrupt_Output_Polarity _bit0
357
358#define AI_Output_Control_Register 60
359#define AI_START_Output_Select _bit10
360#define AI_SCAN_IN_PROG_Output_Select(x) (((x) & 0x3) << 8)
361#define AI_EXTMUX_CLK_Output_Select(x) (((x) & 0x3) << 6)
362#define AI_LOCALMUX_CLK_Output_Select(x) ((x)<<4)
363#define AI_SC_TC_Output_Select(x) ((x)<<2)
364enum ai_convert_output_selection {
365 AI_CONVERT_Output_High_Z = 0,
366 AI_CONVERT_Output_Ground = 1,
367 AI_CONVERT_Output_Enable_Low = 2,
368 AI_CONVERT_Output_Enable_High = 3
369};
370static unsigned AI_CONVERT_Output_Select(enum ai_convert_output_selection
371 selection)
372{
373 return selection & 0x3;
374}
375
376#define AI_START_STOP_Select_Register 62
377#define AI_START_Polarity _bit15
378#define AI_STOP_Polarity _bit14
379#define AI_STOP_Sync _bit13
380#define AI_STOP_Edge _bit12
381#define AI_STOP_Select(a) (((a) & 0x1f)<<7)
382#define AI_START_Sync _bit6
383#define AI_START_Edge _bit5
384#define AI_START_Select(a) ((a) & 0x1f)
385
386#define AI_Trigger_Select_Register 63
387#define AI_START1_Polarity _bit15
388#define AI_START2_Polarity _bit14
389#define AI_START2_Sync _bit13
390#define AI_START2_Edge _bit12
391#define AI_START2_Select(a) (((a) & 0x1f) << 7)
392#define AI_START1_Sync _bit6
393#define AI_START1_Edge _bit5
394#define AI_START1_Select(a) ((a) & 0x1f)
395
396#define AI_DIV_Load_A_Register 64
397
398#define AO_Start_Select_Register 66
399#define AO_UI2_Software_Gate _bit15
400#define AO_UI2_External_Gate_Polarity _bit14
401#define AO_START_Polarity _bit13
402#define AO_AOFREQ_Enable _bit12
403#define AO_UI2_External_Gate_Select(a) (((a) & 0x1f) << 7)
404#define AO_START_Sync _bit6
405#define AO_START_Edge _bit5
406#define AO_START_Select(a) ((a) & 0x1f)
407
408#define AO_Trigger_Select_Register 67
409#define AO_UI2_External_Gate_Enable _bit15
410#define AO_Delayed_START1 _bit14
411#define AO_START1_Polarity _bit13
412#define AO_UI2_Source_Polarity _bit12
413#define AO_UI2_Source_Select(x) (((x)&0x1f)<<7)
414#define AO_START1_Sync _bit6
415#define AO_START1_Edge _bit5
416#define AO_START1_Select(x) (((x)&0x1f)<<0)
417
418#define AO_Mode_3_Register 70
419#define AO_UI2_Switch_Load_Next_TC _bit13
420#define AO_UC_Switch_Load_Every_BC_TC _bit12
421#define AO_Trigger_Length _bit11
422#define AO_Stop_On_Overrun_Error _bit5
423#define AO_Stop_On_BC_TC_Trigger_Error _bit4
424#define AO_Stop_On_BC_TC_Error _bit3
425#define AO_Not_An_UPDATE _bit2
426#define AO_Software_Gate _bit1
427#define AO_Last_Gate_Disable _bit0
428
429#define Joint_Reset_Register 72
430#define Software_Reset _bit11
431#define AO_Configuration_End _bit9
432#define AI_Configuration_End _bit8
433#define AO_Configuration_Start _bit5
434#define AI_Configuration_Start _bit4
435#define G1_Reset _bit3
436#define G0_Reset _bit2
437#define AO_Reset _bit1
438#define AI_Reset _bit0
439
440#define Interrupt_A_Enable_Register 73
441#define Pass_Thru_0_Interrupt_Enable _bit9
442#define G0_Gate_Interrupt_Enable _bit8
443#define AI_FIFO_Interrupt_Enable _bit7
444#define G0_TC_Interrupt_Enable _bit6
445#define AI_Error_Interrupt_Enable _bit5
446#define AI_STOP_Interrupt_Enable _bit4
447#define AI_START_Interrupt_Enable _bit3
448#define AI_START2_Interrupt_Enable _bit2
449#define AI_START1_Interrupt_Enable _bit1
450#define AI_SC_TC_Interrupt_Enable _bit0
451
452#define Interrupt_B_Enable_Register 75
453#define Pass_Thru_1_Interrupt_Enable _bit11
454#define G1_Gate_Interrupt_Enable _bit10
455#define G1_TC_Interrupt_Enable _bit9
456#define AO_FIFO_Interrupt_Enable _bit8
457#define AO_UI2_TC_Interrupt_Enable _bit7
458#define AO_UC_TC_Interrupt_Enable _bit6
459#define AO_Error_Interrupt_Enable _bit5
460#define AO_STOP_Interrupt_Enable _bit4
461#define AO_START_Interrupt_Enable _bit3
462#define AO_UPDATE_Interrupt_Enable _bit2
463#define AO_START1_Interrupt_Enable _bit1
464#define AO_BC_TC_Interrupt_Enable _bit0
465
466#define Second_IRQ_A_Enable_Register 74
467enum Second_IRQ_A_Enable_Bits {
468 AI_SC_TC_Second_Irq_Enable = _bit0,
469 AI_START1_Second_Irq_Enable = _bit1,
470 AI_START2_Second_Irq_Enable = _bit2,
471 AI_START_Second_Irq_Enable = _bit3,
472 AI_STOP_Second_Irq_Enable = _bit4,
473 AI_Error_Second_Irq_Enable = _bit5,
474 G0_TC_Second_Irq_Enable = _bit6,
475 AI_FIFO_Second_Irq_Enable = _bit7,
476 G0_Gate_Second_Irq_Enable = _bit8,
477 Pass_Thru_0_Second_Irq_Enable = _bit9
478};
479
480#define Second_IRQ_B_Enable_Register 76
481enum Second_IRQ_B_Enable_Bits {
482 AO_BC_TC_Second_Irq_Enable = _bit0,
483 AO_START1_Second_Irq_Enable = _bit1,
484 AO_UPDATE_Second_Irq_Enable = _bit2,
485 AO_START_Second_Irq_Enable = _bit3,
486 AO_STOP_Second_Irq_Enable = _bit4,
487 AO_Error_Second_Irq_Enable = _bit5,
488 AO_UC_TC_Second_Irq_Enable = _bit6,
489 AO_UI2_TC_Second_Irq_Enable = _bit7,
490 AO_FIFO_Second_Irq_Enable = _bit8,
491 G1_TC_Second_Irq_Enable = _bit9,
492 G1_Gate_Second_Irq_Enable = _bit10,
493 Pass_Thru_1_Second_Irq_Enable = _bit11
494};
495
496#define AI_Personal_Register 77
497#define AI_SHIFTIN_Pulse_Width _bit15
498#define AI_EOC_Polarity _bit14
499#define AI_SOC_Polarity _bit13
500#define AI_SHIFTIN_Polarity _bit12
501#define AI_CONVERT_Pulse_Timebase _bit11
502#define AI_CONVERT_Pulse_Width _bit10
503#define AI_CONVERT_Original_Pulse _bit9
504#define AI_FIFO_Flags_Polarity _bit8
505#define AI_Overrun_Mode _bit7
506#define AI_EXTMUX_CLK_Pulse_Width _bit6
507#define AI_LOCALMUX_CLK_Pulse_Width _bit5
508#define AI_AIFREQ_Polarity _bit4
509
510#define AO_Personal_Register 78
511enum AO_Personal_Bits {
512 AO_Interval_Buffer_Mode = 1 << 3,
513 AO_BC_Source_Select = 1 << 4,
514 AO_UPDATE_Pulse_Width = 1 << 5,
515 AO_UPDATE_Pulse_Timebase = 1 << 6,
516 AO_UPDATE_Original_Pulse = 1 << 7,
517 AO_DMA_PIO_Control = 1 << 8,
518 AO_AOFREQ_Polarity = 1 << 9,
519 AO_FIFO_Enable = 1 << 10,
520 AO_FIFO_Flags_Polarity = 1 << 11,
521 AO_TMRDACWR_Pulse_Width = 1 << 12,
522 AO_Fast_CPU = 1 << 13,
523 AO_Number_Of_DAC_Packages = 1 << 14,
524 AO_Multiple_DACS_Per_Package = 1 << 15
525};
526#define RTSI_Trig_A_Output_Register 79
527#define RTSI_Trig_B_Output_Register 80
528enum RTSI_Trig_B_Output_Bits {
529 RTSI_Sub_Selection_1_Bit = 0x8000
530};
531static inline unsigned RTSI_Trig_Output_Bits(unsigned rtsi_channel,
532 unsigned source)
533{
534 return (source & 0xf) << ((rtsi_channel % 4) * 4);
535};
536
537static inline unsigned RTSI_Trig_Output_Mask(unsigned rtsi_channel)
538{
539 return 0xf << ((rtsi_channel % 4) * 4);
540};
541
542
543static inline unsigned RTSI_Trig_Output_Source(unsigned rtsi_channel,
544 unsigned bits)
545{
546 return (bits >> ((rtsi_channel % 4) * 4)) & 0xf;
547};
548
549#define RTSI_Board_Register 81
550#define Write_Strobe_0_Register 82
551#define Write_Strobe_1_Register 83
552#define Write_Strobe_2_Register 84
553#define Write_Strobe_3_Register 85
554
555#define AO_Output_Control_Register 86
556#define AO_External_Gate_Enable _bit15
557#define AO_External_Gate_Select(x) (((x)&0x1f)<<10)
558#define AO_Number_Of_Channels(x) (((x)&0xf)<<6)
559#define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4)
560#define AO_External_Gate_Polarity _bit3
561#define AO_UPDATE2_Output_Toggle _bit2
562enum ao_update_output_selection {
563 AO_Update_Output_High_Z = 0,
564 AO_Update_Output_Ground = 1,
565 AO_Update_Output_Enable_Low = 2,
566 AO_Update_Output_Enable_High = 3
567};
568static unsigned AO_UPDATE_Output_Select(enum ao_update_output_selection
569 selection)
570{
571 return selection & 0x3;
572}
573
574#define AI_Mode_3_Register 87
575#define AI_Trigger_Length _bit15
576#define AI_Delay_START _bit14
577#define AI_Software_Gate _bit13
578#define AI_SI_Special_Trigger_Delay _bit12
579#define AI_SI2_Source_Select _bit11
580#define AI_Delayed_START2 _bit10
581#define AI_Delayed_START1 _bit9
582#define AI_External_Gate_Mode _bit8
583#define AI_FIFO_Mode_HF_to_E (3<<6)
584#define AI_FIFO_Mode_F (2<<6)
585#define AI_FIFO_Mode_HF (1<<6)
586#define AI_FIFO_Mode_NE (0<<6)
587#define AI_External_Gate_Polarity _bit5
588#define AI_External_Gate_Select(a) ((a) & 0x1f)
589
590#define G_Autoincrement_Register(a) (68+(a))
591#define G_Command_Register(a) (6+(a))
592#define G_HW_Save_Register(a) (8+(a)*2)
593#define G_HW_Save_Register_High(a) (8+(a)*2)
594#define G_HW_Save_Register_Low(a) (9+(a)*2)
595#define G_Input_Select_Register(a) (36+(a))
596#define G_Load_A_Register(a) (28+(a)*4)
597#define G_Load_A_Register_High(a) (28+(a)*4)
598#define G_Load_A_Register_Low(a) (29+(a)*4)
599#define G_Load_B_Register(a) (30+(a)*4)
600#define G_Load_B_Register_High(a) (30+(a)*4)
601#define G_Load_B_Register_Low(a) (31+(a)*4)
602#define G_Mode_Register(a) (26+(a))
603#define G_Save_Register(a) (12+(a)*2)
604#define G_Save_Register_High(a) (12+(a)*2)
605#define G_Save_Register_Low(a) (13+(a)*2)
606#define G_Status_Register 4
607#define Analog_Trigger_Etc_Register 61
608
609
610#define G_Disarm_Copy _bit15
611#define G_Save_Trace_Copy _bit14
612#define G_Arm_Copy _bit13
613#define G_Bank_Switch_Start _bit10
614#define G_Little_Big_Endian _bit9
615#define G_Synchronized_Gate _bit8
616#define G_Write_Switch _bit7
617#define G_Up_Down(a) (((a)&0x03)<<5)
618#define G_Disarm _bit4
619#define G_Analog_Trigger_Reset _bit3
620#define G_Save_Trace _bit1
621#define G_Arm _bit0
622
623
624#define G_Bank_Switch_Enable _bit12
625#define G_Bank_Switch_Mode _bit11
626#define G_Load _bit2
627
628
629#define G_Gate_Select(a) (((a)&0x1f)<<7)
630#define G_Source_Select(a) (((a)&0x1f)<<2)
631#define G_Write_Acknowledges_Irq _bit1
632#define G_Read_Acknowledges_Irq _bit0
633
634
635#define G_Source_Polarity _bit15
636#define G_Output_Polarity _bit14
637#define G_OR_Gate _bit13
638#define G_Gate_Select_Load_Source _bit12
639
640
641#define G_Loading_On_TC _bit12
642#define G_Output_Mode(a) (((a)&0x03)<<8)
643#define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3)
644#define G_Gating_Mode(a) (((a)&0x03)<<0)
645
646
647#define G_Load_Source_Select _bit7
648#define G_Reload_Source_Switching _bit15
649#define G_Loading_On_Gate _bit14
650#define G_Gate_Polarity _bit13
651
652#define G_Counting_Once(a) (((a)&0x03)<<10)
653#define G_Stop_Mode(a) (((a)&0x03)<<5)
654#define G_Gate_On_Both_Edges _bit2
655
656
657#define G1_Gate_Error_St _bit15
658#define G0_Gate_Error_St _bit14
659#define G1_TC_Error_St _bit13
660#define G0_TC_Error_St _bit12
661#define G1_No_Load_Between_Gates_St _bit11
662#define G0_No_Load_Between_Gates_St _bit10
663#define G1_Armed_St _bit9
664#define G0_Armed_St _bit8
665#define G1_Stale_Data_St _bit7
666#define G0_Stale_Data_St _bit6
667#define G1_Next_Load_Source_St _bit5
668#define G0_Next_Load_Source_St _bit4
669#define G1_Counting_St _bit3
670#define G0_Counting_St _bit2
671#define G1_Save_St _bit1
672#define G0_Save_St _bit0
673
674
675#define G_Autoincrement(a) ((a)<<0)
676
677
678#define Analog_Trigger_Mode(x) ((x) & 0x7)
679#define Analog_Trigger_Enable _bit3
680#define Analog_Trigger_Drive _bit4
681#define GPFO_1_Output_Select _bit7
682#define GPFO_0_Output_Select(a) ((a)<<11)
683#define GPFO_0_Output_Enable _bit14
684#define GPFO_1_Output_Enable _bit15
685
686
687
688
689#define Window_Address 0x00
690#define Window_Data 0x02
691
692#define Configuration_Memory_Clear 82
693#define ADC_FIFO_Clear 83
694#define DAC_FIFO_Clear 84
695
696
697
698
699#define XXX_Status 0x01
700enum XXX_Status_Bits {
701 PROMOUT = 0x1,
702 AI_FIFO_LOWER_NOT_EMPTY = 0x8,
703};
704#define Serial_Command 0x0d
705#define Misc_Command 0x0f
706#define Port_A 0x19
707#define Port_B 0x1b
708#define Port_C 0x1d
709#define Configuration 0x1f
710#define Strobes 0x01
711#define Channel_A_Mode 0x03
712#define Channel_B_Mode 0x05
713#define Channel_C_Mode 0x07
714#define AI_AO_Select 0x09
715enum AI_AO_Select_Bits {
716 AI_DMA_Select_Shift = 0,
717 AI_DMA_Select_Mask = 0xf,
718 AO_DMA_Select_Shift = 4,
719 AO_DMA_Select_Mask = 0xf << AO_DMA_Select_Shift
720};
721#define G0_G1_Select 0x0b
722static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
723{
724 if (channel < 4)
725 return 1 << channel;
726 if (channel == 4)
727 return 0x3;
728 if (channel == 5)
729 return 0x5;
730 BUG();
731 return 0;
732}
733
734static inline unsigned GPCT_DMA_Select_Bits(unsigned gpct_index,
735 unsigned mite_channel)
736{
737 BUG_ON(gpct_index > 1);
738 return ni_stc_dma_channel_select_bitfield(mite_channel) << (4 *
739 gpct_index);
740}
741
742static inline unsigned GPCT_DMA_Select_Mask(unsigned gpct_index)
743{
744 BUG_ON(gpct_index > 1);
745 return 0xf << (4 * gpct_index);
746}
747
748
749
750#define Configuration_Memory_Low 0x10
751enum Configuration_Memory_Low_Bits {
752 AI_DITHER = 0x200,
753 AI_LAST_CHANNEL = 0x8000,
754};
755#define Configuration_Memory_High 0x12
756enum Configuration_Memory_High_Bits {
757 AI_AC_COUPLE = 0x800,
758 AI_DIFFERENTIAL = 0x1000,
759 AI_COMMON = 0x2000,
760 AI_GROUND = 0x3000,
761};
762static inline unsigned int AI_CONFIG_CHANNEL(unsigned int channel)
763{
764 return channel & 0x3f;
765}
766
767#define ADC_FIFO_Data_Register 0x1c
768
769#define AO_Configuration 0x16
770#define AO_Bipolar _bit0
771#define AO_Deglitch _bit1
772#define AO_Ext_Ref _bit2
773#define AO_Ground_Ref _bit3
774#define AO_Channel(x) ((x) << 8)
775
776#define DAC_FIFO_Data 0x1e
777#define DAC0_Direct_Data 0x18
778#define DAC1_Direct_Data 0x1a
779
780
781
782#define Magic_611x 0x19
783#define Calibration_Channel_Select_611x 0x1a
784#define ADC_FIFO_Data_611x 0x1c
785#define AI_FIFO_Offset_Load_611x 0x05
786#define DAC_FIFO_Data_611x 0x14
787#define Cal_Gain_Select_611x 0x05
788
789#define AO_Window_Address_611x 0x18
790#define AO_Window_Data_611x 0x1e
791
792
793#define Magic_6143 0x19
794#define G0G1_DMA_Select_6143 0x0B
795#define PipelineDelay_6143 0x1f
796#define EOC_Set_6143 0x1D
797#define AIDMA_Select_6143 0x09
798#define AIFIFO_Data_6143 0x8C
799#define AIFIFO_Flag_6143 0x84
800#define AIFIFO_Control_6143 0x88
801#define AIFIFO_Status_6143 0x88
802#define AIFIFO_DMAThreshold_6143 0x90
803#define AIFIFO_Words_Available_6143 0x94
804
805#define Calibration_Channel_6143 0x42
806#define Calibration_LowTime_6143 0x20
807#define Calibration_HighTime_6143 0x22
808#define Relay_Counter_Load_Val__6143 0x4C
809#define Signature_6143 0x50
810#define Release_Date_6143 0x54
811#define Release_Oldest_Date_6143 0x58
812
813#define Calibration_Channel_6143_RelayOn 0x8000
814#define Calibration_Channel_6143_RelayOff 0x4000
815#define Calibration_Channel_Gnd_Gnd 0x00
816#define Calibration_Channel_2v5_Gnd 0x02
817#define Calibration_Channel_Pwm_Gnd 0x05
818#define Calibration_Channel_2v5_Pwm 0x0a
819#define Calibration_Channel_Pwm_Pwm 0x0d
820#define Calibration_Channel_Gnd_Pwm 0x0e
821
822
823
824
825enum windowed_regs_67xx_61xx {
826 AO_Immediate_671x = 0x11,
827 AO_Timed_611x = 0x10,
828 AO_FIFO_Offset_Load_611x = 0x13,
829 AO_Later_Single_Point_Updates = 0x14,
830 AO_Waveform_Generation_611x = 0x15,
831 AO_Misc_611x = 0x16,
832 AO_Calibration_Channel_Select_67xx = 0x17,
833 AO_Configuration_2_67xx = 0x18,
834 CAL_ADC_Command_67xx = 0x19,
835 CAL_ADC_Status_67xx = 0x1a,
836 CAL_ADC_Data_67xx = 0x1b,
837 CAL_ADC_Config_Data_High_Word_67xx = 0x1c,
838 CAL_ADC_Config_Data_Low_Word_67xx = 0x1d,
839};
840static inline unsigned int DACx_Direct_Data_671x(int channel)
841{
842 return channel;
843}
844
845enum AO_Misc_611x_Bits {
846 CLEAR_WG = 1,
847};
848enum cs5529_configuration_bits {
849 CSCFG_CAL_CONTROL_MASK = 0x7,
850 CSCFG_SELF_CAL_OFFSET = 0x1,
851 CSCFG_SELF_CAL_GAIN = 0x2,
852 CSCFG_SELF_CAL_OFFSET_GAIN = 0x3,
853 CSCFG_SYSTEM_CAL_OFFSET = 0x5,
854 CSCFG_SYSTEM_CAL_GAIN = 0x6,
855 CSCFG_DONE = 1 << 3,
856 CSCFG_POWER_SAVE_SELECT = 1 << 4,
857 CSCFG_PORT_MODE = 1 << 5,
858 CSCFG_RESET_VALID = 1 << 6,
859 CSCFG_RESET = 1 << 7,
860 CSCFG_UNIPOLAR = 1 << 12,
861 CSCFG_WORD_RATE_2180_CYCLES = 0x0 << 13,
862 CSCFG_WORD_RATE_1092_CYCLES = 0x1 << 13,
863 CSCFG_WORD_RATE_532_CYCLES = 0x2 << 13,
864 CSCFG_WORD_RATE_388_CYCLES = 0x3 << 13,
865 CSCFG_WORD_RATE_324_CYCLES = 0x4 << 13,
866 CSCFG_WORD_RATE_17444_CYCLES = 0x5 << 13,
867 CSCFG_WORD_RATE_8724_CYCLES = 0x6 << 13,
868 CSCFG_WORD_RATE_4364_CYCLES = 0x7 << 13,
869 CSCFG_WORD_RATE_MASK = 0x7 << 13,
870 CSCFG_LOW_POWER = 1 << 16,
871};
872static inline unsigned int CS5529_CONFIG_DOUT(int output)
873{
874 return 1 << (18 + output);
875}
876
877static inline unsigned int CS5529_CONFIG_AOUT(int output)
878{
879 return 1 << (22 + output);
880}
881
882enum cs5529_command_bits {
883 CSCMD_POWER_SAVE = 0x1,
884 CSCMD_REGISTER_SELECT_MASK = 0xe,
885 CSCMD_OFFSET_REGISTER = 0x0,
886 CSCMD_GAIN_REGISTER = 0x2,
887 CSCMD_CONFIG_REGISTER = 0x4,
888 CSCMD_READ = 0x10,
889 CSCMD_CONTINUOUS_CONVERSIONS = 0x20,
890 CSCMD_SINGLE_CONVERSION = 0x40,
891 CSCMD_COMMAND = 0x80,
892};
893enum cs5529_status_bits {
894 CSS_ADC_BUSY = 0x1,
895 CSS_OSC_DETECT = 0x2,
896 CSS_OVERRANGE = 0x4,
897};
898#define SerDacLd(x) (0x08<<(x))
899
900
901
902
903
904
905enum { ai_gain_16 =
906 0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x, ai_gain_622x,
907 ai_gain_628x, ai_gain_6143
908};
909enum caldac_enum { caldac_none = 0, mb88341, dac8800, dac8043, ad8522,
910 ad8804, ad8842, ad8804_debug
911};
912enum ni_reg_type {
913 ni_reg_normal = 0x0,
914 ni_reg_611x = 0x1,
915 ni_reg_6711 = 0x2,
916 ni_reg_6713 = 0x4,
917 ni_reg_67xx_mask = 0x6,
918 ni_reg_6xxx_mask = 0x7,
919 ni_reg_622x = 0x8,
920 ni_reg_625x = 0x10,
921 ni_reg_628x = 0x18,
922 ni_reg_m_series_mask = 0x18,
923 ni_reg_6143 = 0x20
924};
925
926static const struct comedi_lrange range_ni_E_ao_ext;
927
928enum m_series_register_offsets {
929 M_Offset_CDIO_DMA_Select = 0x7,
930 M_Offset_SCXI_Status = 0x7,
931 M_Offset_AI_AO_Select = 0x9,
932 M_Offset_SCXI_Serial_Data_In = 0x9,
933 M_Offset_G0_G1_Select = 0xb,
934 M_Offset_Misc_Command = 0xf,
935 M_Offset_SCXI_Serial_Data_Out = 0x11,
936 M_Offset_SCXI_Control = 0x13,
937 M_Offset_SCXI_Output_Enable = 0x15,
938 M_Offset_AI_FIFO_Data = 0x1c,
939 M_Offset_Static_Digital_Output = 0x24,
940 M_Offset_Static_Digital_Input = 0x24,
941 M_Offset_DIO_Direction = 0x28,
942 M_Offset_Cal_PWM = 0x40,
943 M_Offset_AI_Config_FIFO_Data = 0x5e,
944 M_Offset_Interrupt_C_Enable = 0x88,
945 M_Offset_Interrupt_C_Status = 0x88,
946 M_Offset_Analog_Trigger_Control = 0x8c,
947 M_Offset_AO_Serial_Interrupt_Enable = 0xa0,
948 M_Offset_AO_Serial_Interrupt_Ack = 0xa1,
949 M_Offset_AO_Serial_Interrupt_Status = 0xa1,
950 M_Offset_AO_Calibration = 0xa3,
951 M_Offset_AO_FIFO_Data = 0xa4,
952 M_Offset_PFI_Filter = 0xb0,
953 M_Offset_RTSI_Filter = 0xb4,
954 M_Offset_SCXI_Legacy_Compatibility = 0xbc,
955 M_Offset_Interrupt_A_Ack = 0x104,
956 M_Offset_AI_Status_1 = 0x104,
957 M_Offset_Interrupt_B_Ack = 0x106,
958 M_Offset_AO_Status_1 = 0x106,
959 M_Offset_AI_Command_2 = 0x108,
960 M_Offset_G01_Status = 0x108,
961 M_Offset_AO_Command_2 = 0x10a,
962 M_Offset_AO_Status_2 = 0x10c,
963 M_Offset_G0_Command = 0x10c,
964 M_Offset_G1_Command = 0x10e,
965 M_Offset_G0_HW_Save = 0x110,
966 M_Offset_G0_HW_Save_High = 0x110,
967 M_Offset_AI_Command_1 = 0x110,
968 M_Offset_G0_HW_Save_Low = 0x112,
969 M_Offset_AO_Command_1 = 0x112,
970 M_Offset_G1_HW_Save = 0x114,
971 M_Offset_G1_HW_Save_High = 0x114,
972 M_Offset_G1_HW_Save_Low = 0x116,
973 M_Offset_AI_Mode_1 = 0x118,
974 M_Offset_G0_Save = 0x118,
975 M_Offset_G0_Save_High = 0x118,
976 M_Offset_AI_Mode_2 = 0x11a,
977 M_Offset_G0_Save_Low = 0x11a,
978 M_Offset_AI_SI_Load_A = 0x11c,
979 M_Offset_G1_Save = 0x11c,
980 M_Offset_G1_Save_High = 0x11c,
981 M_Offset_G1_Save_Low = 0x11e,
982 M_Offset_AI_SI_Load_B = 0x120,
983 M_Offset_AO_UI_Save = 0x120,
984 M_Offset_AI_SC_Load_A = 0x124,
985 M_Offset_AO_BC_Save = 0x124,
986 M_Offset_AI_SC_Load_B = 0x128,
987 M_Offset_AO_UC_Save = 0x128,
988 M_Offset_AI_SI2_Load_A = 0x12c,
989 M_Offset_AI_SI2_Load_B = 0x130,
990 M_Offset_G0_Mode = 0x134,
991 M_Offset_G1_Mode = 0x136,
992 M_Offset_Joint_Status_1 = 0x136,
993 M_Offset_G0_Load_A = 0x138,
994 M_Offset_Joint_Status_2 = 0x13a,
995 M_Offset_G0_Load_B = 0x13c,
996 M_Offset_G1_Load_A = 0x140,
997 M_Offset_G1_Load_B = 0x144,
998 M_Offset_G0_Input_Select = 0x148,
999 M_Offset_G1_Input_Select = 0x14a,
1000 M_Offset_AO_Mode_1 = 0x14c,
1001 M_Offset_AO_Mode_2 = 0x14e,
1002 M_Offset_AO_UI_Load_A = 0x150,
1003 M_Offset_AO_UI_Load_B = 0x154,
1004 M_Offset_AO_BC_Load_A = 0x158,
1005 M_Offset_AO_BC_Load_B = 0x15c,
1006 M_Offset_AO_UC_Load_A = 0x160,
1007 M_Offset_AO_UC_Load_B = 0x164,
1008 M_Offset_Clock_and_FOUT = 0x170,
1009 M_Offset_IO_Bidirection_Pin = 0x172,
1010 M_Offset_RTSI_Trig_Direction = 0x174,
1011 M_Offset_Interrupt_Control = 0x176,
1012 M_Offset_AI_Output_Control = 0x178,
1013 M_Offset_Analog_Trigger_Etc = 0x17a,
1014 M_Offset_AI_START_STOP_Select = 0x17c,
1015 M_Offset_AI_Trigger_Select = 0x17e,
1016 M_Offset_AI_SI_Save = 0x180,
1017 M_Offset_AI_DIV_Load_A = 0x180,
1018 M_Offset_AI_SC_Save = 0x184,
1019 M_Offset_AO_Start_Select = 0x184,
1020 M_Offset_AO_Trigger_Select = 0x186,
1021 M_Offset_AO_Mode_3 = 0x18c,
1022 M_Offset_G0_Autoincrement = 0x188,
1023 M_Offset_G1_Autoincrement = 0x18a,
1024 M_Offset_Joint_Reset = 0x190,
1025 M_Offset_Interrupt_A_Enable = 0x192,
1026 M_Offset_Interrupt_B_Enable = 0x196,
1027 M_Offset_AI_Personal = 0x19a,
1028 M_Offset_AO_Personal = 0x19c,
1029 M_Offset_RTSI_Trig_A_Output = 0x19e,
1030 M_Offset_RTSI_Trig_B_Output = 0x1a0,
1031 M_Offset_RTSI_Shared_MUX = 0x1a2,
1032 M_Offset_AO_Output_Control = 0x1ac,
1033 M_Offset_AI_Mode_3 = 0x1ae,
1034 M_Offset_Configuration_Memory_Clear = 0x1a4,
1035 M_Offset_AI_FIFO_Clear = 0x1a6,
1036 M_Offset_AO_FIFO_Clear = 0x1a8,
1037 M_Offset_G0_Counting_Mode = 0x1b0,
1038 M_Offset_G1_Counting_Mode = 0x1b2,
1039 M_Offset_G0_Second_Gate = 0x1b4,
1040 M_Offset_G1_Second_Gate = 0x1b6,
1041 M_Offset_G0_DMA_Config = 0x1b8,
1042 M_Offset_G0_DMA_Status = 0x1b8,
1043 M_Offset_G1_DMA_Config = 0x1ba,
1044 M_Offset_G1_DMA_Status = 0x1ba,
1045 M_Offset_G0_MSeries_ABZ = 0x1c0,
1046 M_Offset_G1_MSeries_ABZ = 0x1c2,
1047 M_Offset_Clock_and_Fout2 = 0x1c4,
1048 M_Offset_PLL_Control = 0x1c6,
1049 M_Offset_PLL_Status = 0x1c8,
1050 M_Offset_PFI_Output_Select_1 = 0x1d0,
1051 M_Offset_PFI_Output_Select_2 = 0x1d2,
1052 M_Offset_PFI_Output_Select_3 = 0x1d4,
1053 M_Offset_PFI_Output_Select_4 = 0x1d6,
1054 M_Offset_PFI_Output_Select_5 = 0x1d8,
1055 M_Offset_PFI_Output_Select_6 = 0x1da,
1056 M_Offset_PFI_DI = 0x1dc,
1057 M_Offset_PFI_DO = 0x1de,
1058 M_Offset_AI_Config_FIFO_Bypass = 0x218,
1059 M_Offset_SCXI_DIO_Enable = 0x21c,
1060 M_Offset_CDI_FIFO_Data = 0x220,
1061 M_Offset_CDO_FIFO_Data = 0x220,
1062 M_Offset_CDIO_Status = 0x224,
1063 M_Offset_CDIO_Command = 0x224,
1064 M_Offset_CDI_Mode = 0x228,
1065 M_Offset_CDO_Mode = 0x22c,
1066 M_Offset_CDI_Mask_Enable = 0x230,
1067 M_Offset_CDO_Mask_Enable = 0x234,
1068};
1069static inline int M_Offset_AO_Waveform_Order(int channel)
1070{
1071 return 0xc2 + 0x4 * channel;
1072};
1073
1074static inline int M_Offset_AO_Config_Bank(int channel)
1075{
1076 return 0xc3 + 0x4 * channel;
1077};
1078
1079static inline int M_Offset_DAC_Direct_Data(int channel)
1080{
1081 return 0xc0 + 0x4 * channel;
1082}
1083
1084static inline int M_Offset_Gen_PWM(int channel)
1085{
1086 return 0x44 + 0x2 * channel;
1087}
1088
1089static inline int M_Offset_Static_AI_Control(int i)
1090{
1091 int offset[] = {
1092 0x64,
1093 0x261,
1094 0x262,
1095 0x263,
1096 };
1097 if (((unsigned)i) >= ARRAY_SIZE(offset)) {
1098 printk("%s: invalid channel=%i\n", __func__, i);
1099 return offset[0];
1100 }
1101 return offset[i];
1102};
1103
1104static inline int M_Offset_AO_Reference_Attenuation(int channel)
1105{
1106 int offset[] = {
1107 0x264,
1108 0x265,
1109 0x266,
1110 0x267
1111 };
1112 if (((unsigned)channel) >= ARRAY_SIZE(offset)) {
1113 printk("%s: invalid channel=%i\n", __func__, channel);
1114 return offset[0];
1115 }
1116 return offset[channel];
1117};
1118
1119static inline unsigned M_Offset_PFI_Output_Select(unsigned n)
1120{
1121 if (n < 1 || n > NUM_PFI_OUTPUT_SELECT_REGS) {
1122 printk("%s: invalid pfi output select register=%i\n",
1123 __func__, n);
1124 return M_Offset_PFI_Output_Select_1;
1125 }
1126 return M_Offset_PFI_Output_Select_1 + (n - 1) * 2;
1127}
1128
1129enum MSeries_AI_Config_FIFO_Data_Bits {
1130 MSeries_AI_Config_Channel_Type_Mask = 0x7 << 6,
1131 MSeries_AI_Config_Channel_Type_Calibration_Bits = 0x0,
1132 MSeries_AI_Config_Channel_Type_Differential_Bits = 0x1 << 6,
1133 MSeries_AI_Config_Channel_Type_Common_Ref_Bits = 0x2 << 6,
1134 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits = 0x3 << 6,
1135 MSeries_AI_Config_Channel_Type_Aux_Bits = 0x5 << 6,
1136 MSeries_AI_Config_Channel_Type_Ghost_Bits = 0x7 << 6,
1137 MSeries_AI_Config_Polarity_Bit = 0x1000,
1138 MSeries_AI_Config_Dither_Bit = 0x2000,
1139 MSeries_AI_Config_Last_Channel_Bit = 0x4000,
1140};
1141static inline unsigned MSeries_AI_Config_Channel_Bits(unsigned channel)
1142{
1143 return channel & 0xf;
1144}
1145
1146static inline unsigned MSeries_AI_Config_Bank_Bits(enum ni_reg_type reg_type,
1147 unsigned channel)
1148{
1149 unsigned bits = channel & 0x30;
1150 if (reg_type == ni_reg_622x) {
1151 if (channel & 0x40)
1152 bits |= 0x400;
1153 }
1154 return bits;
1155}
1156
1157static inline unsigned MSeries_AI_Config_Gain_Bits(unsigned range)
1158{
1159 return (range & 0x7) << 9;
1160}
1161
1162enum MSeries_Clock_and_Fout2_Bits {
1163 MSeries_PLL_In_Source_Select_RTSI0_Bits = 0xb,
1164 MSeries_PLL_In_Source_Select_Star_Trigger_Bits = 0x14,
1165 MSeries_PLL_In_Source_Select_RTSI7_Bits = 0x1b,
1166 MSeries_PLL_In_Source_Select_PXI_Clock10 = 0x1d,
1167 MSeries_PLL_In_Source_Select_Mask = 0x1f,
1168 MSeries_Timebase1_Select_Bit = 0x20,
1169 MSeries_Timebase3_Select_Bit = 0x40,
1170
1171
1172
1173 MSeries_RTSI_10MHz_Bit = 0x80
1174};
1175static inline unsigned MSeries_PLL_In_Source_Select_RTSI_Bits(unsigned
1176 RTSI_channel)
1177{
1178 if (RTSI_channel > 7) {
1179 printk("%s: bug, invalid RTSI_channel=%i\n", __func__,
1180 RTSI_channel);
1181 return 0;
1182 }
1183 if (RTSI_channel == 7)
1184 return MSeries_PLL_In_Source_Select_RTSI7_Bits;
1185 else
1186 return MSeries_PLL_In_Source_Select_RTSI0_Bits + RTSI_channel;
1187}
1188
1189enum MSeries_PLL_Control_Bits {
1190 MSeries_PLL_Enable_Bit = 0x1000,
1191 MSeries_PLL_VCO_Mode_200_325MHz_Bits = 0x0,
1192 MSeries_PLL_VCO_Mode_175_225MHz_Bits = 0x2000,
1193 MSeries_PLL_VCO_Mode_100_225MHz_Bits = 0x4000,
1194 MSeries_PLL_VCO_Mode_75_150MHz_Bits = 0x6000,
1195};
1196static inline unsigned MSeries_PLL_Divisor_Bits(unsigned divisor)
1197{
1198 static const unsigned max_divisor = 0x10;
1199 if (divisor < 1 || divisor > max_divisor) {
1200 printk("%s: bug, invalid divisor=%i\n", __func__, divisor);
1201 return 0;
1202 }
1203 return (divisor & 0xf) << 8;
1204}
1205
1206static inline unsigned MSeries_PLL_Multiplier_Bits(unsigned multiplier)
1207{
1208 static const unsigned max_multiplier = 0x100;
1209 if (multiplier < 1 || multiplier > max_multiplier) {
1210 printk("%s: bug, invalid multiplier=%i\n", __func__,
1211 multiplier);
1212 return 0;
1213 }
1214 return multiplier & 0xff;
1215}
1216
1217enum MSeries_PLL_Status {
1218 MSeries_PLL_Locked_Bit = 0x1
1219};
1220
1221enum MSeries_AI_Config_FIFO_Bypass_Bits {
1222 MSeries_AI_Bypass_Channel_Mask = 0x7,
1223 MSeries_AI_Bypass_Bank_Mask = 0x78,
1224 MSeries_AI_Bypass_Cal_Sel_Pos_Mask = 0x380,
1225 MSeries_AI_Bypass_Cal_Sel_Neg_Mask = 0x1c00,
1226 MSeries_AI_Bypass_Mode_Mux_Mask = 0x6000,
1227 MSeries_AO_Bypass_AO_Cal_Sel_Mask = 0x38000,
1228 MSeries_AI_Bypass_Gain_Mask = 0x1c0000,
1229 MSeries_AI_Bypass_Dither_Bit = 0x200000,
1230 MSeries_AI_Bypass_Polarity_Bit = 0x400000,
1231 MSeries_AI_Bypass_Config_FIFO_Bit = 0x80000000
1232};
1233static inline unsigned MSeries_AI_Bypass_Cal_Sel_Pos_Bits(int
1234 calibration_source)
1235{
1236 return (calibration_source << 7) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask;
1237}
1238
1239static inline unsigned MSeries_AI_Bypass_Cal_Sel_Neg_Bits(int
1240 calibration_source)
1241{
1242 return (calibration_source << 10) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask;
1243}
1244
1245static inline unsigned MSeries_AI_Bypass_Gain_Bits(int gain)
1246{
1247 return (gain << 18) & MSeries_AI_Bypass_Gain_Mask;
1248}
1249
1250enum MSeries_AO_Config_Bank_Bits {
1251 MSeries_AO_DAC_Offset_Select_Mask = 0x7,
1252 MSeries_AO_DAC_Offset_0V_Bits = 0x0,
1253 MSeries_AO_DAC_Offset_5V_Bits = 0x1,
1254 MSeries_AO_DAC_Reference_Mask = 0x38,
1255 MSeries_AO_DAC_Reference_10V_Internal_Bits = 0x0,
1256 MSeries_AO_DAC_Reference_5V_Internal_Bits = 0x8,
1257 MSeries_AO_Update_Timed_Bit = 0x40,
1258 MSeries_AO_Bipolar_Bit = 0x80
1259};
1260
1261enum MSeries_AO_Reference_Attenuation_Bits {
1262 MSeries_Attenuate_x5_Bit = 0x1
1263};
1264
1265static inline unsigned MSeries_Cal_PWM_High_Time_Bits(unsigned count)
1266{
1267 return (count << 16) & 0xffff0000;
1268}
1269
1270static inline unsigned MSeries_Cal_PWM_Low_Time_Bits(unsigned count)
1271{
1272 return count & 0xffff;
1273}
1274
1275static inline unsigned MSeries_PFI_Output_Select_Mask(unsigned channel)
1276{
1277 return 0x1f << (channel % 3) * 5;
1278};
1279
1280static inline unsigned MSeries_PFI_Output_Select_Bits(unsigned channel,
1281 unsigned source)
1282{
1283 return (source & 0x1f) << ((channel % 3) * 5);
1284};
1285
1286
1287static inline unsigned MSeries_PFI_Output_Select_Source(unsigned channel,
1288 unsigned bits)
1289{
1290 return (bits >> ((channel % 3) * 5)) & 0x1f;
1291};
1292
1293enum MSeries_Gi_DMA_Config_Bits {
1294 Gi_DMA_BankSW_Error_Bit = 0x10,
1295 Gi_DMA_Reset_Bit = 0x8,
1296 Gi_DMA_Int_Enable_Bit = 0x4,
1297 Gi_DMA_Write_Bit = 0x2,
1298 Gi_DMA_Enable_Bit = 0x1,
1299};
1300
1301static inline unsigned MSeries_PFI_Filter_Select_Mask(unsigned channel)
1302{
1303 return 0x3 << (channel * 2);
1304}
1305
1306static inline unsigned MSeries_PFI_Filter_Select_Bits(unsigned channel,
1307 unsigned filter)
1308{
1309 return (filter << (channel *
1310 2)) & MSeries_PFI_Filter_Select_Mask(channel);
1311}
1312
1313enum CDIO_DMA_Select_Bits {
1314 CDI_DMA_Select_Shift = 0,
1315 CDI_DMA_Select_Mask = 0xf,
1316 CDO_DMA_Select_Shift = 4,
1317 CDO_DMA_Select_Mask = 0xf << CDO_DMA_Select_Shift
1318};
1319
1320enum CDIO_Status_Bits {
1321 CDO_FIFO_Empty_Bit = 0x1,
1322 CDO_FIFO_Full_Bit = 0x2,
1323 CDO_FIFO_Request_Bit = 0x4,
1324 CDO_Overrun_Bit = 0x8,
1325 CDO_Underflow_Bit = 0x10,
1326 CDI_FIFO_Empty_Bit = 0x10000,
1327 CDI_FIFO_Full_Bit = 0x20000,
1328 CDI_FIFO_Request_Bit = 0x40000,
1329 CDI_Overrun_Bit = 0x80000,
1330 CDI_Overflow_Bit = 0x100000
1331};
1332
1333enum CDIO_Command_Bits {
1334 CDO_Disarm_Bit = 0x1,
1335 CDO_Arm_Bit = 0x2,
1336 CDI_Disarm_Bit = 0x4,
1337 CDI_Arm_Bit = 0x8,
1338 CDO_Reset_Bit = 0x10,
1339 CDI_Reset_Bit = 0x20,
1340 CDO_Error_Interrupt_Enable_Set_Bit = 0x40,
1341 CDO_Error_Interrupt_Enable_Clear_Bit = 0x80,
1342 CDI_Error_Interrupt_Enable_Set_Bit = 0x100,
1343 CDI_Error_Interrupt_Enable_Clear_Bit = 0x200,
1344 CDO_FIFO_Request_Interrupt_Enable_Set_Bit = 0x400,
1345 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit = 0x800,
1346 CDI_FIFO_Request_Interrupt_Enable_Set_Bit = 0x1000,
1347 CDI_FIFO_Request_Interrupt_Enable_Clear_Bit = 0x2000,
1348 CDO_Error_Interrupt_Confirm_Bit = 0x4000,
1349 CDI_Error_Interrupt_Confirm_Bit = 0x8000,
1350 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit = 0x10000,
1351 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit = 0x20000,
1352 CDO_SW_Update_Bit = 0x80000,
1353 CDI_SW_Update_Bit = 0x100000
1354};
1355
1356enum CDI_Mode_Bits {
1357 CDI_Sample_Source_Select_Mask = 0x3f,
1358 CDI_Halt_On_Error_Bit = 0x200,
1359 CDI_Polarity_Bit = 0x400,
1360 CDI_FIFO_Mode_Bit = 0x800,
1361 CDI_Data_Lane_Mask = 0x3000,
1362 CDI_Data_Lane_0_15_Bits = 0x0,
1363 CDI_Data_Lane_16_31_Bits = 0x1000,
1364 CDI_Data_Lane_0_7_Bits = 0x0,
1365 CDI_Data_Lane_8_15_Bits = 0x1000,
1366 CDI_Data_Lane_16_23_Bits = 0x2000,
1367 CDI_Data_Lane_24_31_Bits = 0x3000
1368};
1369
1370enum CDO_Mode_Bits {
1371 CDO_Sample_Source_Select_Mask = 0x3f,
1372 CDO_Retransmit_Bit = 0x100,
1373 CDO_Halt_On_Error_Bit = 0x200,
1374 CDO_Polarity_Bit = 0x400,
1375 CDO_FIFO_Mode_Bit = 0x800,
1376 CDO_Data_Lane_Mask = 0x3000,
1377 CDO_Data_Lane_0_15_Bits = 0x0,
1378 CDO_Data_Lane_16_31_Bits = 0x1000,
1379 CDO_Data_Lane_0_7_Bits = 0x0,
1380 CDO_Data_Lane_8_15_Bits = 0x1000,
1381 CDO_Data_Lane_16_23_Bits = 0x2000,
1382 CDO_Data_Lane_24_31_Bits = 0x3000
1383};
1384
1385enum Interrupt_C_Enable_Bits {
1386 Interrupt_Group_C_Enable_Bit = 0x1
1387};
1388
1389enum Interrupt_C_Status_Bits {
1390 Interrupt_Group_C_Status_Bit = 0x1
1391};
1392
1393#define M_SERIES_EEPROM_SIZE 1024
1394
1395struct ni_board_struct {
1396 int device_id;
1397 int isapnp_id;
1398 char *name;
1399
1400 int n_adchan;
1401 int adbits;
1402
1403 int ai_fifo_depth;
1404 unsigned int alwaysdither:1;
1405 int gainlkup;
1406 int ai_speed;
1407
1408 int n_aochan;
1409 int aobits;
1410 int ao_fifo_depth;
1411 const struct comedi_lrange *ao_range_table;
1412 unsigned ao_speed;
1413
1414 unsigned num_p0_dio_channels;
1415
1416 int reg_type;
1417 unsigned int ao_unipolar:1;
1418 unsigned int has_8255:1;
1419 unsigned int has_analog_trig:1;
1420
1421 enum caldac_enum caldac[3];
1422};
1423
1424#define n_ni_boards (sizeof(ni_boards)/sizeof(struct ni_board_struct))
1425
1426#define boardtype (*(struct ni_board_struct *)dev->board_ptr)
1427
1428#define MAX_N_AO_CHAN 8
1429#define NUM_GPCT 2
1430
1431#define NI_PRIVATE_COMMON \
1432 uint16_t (*stc_readw)(struct comedi_device *dev, int register); \
1433 uint32_t (*stc_readl)(struct comedi_device *dev, int register); \
1434 void (*stc_writew)(struct comedi_device *dev, uint16_t value, int register); \
1435 void (*stc_writel)(struct comedi_device *dev, uint32_t value, int register); \
1436 \
1437 unsigned short dio_output; \
1438 unsigned short dio_control; \
1439 int ao0p, ao1p; \
1440 int lastchan; \
1441 int last_do; \
1442 int rt_irq; \
1443 int irqmask; \
1444 int aimode; \
1445 int ai_continuous; \
1446 int blocksize; \
1447 int n_left; \
1448 unsigned int ai_calib_source; \
1449 unsigned int ai_calib_source_enabled; \
1450 spinlock_t window_lock; \
1451 spinlock_t soft_reg_copy_lock; \
1452 spinlock_t mite_channel_lock; \
1453 \
1454 int changain_state; \
1455 unsigned int changain_spec; \
1456 \
1457 unsigned int caldac_maxdata_list[MAX_N_CALDACS]; \
1458 unsigned short ao[MAX_N_AO_CHAN]; \
1459 unsigned short caldacs[MAX_N_CALDACS]; \
1460 \
1461 unsigned short ai_cmd2; \
1462 \
1463 unsigned short ao_conf[MAX_N_AO_CHAN]; \
1464 unsigned short ao_mode1; \
1465 unsigned short ao_mode2; \
1466 unsigned short ao_mode3; \
1467 unsigned short ao_cmd1; \
1468 unsigned short ao_cmd2; \
1469 unsigned short ao_cmd3; \
1470 unsigned short ao_trigger_select; \
1471 \
1472 struct ni_gpct_device *counter_dev; \
1473 unsigned short an_trig_etc_reg; \
1474 \
1475 unsigned ai_offset[512]; \
1476 \
1477 unsigned long serial_interval_ns; \
1478 unsigned char serial_hw_mode; \
1479 unsigned short clock_and_fout; \
1480 unsigned short clock_and_fout2; \
1481 \
1482 unsigned short int_a_enable_reg; \
1483 unsigned short int_b_enable_reg; \
1484 unsigned short io_bidirection_pin_reg; \
1485 unsigned short rtsi_trig_direction_reg; \
1486 unsigned short rtsi_trig_a_output_reg; \
1487 unsigned short rtsi_trig_b_output_reg; \
1488 unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS]; \
1489 unsigned short ai_ao_select_reg; \
1490 unsigned short g0_g1_select_reg; \
1491 unsigned short cdio_dma_select_reg; \
1492 \
1493 unsigned clock_ns; \
1494 unsigned clock_source; \
1495 \
1496 unsigned short atrig_mode; \
1497 unsigned short atrig_high; \
1498 unsigned short atrig_low; \
1499 \
1500 unsigned short pwm_up_count; \
1501 unsigned short pwm_down_count; \
1502 \
1503 short ai_fifo_buffer[0x2000]; \
1504 uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE]; \
1505 uint32_t serial_number; \
1506 \
1507 struct mite_struct *mite; \
1508 struct mite_channel *ai_mite_chan; \
1509 struct mite_channel *ao_mite_chan;\
1510 struct mite_channel *cdo_mite_chan;\
1511 struct mite_dma_descriptor_ring *ai_mite_ring; \
1512 struct mite_dma_descriptor_ring *ao_mite_ring; \
1513 struct mite_dma_descriptor_ring *cdo_mite_ring; \
1514 struct mite_dma_descriptor_ring *gpct_mite_ring[NUM_GPCT];
1515
1516#endif
1517