1/* 2 comedi/drivers/s626.h 3 Sensoray s626 Comedi driver, header file 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 2000 David A. Schleef <ds@schleef.org> 7 8 Based on Sensoray Model 626 Linux driver Version 0.2 9 Copyright (C) 2002-2004 Sensoray Co., Inc. 10 11 This program is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 2 of the License, or 14 (at your option) any later version. 15 16 This program is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 GNU General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software 23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 25*/ 26 27/* 28 Driver: s626.o (s626.ko) 29 Description: Sensoray 626 driver 30 Devices: Sensoray s626 31 Authors: Gianluca Palli <gpalli@deis.unibo.it>, 32 Updated: Thu, 12 Jul 2005 33 Status: experimental 34 35 Configuration Options: 36 analog input: 37 none 38 39 analog output: 40 none 41 42 digital channel: 43 s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels 44 supported configuration options: 45 INSN_CONFIG_DIO_QUERY 46 COMEDI_INPUT 47 COMEDI_OUTPUT 48 49 encoder: 50 Every channel must be configured before reading. 51 52 Example code 53 54 insn.insn=INSN_CONFIG; // configuration instruction 55 insn.n=1; // number of operation (must be 1) 56 insn.data=&initialvalue; // initial value loaded into encoder 57 // during configuration 58 insn.subdev=5; // encoder subdevice 59 insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); // encoder_channel 60 // to configure 61 62 comedi_do_insn(cf,&insn); // executing configuration 63*/ 64 65#if !defined(TRUE) 66#define TRUE (1) 67#endif 68 69#if !defined(FALSE) 70#define FALSE (0) 71#endif 72 73#include <linux/slab.h> 74 75#define S626_SIZE 0x0200 76#define DMABUF_SIZE 4096 /* 4k pages */ 77 78#define S626_ADC_CHANNELS 16 79#define S626_DAC_CHANNELS 4 80#define S626_ENCODER_CHANNELS 6 81#define S626_DIO_CHANNELS 48 82#define S626_DIO_BANKS 3 /* Number of DIO groups. */ 83#define S626_DIO_EXTCHANS 40 /* Number of */ 84 /* extended-capability */ 85 /* DIO channels. */ 86 87#define NUM_TRIMDACS 12 /* Number of valid TrimDAC channels. */ 88 89/* PCI bus interface types. */ 90#define INTEL 1 /* Intel bus type. */ 91#define MOTOROLA 2 /* Motorola bus type. */ 92 93#define PLATFORM INTEL /* *** SELECT PLATFORM TYPE *** */ 94 95#define RANGE_5V 0x10 /* +/-5V range */ 96#define RANGE_10V 0x00 /* +/-10V range */ 97 98#define EOPL 0x80 /* End of ADC poll list marker. */ 99#define GSEL_BIPOLAR5V 0x00F0 /* LP_GSEL setting for 5V bipolar range. */ 100#define GSEL_BIPOLAR10V 0x00A0 /* LP_GSEL setting for 10V bipolar range. */ 101 102/* Error codes that must be visible to this base class. */ 103#define ERR_ILLEGAL_PARM 0x00010000 /* Illegal function parameter value was specified. */ 104#define ERR_I2C 0x00020000 /* I2C error. */ 105#define ERR_COUNTERSETUP 0x00200000 /* Illegal setup specified for counter channel. */ 106#define ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */ 107 108/* Organization (physical order) and size (in DWORDs) of logical DMA buffers contained by ANA_DMABUF. */ 109#define ADC_DMABUF_DWORDS 40 /* ADC DMA buffer must hold 16 samples, plus pre/post garbage samples. */ 110#define DAC_WDMABUF_DWORDS 1 /* DAC output DMA buffer holds a single sample. */ 111 112/* All remaining space in 4KB DMA buffer is available for the RPS1 program. */ 113 114/* Address offsets, in DWORDS, from base of DMA buffer. */ 115#define DAC_WDMABUF_OS ADC_DMABUF_DWORDS 116 117/* Interrupt enab bit in ISR and IER. */ 118#define IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */ 119#define IRQ_RPS1 0x10000000 120#define ISR_AFOU 0x00000800 121/* Audio fifo under/overflow detected. */ 122 123#define IRQ_COINT1A 0x0400 /* conter 1A overflow interrupt mask */ 124#define IRQ_COINT1B 0x0800 /* conter 1B overflow interrupt mask */ 125#define IRQ_COINT2A 0x1000 /* conter 2A overflow interrupt mask */ 126#define IRQ_COINT2B 0x2000 /* conter 2B overflow interrupt mask */ 127#define IRQ_COINT3A 0x4000 /* conter 3A overflow interrupt mask */ 128#define IRQ_COINT3B 0x8000 /* conter 3B overflow interrupt mask */ 129 130/* RPS command codes. */ 131#define RPS_CLRSIGNAL 0x00000000 /* CLEAR SIGNAL */ 132#define RPS_SETSIGNAL 0x10000000 /* SET SIGNAL */ 133#define RPS_NOP 0x00000000 /* NOP */ 134#define RPS_PAUSE 0x20000000 /* PAUSE */ 135#define RPS_UPLOAD 0x40000000 /* UPLOAD */ 136#define RPS_JUMP 0x80000000 /* JUMP */ 137#define RPS_LDREG 0x90000100 /* LDREG (1 uint32_t only) */ 138#define RPS_STREG 0xA0000100 /* STREG (1 uint32_t only) */ 139#define RPS_STOP 0x50000000 /* STOP */ 140#define RPS_IRQ 0x60000000 /* IRQ */ 141 142#define RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */ 143#define RPS_INVERT 0x04000000 /* Test for negated semaphores. */ 144#define RPS_DEBI 0x00000002 /* DEBI done */ 145 146#define RPS_SIG0 0x00200000 /* RPS semaphore 0 (used by ADC). */ 147#define RPS_SIG1 0x00400000 /* RPS semaphore 1 (used by DAC). */ 148#define RPS_SIG2 0x00800000 /* RPS semaphore 2 (not used). */ 149#define RPS_GPIO2 0x00080000 /* RPS GPIO2 */ 150#define RPS_GPIO3 0x00100000 /* RPS GPIO3 */ 151 152#define RPS_SIGADC RPS_SIG0 /* Trigger/status for ADC's RPS program. */ 153#define RPS_SIGDAC RPS_SIG1 /* Trigger/status for DAC's RPS program. */ 154 155/* RPS clock parameters. */ 156#define RPSCLK_SCALAR 8 /* This is apparent ratio of PCI/RPS clks (undocumented!!). */ 157#define RPSCLK_PER_US (33 / RPSCLK_SCALAR) /* Number of RPS clocks in one microsecond. */ 158 159/* Event counter source addresses. */ 160#define SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */ 161 162/* GPIO constants. */ 163#define GPIO_BASE 0x10004000 /* GPIO 0,2,3 = inputs, GPIO3 = IRQ; GPIO1 = out. */ 164#define GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */ 165#define GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */ 166 167/* Primary Status Register (PSR) constants. */ 168#define PSR_DEBI_E 0x00040000 /* DEBI event flag. */ 169#define PSR_DEBI_S 0x00080000 /* DEBI status flag. */ 170#define PSR_A2_IN 0x00008000 /* Audio output DMA2 protection address reached. */ 171#define PSR_AFOU 0x00000800 /* Audio FIFO under/overflow detected. */ 172#define PSR_GPIO2 0x00000020 /* GPIO2 input pin: 0=AdcBusy, 1=AdcIdle. */ 173#define PSR_EC0S 0x00000001 /* Event counter 0 threshold reached. */ 174 175/* Secondary Status Register (SSR) constants. */ 176#define SSR_AF2_OUT 0x00000200 /* Audio 2 output FIFO under/overflow detected. */ 177 178/* Master Control Register 1 (MC1) constants. */ 179#define MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */ 180#define MC1_SHUTDOWN 0x3FFF0000 /* Shut down all MC1-controlled enables. */ 181 182#define MC1_ERPS1 0x2000 /* enab/disable RPS task 1. */ 183#define MC1_ERPS0 0x1000 /* enab/disable RPS task 0. */ 184#define MC1_DEBI 0x0800 /* enab/disable DEBI pins. */ 185#define MC1_AUDIO 0x0200 /* enab/disable audio port pins. */ 186#define MC1_I2C 0x0100 /* enab/disable I2C interface. */ 187#define MC1_A2OUT 0x0008 /* enab/disable transfer on A2 out. */ 188#define MC1_A2IN 0x0004 /* enab/disable transfer on A2 in. */ 189#define MC1_A1IN 0x0001 /* enab/disable transfer on A1 in. */ 190 191/* Master Control Register 2 (MC2) constants. */ 192#define MC2_UPLD_DEBIq 0x00020002 /* Upload DEBI registers. */ 193#define MC2_UPLD_IICq 0x00010001 /* Upload I2C registers. */ 194#define MC2_RPSSIG2_ONq 0x20002000 /* Assert RPS_SIG2. */ 195#define MC2_RPSSIG1_ONq 0x10001000 /* Assert RPS_SIG1. */ 196#define MC2_RPSSIG0_ONq 0x08000800 /* Assert RPS_SIG0. */ 197#define MC2_UPLD_DEBI_MASKq 0x00000002 /* Upload DEBI mask. */ 198#define MC2_UPLD_IIC_MASKq 0x00000001 /* Upload I2C mask. */ 199#define MC2_RPSSIG2_MASKq 0x00002000 /* RPS_SIG2 bit mask. */ 200#define MC2_RPSSIG1_MASKq 0x00001000 /* RPS_SIG1 bit mask. */ 201#define MC2_RPSSIG0_MASKq 0x00000800 /* RPS_SIG0 bit mask. */ 202 203#define MC2_DELAYTRIG_4USq MC2_RPSSIG1_ON 204#define MC2_DELAYBUSY_4USq MC2_RPSSIG1_MASK 205 206#define MC2_DELAYTRIG_6USq MC2_RPSSIG2_ON 207#define MC2_DELAYBUSY_6USq MC2_RPSSIG2_MASK 208 209#define MC2_UPLD_DEBI 0x0002 /* Upload DEBI. */ 210#define MC2_UPLD_IIC 0x0001 /* Upload I2C. */ 211#define MC2_RPSSIG2 0x2000 /* RPS signal 2 (not used). */ 212#define MC2_RPSSIG1 0x1000 /* RPS signal 1 (DAC RPS busy). */ 213#define MC2_RPSSIG0 0x0800 /* RPS signal 0 (ADC RPS busy). */ 214 215#define MC2_ADC_RPS MC2_RPSSIG0 /* ADC RPS busy. */ 216#define MC2_DAC_RPS MC2_RPSSIG1 /* DAC RPS busy. */ 217 218/* ***** oldies ***** */ 219#define MC2_UPLD_DEBIQ 0x00020002 /* Upload DEBI registers. */ 220#define MC2_UPLD_IICQ 0x00010001 /* Upload I2C registers. */ 221 222/* PCI BUS (SAA7146) REGISTER ADDRESS OFFSETS */ 223#define P_PCI_BT_A 0x004C /* Audio DMA burst/threshold control. */ 224#define P_DEBICFG 0x007C /* DEBI configuration. */ 225#define P_DEBICMD 0x0080 /* DEBI command. */ 226#define P_DEBIPAGE 0x0084 /* DEBI page. */ 227#define P_DEBIAD 0x0088 /* DEBI target address. */ 228#define P_I2CCTRL 0x008C /* I2C control. */ 229#define P_I2CSTAT 0x0090 /* I2C status. */ 230#define P_BASEA2_IN 0x00AC /* Audio input 2 base physical DMAbuf 231 * address. */ 232#define P_PROTA2_IN 0x00B0 /* Audio input 2 physical DMAbuf 233 * protection address. */ 234#define P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */ 235#define P_BASEA2_OUT 0x00B8 /* Audio output 2 base physical DMAbuf 236 * address. */ 237#define P_PROTA2_OUT 0x00BC /* Audio output 2 physical DMAbuf 238 * protection address. */ 239#define P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */ 240#define P_RPSPAGE0 0x00C4 /* RPS0 page. */ 241#define P_RPSPAGE1 0x00C8 /* RPS1 page. */ 242#define P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */ 243#define P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */ 244#define P_IER 0x00DC /* Interrupt enable. */ 245#define P_GPIO 0x00E0 /* General-purpose I/O. */ 246#define P_EC1SSR 0x00E4 /* Event counter set 1 source select. */ 247#define P_ECT1R 0x00EC /* Event counter threshold set 1. */ 248#define P_ACON1 0x00F4 /* Audio control 1. */ 249#define P_ACON2 0x00F8 /* Audio control 2. */ 250#define P_MC1 0x00FC /* Master control 1. */ 251#define P_MC2 0x0100 /* Master control 2. */ 252#define P_RPSADDR0 0x0104 /* RPS0 instruction pointer. */ 253#define P_RPSADDR1 0x0108 /* RPS1 instruction pointer. */ 254#define P_ISR 0x010C /* Interrupt status. */ 255#define P_PSR 0x0110 /* Primary status. */ 256#define P_SSR 0x0114 /* Secondary status. */ 257#define P_EC1R 0x0118 /* Event counter set 1. */ 258#define P_ADP4 0x0138 /* Logical audio DMA pointer of audio 259 * input FIFO A2_IN. */ 260#define P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */ 261#define P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */ 262#define P_TSL1 0x0180 /* Audio time slot list 1. */ 263#define P_TSL2 0x01C0 /* Audio time slot list 2. */ 264 265/* LOCAL BUS (GATE ARRAY) REGISTER ADDRESS OFFSETS */ 266/* Analog I/O registers: */ 267#define LP_DACPOL 0x0082 /* Write DAC polarity. */ 268#define LP_GSEL 0x0084 /* Write ADC gain. */ 269#define LP_ISEL 0x0086 /* Write ADC channel select. */ 270/* Digital I/O (write only): */ 271#define LP_WRINTSELA 0x0042 /* Write A interrupt enable. */ 272#define LP_WREDGSELA 0x0044 /* Write A edge selection. */ 273#define LP_WRCAPSELA 0x0046 /* Write A capture enable. */ 274#define LP_WRDOUTA 0x0048 /* Write A digital output. */ 275#define LP_WRINTSELB 0x0052 /* Write B interrupt enable. */ 276#define LP_WREDGSELB 0x0054 /* Write B edge selection. */ 277#define LP_WRCAPSELB 0x0056 /* Write B capture enable. */ 278#define LP_WRDOUTB 0x0058 /* Write B digital output. */ 279#define LP_WRINTSELC 0x0062 /* Write C interrupt enable. */ 280#define LP_WREDGSELC 0x0064 /* Write C edge selection. */ 281#define LP_WRCAPSELC 0x0066 /* Write C capture enable. */ 282#define LP_WRDOUTC 0x0068 /* Write C digital output. */ 283 284/* Digital I/O (read only): */ 285#define LP_RDDINA 0x0040 /* Read digital input. */ 286#define LP_RDCAPFLGA 0x0048 /* Read edges captured. */ 287#define LP_RDINTSELA 0x004A /* Read interrupt enable register. */ 288#define LP_RDEDGSELA 0x004C /* Read edge selection register. */ 289#define LP_RDCAPSELA 0x004E /* Read capture enable register. */ 290#define LP_RDDINB 0x0050 /* Read digital input. */ 291#define LP_RDCAPFLGB 0x0058 /* Read edges captured. */ 292#define LP_RDINTSELB 0x005A /* Read interrupt enable register. */ 293#define LP_RDEDGSELB 0x005C /* Read edge selection register. */ 294#define LP_RDCAPSELB 0x005E /* Read capture enable register. */ 295#define LP_RDDINC 0x0060 /* Read digital input. */ 296#define LP_RDCAPFLGC 0x0068 /* Read edges captured. */ 297#define LP_RDINTSELC 0x006A /* Read interrupt enable register. */ 298#define LP_RDEDGSELC 0x006C /* Read edge selection register. */ 299#define LP_RDCAPSELC 0x006E /* Read capture enable register. */ 300 301/* Counter Registers (read/write): */ 302#define LP_CR0A 0x0000 /* 0A setup register. */ 303#define LP_CR0B 0x0002 /* 0B setup register. */ 304#define LP_CR1A 0x0004 /* 1A setup register. */ 305#define LP_CR1B 0x0006 /* 1B setup register. */ 306#define LP_CR2A 0x0008 /* 2A setup register. */ 307#define LP_CR2B 0x000A /* 2B setup register. */ 308 309/* Counter PreLoad (write) and Latch (read) Registers: */ 310#define LP_CNTR0ALSW 0x000C /* 0A lsw. */ 311#define LP_CNTR0AMSW 0x000E /* 0A msw. */ 312#define LP_CNTR0BLSW 0x0010 /* 0B lsw. */ 313#define LP_CNTR0BMSW 0x0012 /* 0B msw. */ 314#define LP_CNTR1ALSW 0x0014 /* 1A lsw. */ 315#define LP_CNTR1AMSW 0x0016 /* 1A msw. */ 316#define LP_CNTR1BLSW 0x0018 /* 1B lsw. */ 317#define LP_CNTR1BMSW 0x001A /* 1B msw. */ 318#define LP_CNTR2ALSW 0x001C /* 2A lsw. */ 319#define LP_CNTR2AMSW 0x001E /* 2A msw. */ 320#define LP_CNTR2BLSW 0x0020 /* 2B lsw. */ 321#define LP_CNTR2BMSW 0x0022 /* 2B msw. */ 322 323/* Miscellaneous Registers (read/write): */ 324#define LP_MISC1 0x0088 /* Read/write Misc1. */ 325#define LP_WRMISC2 0x0090 /* Write Misc2. */ 326#define LP_RDMISC2 0x0082 /* Read Misc2. */ 327 328/* Bit masks for MISC1 register that are the same for reads and writes. */ 329#define MISC1_WENABLE 0x8000 /* enab writes to MISC2 (except Clear 330 * Watchdog bit). */ 331#define MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */ 332#define MISC1_EDCAP 0x1000 /* enab edge capture on DIO chans 333 * specified by LP_WRCAPSELx. */ 334#define MISC1_NOEDCAP 0x0000 /* Disable edge capture on specified 335 * DIO chans. */ 336 337/* Bit masks for MISC1 register reads. */ 338#define RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */ 339 340/* Bit masks for MISC2 register writes. */ 341#define WRMISC2_WDCLEAR 0x8000 /* Reset watchdog timer to zero. */ 342#define WRMISC2_CHARGE_ENABLE 0x4000 /* enab battery trickle charging. */ 343 344/* Bit masks for MISC2 register that are the same for reads and writes. */ 345#define MISC2_BATT_ENABLE 0x0008 /* Backup battery enable. */ 346#define MISC2_WDENABLE 0x0004 /* Watchdog timer enable. */ 347#define MISC2_WDPERIOD_MASK 0x0003 /* Watchdog interval */ 348 /* select mask. */ 349 350/* Bit masks for ACON1 register. */ 351#define A2_RUN 0x40000000 /* Run A2 based on TSL2. */ 352#define A1_RUN 0x20000000 /* Run A1 based on TSL1. */ 353#define A1_SWAP 0x00200000 /* Use big-endian for A1. */ 354#define A2_SWAP 0x00100000 /* Use big-endian for A2. */ 355#define WS_MODES 0x00019999 /* WS0 = TSL1 trigger */ 356 /* input, WS1-WS4 = */ 357 /* CS* outputs. */ 358 359#if PLATFORM == INTEL /* Base ACON1 config: always run A1 based 360 * on TSL1. */ 361#define ACON1_BASE (WS_MODES | A1_RUN) 362#elif PLATFORM == MOTOROLA 363#define ACON1_BASE (WS_MODES | A1_RUN | A1_SWAP | A2_SWAP) 364#endif 365 366#define ACON1_ADCSTART ACON1_BASE /* Start ADC: run A1 367 * based on TSL1. */ 368#define ACON1_DACSTART (ACON1_BASE | A2_RUN) 369/* Start transmit to DAC: run A2 based on TSL2. */ 370#define ACON1_DACSTOP ACON1_BASE /* Halt A2. */ 371 372/* Bit masks for ACON2 register. */ 373#define A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */ 374#define A2_CLKSRC_X1 0x00800000 /* A2 bit rate = ACLK/1 (DACs). */ 375#define A2_CLKSRC_X2 0x00C00000 /* A2 bit rate = ACLK/2 (DACs). */ 376#define A2_CLKSRC_X4 0x01400000 /* A2 bit rate = ACLK/4 (DACs). */ 377#define INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */ 378#define BCLK2_OE 0x00040000 /* enab BCLK2 (DACs). */ 379#define ACON2_XORMASK 0x000C0000 /* XOR mask for ACON2 */ 380 /* active-low bits. */ 381 382#define ACON2_INIT (ACON2_XORMASK ^ (A1_CLKSRC_BCLK1 | A2_CLKSRC_X2 | INVERT_BCLK2 | BCLK2_OE)) 383 384/* Bit masks for timeslot records. */ 385#define WS1 0x40000000 /* WS output to assert. */ 386#define WS2 0x20000000 387#define WS3 0x10000000 388#define WS4 0x08000000 389#define RSD1 0x01000000 /* Shift A1 data in on SD1. */ 390#define SDW_A1 0x00800000 /* Store rcv'd char at next 391 * char slot of DWORD1 buffer. */ 392#define SIB_A1 0x00400000 /* Store rcv'd char at next 393 * char slot of FB1 buffer. */ 394#define SF_A1 0x00200000 /* Write unsigned long 395 * buffer to input FIFO. */ 396 397/* Select parallel-to-serial converter's data source: */ 398#define XFIFO_0 0x00000000 /* Data fifo byte 0. */ 399#define XFIFO_1 0x00000010 /* Data fifo byte 1. */ 400#define XFIFO_2 0x00000020 /* Data fifo byte 2. */ 401#define XFIFO_3 0x00000030 /* Data fifo byte 3. */ 402#define XFB0 0x00000040 /* FB_BUFFER byte 0. */ 403#define XFB1 0x00000050 /* FB_BUFFER byte 1. */ 404#define XFB2 0x00000060 /* FB_BUFFER byte 2. */ 405#define XFB3 0x00000070 /* FB_BUFFER byte 3. */ 406#define SIB_A2 0x00000200 /* Store next dword from A2's 407 * input shifter to FB2 buffer. */ 408#define SF_A2 0x00000100 /* Store next dword from A2's 409 * input shifter to its input 410 * fifo. */ 411#define LF_A2 0x00000080 /* Load next dword from A2's 412 * output fifo into its 413 * output dword buffer. */ 414#define XSD2 0x00000008 /* Shift data out on SD2. */ 415#define RSD3 0x00001800 /* Shift data in on SD3. */ 416#define RSD2 0x00001000 /* Shift data in on SD2. */ 417#define LOW_A2 0x00000002 /* Drive last SD low */ 418 /* for 7 clks, then */ 419 /* tri-state. */ 420#define EOS 0x00000001 /* End of superframe. */ 421 422/* I2C configuration constants. */ 423#define I2C_CLKSEL 0x0400 424/* I2C bit rate = PCIclk/480 = 68.75 KHz. */ 425 426#define I2C_BITRATE 68.75 427/* I2C bus data bit rate (determined by I2C_CLKSEL) in KHz. */ 428 429#define I2C_WRTIME 15.0 430/* Worst case time, in msec, for EEPROM internal write op. */ 431 432/* I2C manifest constants. */ 433 434/* Max retries to wait for EEPROM write. */ 435#define I2C_RETRIES (I2C_WRTIME * I2C_BITRATE / 9.0) 436#define I2C_ERR 0x0002 /* I2C control/status */ 437 /* flag ERROR. */ 438#define I2C_BUSY 0x0001 /* I2C control/status */ 439 /* flag BUSY. */ 440#define I2C_ABORT 0x0080 /* I2C status flag ABORT. */ 441#define I2C_ATTRSTART 0x3 /* I2C attribute START. */ 442#define I2C_ATTRCONT 0x2 /* I2C attribute CONT. */ 443#define I2C_ATTRSTOP 0x1 /* I2C attribute STOP. */ 444#define I2C_ATTRNOP 0x0 /* I2C attribute NOP. */ 445 446/* I2C read command | EEPROM address. */ 447#define I2CR (devpriv->I2CAdrs | 1) 448 449/* I2C write command | EEPROM address. */ 450#define I2CW (devpriv->I2CAdrs) 451 452/* Code macros used for constructing I2C command bytes. */ 453#define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) 454#define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) 455#define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) 456 457/* oldest */ 458#define P_DEBICFGq 0x007C /* DEBI configuration. */ 459#define P_DEBICMDq 0x0080 /* DEBI command. */ 460#define P_DEBIPAGEq 0x0084 /* DEBI page. */ 461#define P_DEBIADq 0x0088 /* DEBI target address. */ 462 463#define DEBI_CFG_TOQ 0x03C00000 /* timeout (15 PCI cycles) */ 464#define DEBI_CFG_FASTQ 0x10000000 /* fast mode enable */ 465#define DEBI_CFG_16Q 0x00080000 /* 16-bit access enable */ 466#define DEBI_CFG_INCQ 0x00040000 /* enable address increment */ 467#define DEBI_CFG_TIMEROFFQ 0x00010000 /* disable timer */ 468#define DEBI_CMD_RDQ 0x00050000 /* read immediate 2 bytes */ 469#define DEBI_CMD_WRQ 0x00040000 /* write immediate 2 bytes */ 470#define DEBI_PAGE_DISABLEQ 0x00000000 /* paging disable */ 471 472/* DEBI command constants. */ 473#define DEBI_CMD_SIZE16 (2 << 17) /* Transfer size is */ 474 /* always 2 bytes. */ 475#define DEBI_CMD_READ 0x00010000 /* Read operation. */ 476#define DEBI_CMD_WRITE 0x00000000 /* Write operation. */ 477 478/* Read immediate 2 bytes. */ 479#define DEBI_CMD_RDWORD (DEBI_CMD_READ | DEBI_CMD_SIZE16) 480 481/* Write immediate 2 bytes. */ 482#define DEBI_CMD_WRWORD (DEBI_CMD_WRITE | DEBI_CMD_SIZE16) 483 484/* DEBI configuration constants. */ 485#define DEBI_CFG_XIRQ_EN 0x80000000 /* enab external */ 486 /* interrupt on GPIO3. */ 487#define DEBI_CFG_XRESUME 0x40000000 /* Resume block */ 488 /* transfer when XIRQ */ 489 /* deasserted. */ 490#define DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */ 491 492/* 4-bit field that specifies DEBI timeout value in PCI clock cycles: */ 493#define DEBI_CFG_TOUT_BIT 22 /* Finish DEBI cycle after */ 494 /* this many clocks. */ 495 496/* 2-bit field that specifies Endian byte lane steering: */ 497#define DEBI_CFG_SWAP_NONE 0x00000000 /* Straight - don't */ 498 /* swap any bytes */ 499 /* (Intel). */ 500#define DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */ 501#define DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */ 502#define DEBI_CFG_16 0x00080000 /* Slave is able to */ 503 /* serve 16-bit */ 504 /* cycles. */ 505 506#define DEBI_CFG_SLAVE16 0x00080000 /* Slave is able to */ 507 /* serve 16-bit */ 508 /* cycles. */ 509#define DEBI_CFG_INC 0x00040000 /* enab address */ 510 /* increment for block */ 511 /* transfers. */ 512#define DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */ 513#define DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */ 514 515#if PLATFORM == INTEL 516 517#define DEBI_TOUT 7 /* Wait 7 PCI clocks */ 518 /* (212 ns) before */ 519 /* polling RDY. */ 520 521/* Intel byte lane steering (pass through all byte lanes). */ 522#define DEBI_SWAP DEBI_CFG_SWAP_NONE 523 524#elif PLATFORM == MOTOROLA 525 526#define DEBI_TOUT 15 /* Wait 15 PCI clocks (454 ns) */ 527 /* maximum before timing out. */ 528#define DEBI_SWAP DEBI_CFG_SWAP_2 /* Motorola byte lane steering. */ 529 530#endif 531 532/* DEBI page table constants. */ 533#define DEBI_PAGE_DISABLE 0x00000000 /* Paging disable. */ 534 535/* ******* EXTRA FROM OTHER SANSORAY * .h ******* */ 536 537/* LoadSrc values: */ 538#define LOADSRC_INDX 0 /* Preload core in response to */ 539 /* Index. */ 540#define LOADSRC_OVER 1 /* Preload core in response to */ 541 /* Overflow. */ 542#define LOADSRCB_OVERA 2 /* Preload B core in response */ 543 /* to A Overflow. */ 544#define LOADSRC_NONE 3 /* Never preload core. */ 545 546/* IntSrc values: */ 547#define INTSRC_NONE 0 /* Interrupts disabled. */ 548#define INTSRC_OVER 1 /* Interrupt on Overflow. */ 549#define INTSRC_INDX 2 /* Interrupt on Index. */ 550#define INTSRC_BOTH 3 /* Interrupt on Index or Overflow. */ 551 552/* LatchSrc values: */ 553#define LATCHSRC_AB_READ 0 /* Latch on read. */ 554#define LATCHSRC_A_INDXA 1 /* Latch A on A Index. */ 555#define LATCHSRC_B_INDXB 2 /* Latch B on B Index. */ 556#define LATCHSRC_B_OVERA 3 /* Latch B on A Overflow. */ 557 558/* IndxSrc values: */ 559#define INDXSRC_HARD 0 /* Hardware or software index. */ 560#define INDXSRC_SOFT 1 /* Software index only. */ 561 562/* IndxPol values: */ 563#define INDXPOL_POS 0 /* Index input is active high. */ 564#define INDXPOL_NEG 1 /* Index input is active low. */ 565 566/* ClkSrc values: */ 567#define CLKSRC_COUNTER 0 /* Counter mode. */ 568#define CLKSRC_TIMER 2 /* Timer mode. */ 569#define CLKSRC_EXTENDER 3 /* Extender mode. */ 570 571/* ClkPol values: */ 572#define CLKPOL_POS 0 /* Counter/Extender clock is */ 573 /* active high. */ 574#define CLKPOL_NEG 1 /* Counter/Extender clock is */ 575 /* active low. */ 576#define CNTDIR_UP 0 /* Timer counts up. */ 577#define CNTDIR_DOWN 1 /* Timer counts down. */ 578 579/* ClkEnab values: */ 580#define CLKENAB_ALWAYS 0 /* Clock always enabled. */ 581#define CLKENAB_INDEX 1 /* Clock is enabled by index. */ 582 583/* ClkMult values: */ 584#define CLKMULT_4X 0 /* 4x clock multiplier. */ 585#define CLKMULT_2X 1 /* 2x clock multiplier. */ 586#define CLKMULT_1X 2 /* 1x clock multiplier. */ 587 588/* Bit Field positions in COUNTER_SETUP structure: */ 589#define BF_LOADSRC 9 /* Preload trigger. */ 590#define BF_INDXSRC 7 /* Index source. */ 591#define BF_INDXPOL 6 /* Index polarity. */ 592#define BF_CLKSRC 4 /* Clock source. */ 593#define BF_CLKPOL 3 /* Clock polarity/count direction. */ 594#define BF_CLKMULT 1 /* Clock multiplier. */ 595#define BF_CLKENAB 0 /* Clock enable. */ 596 597/* Enumerated counter operating modes specified by ClkSrc bit field in */ 598/* a COUNTER_SETUP. */ 599 600#define CLKSRC_COUNTER 0 /* Counter: ENC_C clock, ENC_D */ 601 /* direction. */ 602#define CLKSRC_TIMER 2 /* Timer: SYS_C clock, */ 603 /* direction specified by */ 604 /* ClkPol. */ 605#define CLKSRC_EXTENDER 3 /* Extender: OVR_A clock, */ 606 /* ENC_D direction. */ 607 608/* Enumerated counter clock multipliers. */ 609 610#define MULT_X0 0x0003 /* Supports no multipliers; */ 611 /* fixed physical multiplier = */ 612 /* 3. */ 613#define MULT_X1 0x0002 /* Supports multiplier x1; */ 614 /* fixed physical multiplier = */ 615 /* 2. */ 616#define MULT_X2 0x0001 /* Supports multipliers x1, */ 617 /* x2; physical multipliers = */ 618 /* 1 or 2. */ 619#define MULT_X4 0x0000 /* Supports multipliers x1, */ 620 /* x2, x4; physical */ 621 /* multipliers = 0, 1 or 2. */ 622 623/* Sanity-check limits for parameters. */ 624 625#define NUM_COUNTERS 6 /* Maximum valid counter */ 626 /* logical channel number. */ 627#define NUM_INTSOURCES 4 628#define NUM_LATCHSOURCES 4 629#define NUM_CLKMULTS 4 630#define NUM_CLKSOURCES 4 631#define NUM_CLKPOLS 2 632#define NUM_INDEXPOLS 2 633#define NUM_INDEXSOURCES 2 634#define NUM_LOADTRIGS 4 635 636/* Bit field positions in CRA and CRB counter control registers. */ 637 638/* Bit field positions in CRA: */ 639#define CRABIT_INDXSRC_B 14 /* B index source. */ 640#define CRABIT_CLKSRC_B 12 /* B clock source. */ 641#define CRABIT_INDXPOL_A 11 /* A index polarity. */ 642#define CRABIT_LOADSRC_A 9 /* A preload trigger. */ 643#define CRABIT_CLKMULT_A 7 /* A clock multiplier. */ 644#define CRABIT_INTSRC_A 5 /* A interrupt source. */ 645#define CRABIT_CLKPOL_A 4 /* A clock polarity. */ 646#define CRABIT_INDXSRC_A 2 /* A index source. */ 647#define CRABIT_CLKSRC_A 0 /* A clock source. */ 648 649/* Bit field positions in CRB: */ 650#define CRBBIT_INTRESETCMD 15 /* Interrupt reset command. */ 651#define CRBBIT_INTRESET_B 14 /* B interrupt reset enable. */ 652#define CRBBIT_INTRESET_A 13 /* A interrupt reset enable. */ 653#define CRBBIT_CLKENAB_A 12 /* A clock enable. */ 654#define CRBBIT_INTSRC_B 10 /* B interrupt source. */ 655#define CRBBIT_LATCHSRC 8 /* A/B latch source. */ 656#define CRBBIT_LOADSRC_B 6 /* B preload trigger. */ 657#define CRBBIT_CLKMULT_B 3 /* B clock multiplier. */ 658#define CRBBIT_CLKENAB_B 2 /* B clock enable. */ 659#define CRBBIT_INDXPOL_B 1 /* B index polarity. */ 660#define CRBBIT_CLKPOL_B 0 /* B clock polarity. */ 661 662/* Bit field masks for CRA and CRB. */ 663 664#define CRAMSK_INDXSRC_B ((uint16_t)(3 << CRABIT_INDXSRC_B)) 665#define CRAMSK_CLKSRC_B ((uint16_t)(3 << CRABIT_CLKSRC_B)) 666#define CRAMSK_INDXPOL_A ((uint16_t)(1 << CRABIT_INDXPOL_A)) 667#define CRAMSK_LOADSRC_A ((uint16_t)(3 << CRABIT_LOADSRC_A)) 668#define CRAMSK_CLKMULT_A ((uint16_t)(3 << CRABIT_CLKMULT_A)) 669#define CRAMSK_INTSRC_A ((uint16_t)(3 << CRABIT_INTSRC_A)) 670#define CRAMSK_CLKPOL_A ((uint16_t)(3 << CRABIT_CLKPOL_A)) 671#define CRAMSK_INDXSRC_A ((uint16_t)(3 << CRABIT_INDXSRC_A)) 672#define CRAMSK_CLKSRC_A ((uint16_t)(3 << CRABIT_CLKSRC_A)) 673 674#define CRBMSK_INTRESETCMD ((uint16_t)(1 << CRBBIT_INTRESETCMD)) 675#define CRBMSK_INTRESET_B ((uint16_t)(1 << CRBBIT_INTRESET_B)) 676#define CRBMSK_INTRESET_A ((uint16_t)(1 << CRBBIT_INTRESET_A)) 677#define CRBMSK_CLKENAB_A ((uint16_t)(1 << CRBBIT_CLKENAB_A)) 678#define CRBMSK_INTSRC_B ((uint16_t)(3 << CRBBIT_INTSRC_B)) 679#define CRBMSK_LATCHSRC ((uint16_t)(3 << CRBBIT_LATCHSRC)) 680#define CRBMSK_LOADSRC_B ((uint16_t)(3 << CRBBIT_LOADSRC_B)) 681#define CRBMSK_CLKMULT_B ((uint16_t)(3 << CRBBIT_CLKMULT_B)) 682#define CRBMSK_CLKENAB_B ((uint16_t)(1 << CRBBIT_CLKENAB_B)) 683#define CRBMSK_INDXPOL_B ((uint16_t)(1 << CRBBIT_INDXPOL_B)) 684#define CRBMSK_CLKPOL_B ((uint16_t)(1 << CRBBIT_CLKPOL_B)) 685 686#define CRBMSK_INTCTRL (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A | CRBMSK_INTRESET_B) /* Interrupt reset control bits. */ 687 688/* Bit field positions for standardized SETUP structure. */ 689 690#define STDBIT_INTSRC 13 691#define STDBIT_LATCHSRC 11 692#define STDBIT_LOADSRC 9 693#define STDBIT_INDXSRC 7 694#define STDBIT_INDXPOL 6 695#define STDBIT_CLKSRC 4 696#define STDBIT_CLKPOL 3 697#define STDBIT_CLKMULT 1 698#define STDBIT_CLKENAB 0 699 700/* Bit field masks for standardized SETUP structure. */ 701 702#define STDMSK_INTSRC ((uint16_t)(3 << STDBIT_INTSRC)) 703#define STDMSK_LATCHSRC ((uint16_t)(3 << STDBIT_LATCHSRC)) 704#define STDMSK_LOADSRC ((uint16_t)(3 << STDBIT_LOADSRC)) 705#define STDMSK_INDXSRC ((uint16_t)(1 << STDBIT_INDXSRC)) 706#define STDMSK_INDXPOL ((uint16_t)(1 << STDBIT_INDXPOL)) 707#define STDMSK_CLKSRC ((uint16_t)(3 << STDBIT_CLKSRC)) 708#define STDMSK_CLKPOL ((uint16_t)(1 << STDBIT_CLKPOL)) 709#define STDMSK_CLKMULT ((uint16_t)(3 << STDBIT_CLKMULT)) 710#define STDMSK_CLKENAB ((uint16_t)(1 << STDBIT_CLKENAB)) 711 712struct bufferDMA { 713 dma_addr_t PhysicalBase; 714 void *LogicalBase; 715 uint32_t DMAHandle; 716}; 717